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soc/intel/skylake: Remove pch_enable_dev() from SoC

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PCI resources MMIO space/bus master enabling is handled inside
pch_dev_enable_resources() from common device code. Hence
no need to have an explicit soc function to do the same.

TEST=lspci from kernel console shows same pci device list
without and without this patch.

Change-Id: I005e486dd435e9c61ae3f5dfe3ff0e8f688d16e1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Subrata Banik
2017-12-06 18:14:01 +05:30
parent 578a79d500
commit 3c838c7399
5 changed files with 4 additions and 54 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
src/soc/intel/skylake/chip_fsp20.c
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@@ -74,17 +74,10 @@ static struct device_operations cpu_bus_ops = {
static void soc_enable(device_t dev)
{
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
if (dev->path.type == DEVICE_PATH_DOMAIN)
dev->ops = &pci_domain_ops;
} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
dev->ops = &cpu_bus_ops;
} else if (dev->path.type == DEVICE_PATH_PCI) {
/* Handle PCH device enable */
if (PCI_SLOT(dev->path.pci.devfn) > SA_DEV_SLOT_IGD &&
(dev->ops == NULL || dev->ops->enable == NULL)) {
pch_enable_dev(dev);
}
}
}
struct chip_operations soc_intel_skylake_ops = {