sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Revert deletion of src/arch/i386/init.

Browse Source 
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5132 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Patrick Georgi
2010-02-19 19:59:03 +00:00
parent 8e9234ffff
commit 3c970eee2a
11 changed files with 983 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/arch/i386/init/Makefile.inc Normal file
View File

@@ -0,0 +1 @@
# If you add something to this file, enable it in src/arch/i386/Makefile.inc first.

47
src/arch/i386/init/bootblock.c Normal file
View File

@@ -0,0 +1,47 @@
#define __PRE_RAM__
#if CONFIG_LOGICAL_CPUS && \
(defined(CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT) || defined(CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT))
#include <cpu/x86/lapic/boot_cpu.c>
#else
#define boot_cpu(x) 1
#endif
#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT
#else
static void bootblock_northbridge_init(void) { }
#endif
#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT
#else
static void bootblock_southbridge_init(void) { }
#endif
static unsigned long findstage(char* target)
{
unsigned long entry;
asm volatile (
"mov $1f, %%esp\n\t"
"jmp walkcbfs\n\t"
"1:\n\t" : "=a" (entry) : "S" (target) : "ebx", "ecx", "edi", "esp");
return entry;
}
static void call(unsigned long addr, unsigned long bist)
{
asm volatile ("jmp *%0\n\t" : : "r" (addr), "a" (bist));
}
static void main(unsigned long bist)
{
if (boot_cpu()) {
bootblock_northbridge_init();
bootblock_southbridge_init();
}
const char* target1 = "fallback/romstage";
unsigned long entry;
entry = findstage(target1);
if (entry) call(entry, bist);
asm volatile ("1:\n\thlt\n\tjmp 1b\n\t");
}

37
src/arch/i386/init/bootblock_prologue.c Normal file
View File

@@ -0,0 +1,37 @@
/* -*- asm -*-
* $ $
*
*/
/*
* Copyright (C) 1996-2002 Markus Franz Xaver Johannes Oberhumer
*
* This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* Originally this code was part of ucl the data compression library
* for upx the ``Ultimate Packer of eXecutables''.
*
* - Converted to gas assembly, and refitted to work with etherboot.
* Eric Biederman 20 Aug 2002
* - Merged the nrv2b decompressor into crt0.base of coreboot
* Eric Biederman 26 Sept 2002
*/
#include <arch/asm.h>
#include <arch/intel.h>
#include <console/loglevel.h>
/*
* This is the entry code the code in .reset section
* jumps to this address.
*
*/
.section ".rom.data", "a", @progbits
.section ".rom.text", "ax", @progbits
intel_chip_post_macro(0x01) /* delay for chipsets */

363
src/arch/i386/init/car.S Normal file
View File

@@ -0,0 +1,363 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
* Copyright (C) 2005 Eswar Nallusamy, LANL
* Copyright (C) 2005 Tyan
* (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
* Copyright (C) 2007 coresystems GmbH
* (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
* Copyright (C) 2008 Carl-Daniel Hailfinger
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* Init code - Switch CPU to protected mode and enable Cache-as-Ram (CAR). */
#include <arch/intel.h>
#define ROM_CODE_SEG 0x08
#define ROM_DATA_SEG 0x10
#define CACHE_RAM_CODE_SEG 0x18
#define CACHE_RAM_DATA_SEG 0x20
/* When we come here we are in protected mode. We expand the stack
* and copy the data segment from ROM to the memory.
*
* After that, we call the chipset bootstrap routine that
* does what is left of the chipset initialization.
*
* NOTE: Aligned to 4 so that we are sure that the prefetch
* cache will be reloaded.
*/
.section .rom.text
.align 4
.globl protected_stage0
protected_stage0:
lgdt %cs:gdtptr
ljmp $ROM_CODE_SEG, $__protected_stage0
.globl __protected_stage0
__protected_stage0:
/* Save the BIST result. */
movl %eax, %ebp
intel_chip_post_macro(0x01)
movw $ROM_DATA_SEG, %ax
movw %ax, %ds
movw %ax, %es
movw %ax, %ss
movw %ax, %fs
movw %ax, %gs
/* Restore the BIST value to %eax. */
movl %ebp, %eax
.align 4
/* disable HyperThreading is done by eswar
* the other is very similar to the AMD CAR, except remove amd specific msr
*/
#define CacheSize CONFIG_DCACHE_RAM_SIZE
#define CacheBase CONFIG_DCACHE_RAM_BASE
#include <cpu/x86/mtrr.h>
/* Save the BIST result */
movl %eax, %ebp
CacheAsRam:
/* Check whether the processor has HT capability */
movl $01, %eax
cpuid
btl $28, %edx
jnc NotHtProcessor
bswapl %ebx
cmpb $01, %bh
jbe NotHtProcessor
/* It is a HT processor; Send SIPI to the other logical processor
* within this processor so that the CAR related common system
* registers are programmed accordingly
*/
/* Use some register that is common to both logical processors
* as semaphore. Refer Appendix B, Vol.3
*/
xorl %eax, %eax
xorl %edx, %edx
movl $0x250, %ecx
wrmsr
/* Figure out the logical AP's APIC ID; the following logic will work
* only for processors with 2 threads.
*
* Refer to Vol 3. Table 7-1 for details about this logic
*/
movl $0xFEE00020, %esi
movl (%esi), %ebx
andl $0xFF000000, %ebx
bswapl %ebx
btl $0, %ebx
jnc LogicalAP0
andb $0xFE, %bl
jmp SendSIPI
LogicalAP0:
orb $0x01, %bl
SendSIPI:
bswapl %ebx /* ebx - logical AP's APIC ID */
/* Fill up the IPI command registers in the Local APIC mapped to
* default address and issue SIPI to the other logical processor
* within this processor die.
*/
RetrySIPI:
movl %ebx, %eax
movl $0xFEE00310, %esi
movl %eax, (%esi)
/* SIPI vector - F900:0000 */
movl $0x000006F9, %eax
movl $0xFEE00300, %esi
movl %eax, (%esi)
movl $0x30, %ecx
SIPIDelay:
pause
decl %ecx
jnz SIPIDelay
movl (%esi), %eax
andl $0x00001000, %eax
jnz RetrySIPI
/* Wait for the Logical AP to complete initialization */
LogicalAPSIPINotdone:
movl $0x250, %ecx
rdmsr
orl %eax, %eax
jz LogicalAPSIPINotdone
NotHtProcessor:
/* Set the default memory type and enable fixed and variable MTRRs */
movl $MTRRdefType_MSR, %ecx
xorl %edx, %edx
/* Enable Variable and Fixed MTRRs */
movl $0x00000c00, %eax
wrmsr
/* Clear all MTRRs */
xorl %edx, %edx
movl $fixed_mtrr_msr, %esi
clear_fixed_var_mtrr:
lodsl (%esi), %eax
testl %eax, %eax
jz clear_fixed_var_mtrr_out
movl %eax, %ecx
xorl %eax, %eax
wrmsr
jmp clear_fixed_var_mtrr
clear_fixed_var_mtrr_out:
/* 0x06 is the WB IO type for a given 4k segment.
* segs is the number of 4k segments in the area of the particular
* register we want to use for CAR.
* reg is the register where the IO type should be stored.
*/
.macro extractmask segs, reg
.if \segs <= 0
/* The xorl here is superfluous because at the point of first execution
* of this macro, %eax and %edx are cleared. Later invocations of this
* macro will have a monotonically increasing segs parameter.
*/
xorl \reg, \reg
.elseif \segs == 1
movl $0x06000000, \reg /* WB IO type */
.elseif \segs == 2
movl $0x06060000, \reg /* WB IO type */
.elseif \segs == 3
movl $0x06060600, \reg /* WB IO type */
.elseif \segs >= 4
movl $0x06060606, \reg /* WB IO type */
.endif
.endm
/* size is the cache size in bytes we want to use for CAR.
* windowoffset is the 32k-aligned window into CAR size
*/
.macro simplemask carsize, windowoffset
/* DO NOT CHANGE THE FORMATTING of the two lines below! Whitespace is
* interpreted as an argument delimiter by some versions of GNU as. */
extractmask (((\carsize-\windowoffset)/0x1000)-4), %eax
extractmask (((\carsize-\windowoffset)/0x1000)), %edx
.endm
#if CacheSize > 0x10000
#error Invalid CAR size, must be at most 64k.
#endif
#if CacheSize < 0x1000
#error Invalid CAR size, must be at least 4k. This is a processor limitation.
#endif
#if (CacheSize & (0x1000 - 1))
#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation.
#endif
#if CacheSize > 0x8000
/* enable caching for 32K-64K using fixed mtrr */
movl $0x268, %ecx /* fix4k_c0000*/
simplemask CacheSize, 0x8000
wrmsr
#endif
/* enable caching for 0-32K using fixed mtrr */
movl $0x269, %ecx /* fix4k_c8000*/
simplemask CacheSize, 0
wrmsr
#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
#else
#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
#endif
/* enable write base caching so we can do execute in place
* on the flash rom.
*/
movl $0x202, %ecx
xorl %edx, %edx
movl $REAL_XIP_ROM_BASE, %eax
orl $MTRR_TYPE_WRBACK, %eax
wrmsr
movl $0x203, %ecx
movl $0x0000000f, %edx
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
wrmsr
#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
/* enable cache */
movl %cr0, %eax
andl $0x9fffffff,%eax
movl %eax, %cr0
/* Read the range with lodsl*/
movl $CacheBase, %esi
cld
movl $(CacheSize>>2), %ecx
rep lodsl
/* Clear the range */
movl $CacheBase, %edi
movl $(CacheSize>>2), %ecx
xorl %eax, %eax
rep stosl
/* TODO: make this a config variable */
#if CARTEST
/* check the cache as ram */
movl $CacheBase, %esi
movl $(CacheSize>>2), %ecx
.xin1:
movl %esi, %eax
movl %eax, (%esi)
decl %ecx
je .xout1
add $4, %esi
jmp .xin1
.xout1:
movl $CacheBase, %esi
// movl $(CacheSize>>2), %ecx
movl $4, %ecx
.xin1x:
movl %esi, %eax
movl $0x4000, %edx
movb %ah, %al
.testx1:
outb %al, $0x80
decl %edx
jnz .testx1
movl (%esi), %eax
cmpb 0xff, %al
je .xin2 /* dont show */
movl $0x4000, %edx
.testx2:
outb %al, $0x80
decl %edx
jnz .testx2
.xin2: decl %ecx
je .xout1x
add $4, %esi
jmp .xin1x
.xout1x:
#endif
movl $(CacheBase+CacheSize-4), %eax
movl %eax, %esp
/* Load a different set of data segments */
movw $CACHE_RAM_DATA_SEG, %ax
movw %ax, %ds
movw %ax, %es
movw %ax, %ss
lout:
/* Store zero for the pointer to the global variables. */
pushl $0
/* Restore the BIST result. */
movl %ebp, %eax
/* We need to set ebp? No need. */
movl %esp, %ebp
/* Third parameter: cpu #: 0 == BSP all other are APs.
* 0 until SMP support is added.
*/
pushl $0
/* Second parameter: init_detected */
/* Store zero for the unused init_detected parameter. */
pushl $0
/* First parameter: bist */
pushl %eax
call main
/* We will not go back. */
fixed_mtrr_msr:
.long 0x250, 0x258, 0x259
.long 0x268, 0x269, 0x26A
.long 0x26B, 0x26C, 0x26D
.long 0x26E, 0x26F
var_mtrr_msr:
.long 0x200, 0x201, 0x202, 0x203
.long 0x204, 0x205, 0x206, 0x207
.long 0x208, 0x209, 0x20A, 0x20B
.long 0x20C, 0x20D, 0x20E, 0x20F
.long 0x000 /* NULL, end of table */

143
src/arch/i386/init/crt0.S.lb Normal file
View File

@@ -0,0 +1,143 @@
/* -*- asm -*-
* $ $
*
*/
/*
* Copyright (C) 1996-2002 Markus Franz Xaver Johannes Oberhumer
*
* This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* Originally this code was part of ucl the data compression library
* for upx the ``Ultimate Packer of eXecutables''.
*
* - Converted to gas assembly, and refitted to work with etherboot.
* Eric Biederman 20 Aug 2002
* - Merged the nrv2b decompressor into crt0.base of coreboot
* Eric Biederman 26 Sept 2002
*/
#include <arch/asm.h>
#include <arch/intel.h>
#include <console/loglevel.h>
/*
* This is the entry code the code in .reset section
* jumps to this address.
*
*/
.section ".rom.data", "a", @progbits
.section ".rom.text", "ax", @progbits
intel_chip_post_macro(0x01) /* delay for chipsets */
#include "crt0_includes.h"
#if CONFIG_USE_DCACHE_RAM == 0
#ifndef CONSOLE_DEBUG_TX_STRING
/* uses: esp, ebx, ax, dx */
# define __CRT_CONSOLE_TX_STRING(string) \
mov string, %ebx ; \
CALLSP(crt_console_tx_string)
# if defined(CONFIG_TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
# define CONSOLE_DEBUG_TX_STRING(string) __CRT_CONSOLE_TX_STRING(string)
# else
# define CONSOLE_DEBUG_TX_STRING(string)
# endif
#endif
/* clear boot_complete flag */
xorl %ebp, %ebp
__main:
CONSOLE_DEBUG_TX_STRING($str_copying_to_ram)
/*
* Copy data into RAM and clear the BSS. Since these segments
* isn\'t really that big we just copy/clear using bytes, not
* double words.
*/
intel_chip_post_macro(0x11) /* post 11 */
cld /* clear direction flag */
/* copy coreboot from it's initial load location to
* the location it is compiled to run at.
* Normally this is copying from FLASH ROM to RAM.
*/
movl %ebp, %esi
/* FIXME: look for a proper place for the stack */
movl $0x4000000, %esp
movl %esp, %ebp
pushl %esi
pushl $str_coreboot_ram_name
call cbfs_and_run_core
.Lhlt:
intel_chip_post_macro(0xee) /* post fe */
hlt
jmp .Lhlt
#ifdef __CRT_CONSOLE_TX_STRING
/* Uses esp, ebx, ax, dx */
crt_console_tx_string:
mov (%ebx), %al
inc %ebx
cmp $0, %al
jne 9f
RETSP
9:
/* Base Address */
#ifndef CONFIG_TTYS0_BASE
#define CONFIG_TTYS0_BASE 0x3f8
#endif
/* Data */
#define TTYS0_RBR (CONFIG_TTYS0_BASE+0x00)
/* Control */
#define TTYS0_TBR TTYS0_RBR
#define TTYS0_IER (CONFIG_TTYS0_BASE+0x01)
#define TTYS0_IIR (CONFIG_TTYS0_BASE+0x02)
#define TTYS0_FCR TTYS0_IIR
#define TTYS0_LCR (CONFIG_TTYS0_BASE+0x03)
#define TTYS0_MCR (CONFIG_TTYS0_BASE+0x04)
#define TTYS0_DLL TTYS0_RBR
#define TTYS0_DLM TTYS0_IER
/* Status */
#define TTYS0_LSR (CONFIG_TTYS0_BASE+0x05)
#define TTYS0_MSR (CONFIG_TTYS0_BASE+0x06)
#define TTYS0_SCR (CONFIG_TTYS0_BASE+0x07)
mov %al, %ah
10: mov $TTYS0_LSR, %dx
inb %dx, %al
test $0x20, %al
je 10b
mov $TTYS0_TBR, %dx
mov %ah, %al
outb %al, %dx
jmp crt_console_tx_string
#endif /* __CRT_CONSOLE_TX_STRING */
#if defined(CONSOLE_DEBUG_TX_STRING) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
.section ".rom.data"
#if CONFIG_COMPRESS
str_copying_to_ram: .string "Uncompressing coreboot to RAM.\r\n"
#else
str_copying_to_ram: .string "Copying coreboot to RAM.\r\n"
#endif
str_pre_main: .string "Jumping to coreboot.\r\n"
.previous
#endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */
str_coreboot_ram_name: .ascii CONFIG_CBFS_PREFIX
.string "/coreboot_ram"
#endif /* CONFIG_USE_DCACHE_RAM */

156
src/arch/i386/init/entry.S Normal file
View File

@@ -0,0 +1,156 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 1999 Ronald G. Minnich
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/rom_segs.h>
.code16
.globl _stage0
_stage0:
cli
/* Save the BIST result. */
movl %eax, %ebp;
/* thanks to kmliu@sis.com.tw for this TLB fix */
/* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before
* executing any further code. Even though paging is disabled we
* could still get false address translations due to the TLB if we
* didn't invalidate it.
*/
xorl %eax, %eax
movl %eax, %cr3 /* Invalidate TLB. */
/* Switch to protected mode. */
/* NOTE: With GNU assembler version 2.15.94.0.2.2 (i386-redhat-linux)
* using BFD version 2.15.94.0.2.2 20041220 this works fine without all
* the ld hackery and other things. So leave it as is with this comment.
*/
data32 lgdt %cs:gdtptr
movl %cr0, %eax
andl $0x7FFAFFD1, %eax /* PG, AM, WP, NE, TS, EM, MP = 0 */
orl $0x60000001, %eax /* CD, NW, PE = 1 */
movl %eax, %cr0
/* Restore BIST result. */
movl %ebp, %eax
// port80_post(0x23)
/* Now we are in protected mode. Jump to a 32 bit code segment. */
data32 ljmp $ROM_CODE_SEG, $protected_stage0
/* I am leaving this weird jump in here in the event that future gas
* bugs force it to be used.
*/
/* .byte 0x66 */
.code32
/* ljmp $ROM_CODE_SEG, $protected_stage0 */
/* .code16 */
.align 4
.globl gdt16
gdt16 = . - _stage0
gdt16x:
.word gdt16xend - gdt16x -1 /* Compute the table limit. */
.long gdt16x
.word 0
/* selgdt 0x08, flat code segment */
.word 0xffff, 0x0000
.byte 0x00, 0x9b, 0xcf, 0x00
/* selgdt 0x10, flat data segment */
.word 0xffff, 0x0000
.byte 0x00, 0x93, 0xcf, 0x00
gdt16xend:
/* From now on we are 32 bit. */
.code32
/* We have two gdts where we could have one. That is ok.
*
* Let's not worry about this -- optimizing gdt is pointless since
* we're only in it for a little bit.
*
* Btw. note the trick below: The GDT points to ITSELF, and the first
* good descriptor is at offset 8. So you word-align the table, and
* then because you chose 8, you get a nice 64-bit aligned GDT entry,
* which is good as this is the size of the entry.
* Just in case you ever wonder why people do this.
*/
.align 4
.globl gdtptr
.globl gdt_limit
gdt_limit = gdt_end - gdt - 1 /* Compute the table limit. */
gdt:
gdtptr:
.word gdt_end - gdt -1 /* Compute the table limit. */
.long gdt /* We know the offset. */
.word 0
/* selgdt 0x08, flat code segment */
.word 0xffff, 0x0000
.byte 0x00, 0x9b, 0xcf, 0x00
/* selgdt 0x10, flat data segment */
.word 0xffff, 0x0000
.byte 0x00, 0x93, 0xcf, 0x00
/* selgdt 0x18, flat code segment for CAR */
.word 0xffff, 0x0000
.byte 0x00, 0x9b, 0xcf, 0x00
/* selgdt 0x20, flat data segment for CAR */
.word 0xffff, 0x0000
.byte 0x00, 0x93, 0xcf, 0x00
gdt_end:
/* Reset vector. */
/*
* RVECTOR: Size of reset vector, default is 0x10.
* RESRVED: Size of vpd code, default is 0xf0.
* BOOTBLK: Size of bootblock code, default is 0x1f00 (8k-256b).
*/
SEGMENT_SIZE = 0x10000
RVECTOR = 0x00010
/* Due to YET ANOTHER BUG in GNU bintools, you can NOT have a code16 here.
* I think we should leave it this way forever, as the bugs come and
* go -- and come again.
*
* .code16
* .section ".rom.text"
*/
.section ".reset", "ax"
.globl _resetjump
_resetjump:
/* GNU bintools bugs again. This jumps to stage0 - 2. Sigh. */
/* jmp _stage0 */
.byte 0xe9
.int _stage0 - ( . + 2 )
/* Note: The above jump is hand coded to work around bugs in binutils.
* 5 bytes are used for a 3 byte instruction. This works because x86
* is little endian and allows us to use supported 32 bit relocations
* instead of the weird 16 bit relocations that binutils does not
* handle consistenly between versions because they are used so rarely.
*/

40
src/arch/i386/init/ldscript.ld Normal file
View File

@@ -0,0 +1,40 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
TARGET(binary)
SECTIONS
{
/DISCARD/ : {
*(.comment)
*(.note.*)
*(.note)
}
}
SECTIONS {
_ROMTOP = 0xfffffff0;
. = _ROMTOP;
.resetvector . : {
*(.reset)
. = 15 ;
BYTE(0x00);
}
}

13
src/arch/i386/init/ldscript_apc.lb Normal file
View File

@@ -0,0 +1,13 @@
INPUT(coreboot_apc.rom)
SECTIONS
{
.apcrom . : {
_apcrom = .;
coreboot_apc.rom(*)
_eapcrom = .;
}
_iseg_apc = CONFIG_DCACHE_RAM_BASE;
_eiseg_apc = _iseg_apc + SIZEOF(.apcrom);
_liseg_apc = _apcrom;
_eliseg_apc = _eapcrom;
}

59
src/arch/i386/init/ldscript_cbfs.lb Normal file
View File

@@ -0,0 +1,59 @@
/*
* Memory map:
*
* CONFIG_RAMBASE
* : data segment
* : bss segment
* : heap
* : stack
* CONFIG_ROMBASE
* : coreboot text
* : readonly text
*/
/*
* Bootstrap code for the STPC Consumer
* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
*
*/
/*
* Written by Johan Rydberg, based on work by Daniel Kahlin.
* Rewritten by Eric Biederman
*/
/*
* We use ELF as output format. So that we can
* debug the code in some form.
*/
OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
OUTPUT_ARCH(i386)
/*
ENTRY(_start)
*/
TARGET(binary)
SECTIONS
{
. = CONFIG_ROMBASE;
/* This section might be better named .setup */
.rom . : {
_rom = .;
*(.rom.text);
*(.rom.data);
*(.rodata.*);
*(.rom.data.*);
. = ALIGN(16);
_erom = .;
}
_lrom = LOADADDR(.rom);
_elrom = LOADADDR(.rom) + SIZEOF(.rom);
/DISCARD/ : {
*(.comment)
*(.comment.*)
*(.note)
*(.note.*)
}
}

59
src/arch/i386/init/ldscript_failover.lb Normal file
View File

@@ -0,0 +1,59 @@
/*
* Memory map:
*
* CONFIG_RAMBASE
* : data segment
* : bss segment
* : heap
* : stack
* CONFIG_ROMBASE
* : coreboot text
* : readonly text
*/
/*
* Bootstrap code for the STPC Consumer
* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
*
*/
/*
* Written by Johan Rydberg, based on work by Daniel Kahlin.
* Rewritten by Eric Biederman
*/
/*
* We use ELF as output format. So that we can
* debug the code in some form.
*/
OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
OUTPUT_ARCH(i386)
/*
ENTRY(_start)
*/
TARGET(binary)
SECTIONS
{
. = CONFIG_ROMBASE;
/* This section might be better named .setup */
.rom . : {
_rom = .;
*(.rom.text);
*(.rom.data);
*(.rom.data.*);
*(.rodata.*);
. = ALIGN(16);
_erom = .;
}
_lrom = LOADADDR(.rom);
_elrom = LOADADDR(.rom) + SIZEOF(.rom);
/DISCARD/ : {
*(.comment)
*(.note)
*(.comment.*)
*(.note.*)
}
}

65
src/arch/i386/init/ldscript_fallback_cbfs.lb Normal file
View File

@@ -0,0 +1,65 @@
/*
* Memory map:
*
* CONFIG_RAMBASE
* : data segment
* : bss segment
* : heap
* : stack
* CONFIG_ROMBASE
* : coreboot text
* : readonly text
*/
/*
* Bootstrap code for the STPC Consumer
* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
*
*/
/*
* Written by Johan Rydberg, based on work by Daniel Kahlin.
* Rewritten by Eric Biederman
*/
/*
* We use ELF as output format. So that we can
* debug the code in some form.
*/
OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
OUTPUT_ARCH(i386)
/*
ENTRY(_start)
*/
TARGET(binary)
SECTIONS
{
. = CONFIG_ROMBASE;
/* cut _start into last 64k*/
_x = .;
. = (_x < (CONFIG_ROMBASE - 0x10000 + CONFIG_ROM_IMAGE_SIZE)) ? (CONFIG_ROMBASE - 0x10000 + CONFIG_ROM_IMAGE_SIZE) : _x;
/* This section might be better named .setup */
.rom . : {
_rom = .;
*(.rom.text);
*(.rom.data);
*(.init.rodata.*);
*(.init.text);
*(.rodata.*);
*(.rom.data.*);
. = ALIGN(16);
_erom = .;
}
_lrom = LOADADDR(.rom);
_elrom = LOADADDR(.rom) + SIZEOF(.rom);
/DISCARD/ : {
*(.comment)
*(.note)
*(.comment.*)
*(.note.*)
}
}