mb/google/rex: Update FMD to incorporate ISH firmware

This patch adds two new chromeos_*.fmd files for release and debug FSP
builds targeting rex_ec_ish.

`rex_ec_ish` variant would pack ISH firmware into the CSE boot partition
hence, the blob size is expected to increase. Creates separate flash map
layout to ensure ISH work is not impacting on the regular `rex0` project
SPI flash usage.

BUG=b:284254353
TEST=Able to build google/rex_ish_ec board and boot on target hardware.

Change-Id: Ife4663d3ccf80a928646eadaac4c9ab49ad29055
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75471
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/rex/Kconfig

@@ -70,10 +70,11 @@ config DEVICETREE
 	default "variants/baseboard/\$(CONFIG_BASEBOARD_DIR)/devicetree.cb"
 
 config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos_ec_ish-debug-fsp.fmd" if CHROMEOS && DRIVERS_INTEL_ISH && BUILDING_WITH_DEBUG_FSP
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos_ec_ish.fmd" if CHROMEOS && DRIVERS_INTEL_ISH
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-debug-fsp.fmd" if CHROMEOS && BUILDING_WITH_DEBUG_FSP
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
 
-
 config MAINBOARD_DIR
 	default "google/rex"
 

src/mainboard/google/rex/chromeos_ec_ish-debug-fsp.fmd

@@ -0,0 +1,56 @@
+FLASH 32M {
+	SI_ALL 9M {
+		SI_DESC 16K
+		SI_ME
+	}
+	SI_BIOS 23M {
+		RW_SECTION_A 7680K {
+			VBLOCK_A 8K
+			FW_MAIN_A(CBFS)
+			RW_FWID_A 64
+			ME_RW_A(CBFS) 4500K
+		}
+		# This section starts at the 16M boundary in SPI flash.
+		# MTL does not support a region crossing this boundary,
+		# because the SPI flash is memory-mapped into two non-
+		# contiguous windows.
+		RW_SECTION_B 7680K {
+			VBLOCK_B 8K
+			FW_MAIN_B(CBFS)
+			RW_FWID_B 64
+			ME_RW_B(CBFS) 4500K
+		}
+		RW_MISC 1M {
+			UNIFIED_MRC_CACHE(PRESERVE) 128K {
+				RECOVERY_MRC_CACHE 64K
+				RW_MRC_CACHE 64K
+			}
+			RW_ELOG(PRESERVE) 16K
+			RW_SHARED 16K {
+				SHARED_DATA 8K
+				VBLOCK_DEV 8K
+			}
+			# The RW_SPD_CACHE region is only used for rex variants that use DDRx memory.
+			# It is placed in the common `chromeos.fmd` file because it is only 4K and there
+			# is free space in the RW_MISC region that cannot be easily reclaimed because
+			# the RW_SECTION_B must start on the 16M boundary.
+			RW_SPD_CACHE(PRESERVE) 4K
+			RW_VPD(PRESERVE) 8K
+			RW_NVRAM(PRESERVE) 24K
+		}
+		RW_LEGACY(CBFS) 1M
+		RW_UNUSED 2M
+		# Make WP_RO region align with SPI vendor
+		# memory protected range specification.
+		WP_RO 4M {
+			RO_VPD(PRESERVE) 16K
+			RO_GSCVD 8K
+			RO_SECTION {
+				FMAP 2K
+				RO_FRID 64
+				GBB@4K 12K
+				COREBOOT(CBFS)
+			}
+		}
+	}
+}

src/mainboard/google/rex/chromeos_ec_ish.fmd

@@ -0,0 +1,56 @@
+FLASH 32M {
+	SI_ALL 9M {
+		SI_DESC 16K
+		SI_ME
+	}
+	SI_BIOS 23M {
+		RW_SECTION_A 7M {
+			VBLOCK_A 8K
+			FW_MAIN_A(CBFS)
+			RW_FWID_A 64
+			ME_RW_A(CBFS) 4500K
+		}
+		# This section starts at the 16M boundary in SPI flash.
+		# MTL does not support a region crossing this boundary,
+		# because the SPI flash is memory-mapped into two non-
+		# contiguous windows.
+		RW_SECTION_B 7M {
+			VBLOCK_B 8K
+			FW_MAIN_B(CBFS)
+			RW_FWID_B 64
+			ME_RW_B(CBFS) 4500K
+		}
+		RW_MISC 1M {
+			UNIFIED_MRC_CACHE(PRESERVE) 128K {
+				RECOVERY_MRC_CACHE 64K
+				RW_MRC_CACHE 64K
+			}
+			RW_ELOG(PRESERVE) 16K
+			RW_SHARED 16K {
+				SHARED_DATA 8K
+				VBLOCK_DEV 8K
+			}
+			# The RW_SPD_CACHE region is only used for rex variants that use DDRx memory.
+			# It is placed in the common `chromeos.fmd` file because it is only 4K and there
+			# is free space in the RW_MISC region that cannot be easily reclaimed because
+			# the RW_SECTION_B must start on the 16M boundary.
+			RW_SPD_CACHE(PRESERVE) 4K
+			RW_VPD(PRESERVE) 8K
+			RW_NVRAM(PRESERVE) 24K
+		}
+		RW_LEGACY(CBFS) 1M
+		RW_UNUSED 3M
+		# Make WP_RO region align with SPI vendor
+		# memory protected range specification.
+		WP_RO 4M {
+			RO_VPD(PRESERVE) 16K
+			RO_GSCVD 8K
+			RO_SECTION {
+				FMAP 2K
+				RO_FRID 64
+				GBB@4K 12K
+				COREBOOT(CBFS)
+			}
+		}
+	}
+}