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small cleanup attempt in sc520 code. there needs to be some major spring

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cleaning


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2214 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
2006-03-19 17:50:54 +00:00
parent 677267a82a
commit 3cb4dc9c6b
4 changed files with 85 additions and 91 deletions
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2
src/config/Options.lb
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@@ -817,7 +817,7 @@ end
define HT_CHAIN_UNITID_BASE
default 1
export always
comment "this will be first hypertransport device's unitid base, if sb ht chain only has one ht device, it could be 0"
comment "first hypertransport device's unitid base. if southbridge ht chain only has one ht device, it could be 0"
end
define HT_CHAIN_END_UNITID_BASE

101
src/cpu/amd/sc520/raminit.c
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@@ -56,69 +56,44 @@
#define drcbendadr (( volatile unsigned long *)0xfffef018)
#define eccctl (( volatile unsigned char *)0xfffef020)
#define dbctl (( volatile unsigned char *)0xfffef040)
void
setupsc520(void){
void setupsc520(void)
{
volatile unsigned char *cp;
volatile unsigned short *sp;
volatile unsigned long *edi;
volatile unsigned long *par;
/* do this to see if MMCR will start acting right.
* we suspect you have to do SOMETHING to get things going.
* I'm really starting to hate this processor.
/* do this to see if MMCR will start acting right. we suspect
* you have to do SOMETHING to get things going. I'm really
* starting to hate this processor.
*/
/* no, that did not help. I wonder what will?
* outl(0x800df0cb, 0xfffc);
*/
/* well, this is special! You have to do SHORT writes to the locations,
* even though they are CHAR in size and CHAR aligned and technically, a
* SHORT write will result in -- yoo ha! -- over writing the next location!
* Thanks to the u-boot guys for a reference code I can use.
* with these short pointers, it now reliably comes up after power cycle
* with printk. Ah yi yi.
/* well, this is special! You have to do SHORT writes to the
* locations, even though they are CHAR in size and CHAR aligned
* and technically, a SHORT write will result in -- yoo ha! --
* over writing the next location! Thanks to the u-boot guys
* for a reference code I can use. with these short pointers,
* it now reliably comes up after power cycle with printk. Ah yi
* yi.
*/
/* turn off the write buffer*/
/* per the note above, make this a short? Let's try it.
*/
/* per the note above, make this a short? Let's try it. */
sp = (unsigned short *)0xfffef040;
*sp = 0;
// moved to auto.c by stepan
setup_pars();
#if 0
/* as per the book: */
/* PAR register setup */
/* set up the PAR registers as they are on the MSM586SEG */
par = (unsigned long *) 0xfffef088;
/* moved to auto.c by Stepan, Ron says: */
/* NOTE: move this to mainboard.c ASAP */
#if 1
*par++ = 0x607c00a0; /*PAR0: PCI:Base 0xa0000; size 0x1f000:*/
*par++ = 0x480400d8; /*PAR1: GP BUS MEM:CS2:Base 0xd8, size 0x4:*/
*par++ = 0x340100ea; /*PAR2: GP BUS IO:CS5:Base 0xea, size 0x1:*/
*par++ = 0x380701f0; /*PAR3: GP BUS IO:CS6:Base 0x1f0, size 0x7:*/
*par++ = 0x3c0003f6; /*PAR4: GP BUS IO:CS7:Base 0x3f6, size 0x0:*/
*par++ = 0x35ff0400; /*PAR5: GP BUS IO:CS5:Base 0x400, size 0xff:*/
*par++ = 0x35ff0600; /*PAR6: GP BUS IO:CS5:Base 0x600, size 0xff:*/
*par++ = 0x35ff0800; /*PAR7: GP BUS IO:CS5:Base 0x800, size 0xff:*/
*par++ = 0x35ff0a00; /*PAR8: GP BUS IO:CS5:Base 0xa00, size 0xff:*/
*par++ = 0x35ff0e00; /*PAR9: GP BUS IO:CS5:Base 0xe00, size 0xff:*/
*par++ = 0x34fb0104; /*PAR10: GP BUS IO:CS5:Base 0x104, size 0xfb:*/
*par++ = 0x35af0200; /*PAR11: GP BUS IO:CS5:Base 0x200, size 0xaf:*/
*par++ = 0x341f03e0; /*PAR12: GP BUS IO:CS5:Base 0x3e0, size 0x1f:*/
*par++ = 0xe41c00c0; /*PAR13: SDRAM:code:cache:nowrite:Base 0xc0000, size 0x7000:*/
*par++ = 0x545c00c8; /*PAR14: GP BUS MEM:CS5:Base 0xc8, size 0x5c:*/
#else
par += 15;
#endif
*par++ = 0x8a020200; /*PAR15: BOOTCS:code:nocache:write:Base 0x2000000, size 0x80000:*/
#endif
setup_pars();
/* CPCSF register */
sp = (unsigned short *)0xfffefc24;
*sp = 0xfe;
@@ -178,8 +153,8 @@ setupsc520(void){
outb(0x55, 0x80);
#endif
/*; set the uart baud rate clocks to the normal 1.8432 MHz.*/
/* enable interrupts here? Why not? */
/* set the uart baud rate clocks to the normal 1.8432 MHz.*/
/* enable interrupts here? Why not? */
cp = (unsigned char *)0xfffefcc0;
*cp = 4 | 3; /* uart 1 clock source */
cp = (unsigned char *)0xfffefcc4;
@@ -205,19 +180,20 @@ setupsc520(void){
cp = (unsigned char *)0x0fffefd51;
*cp = 0x02;
#endif
/*; "enumerate" the PCI. Mainly set the interrupt bits on the PCnetFast. */
/* Stepan says: This needs to go to the msm586seg code */
/* "enumerate" the PCI. Mainly set the interrupt bits on the PCnetFast. */
outl(0xcf8, 0x08000683c);
outl(0xcfc, 0xc); /* set the interrupt line */
/*; Set the SC520 PCI host bridge to target mode to allow external*/
/*; bus mastering events*/
outl(0x0cf8,0x080000004); /*index the status command register on device 0*/
/* Set the SC520 PCI host bridge to target mode to
* allow external bus mastering events
*/
/* index the status command register on device 0*/
outl(0x0cf8,0x080000004);
outl(0xcfc, 0x2); /*set the memory access enable bit*/
OUTC(0x0fffef072, 1); /* enable req bits in SYSARBMENB */
}
@@ -632,9 +608,10 @@ bad_ram:
/* This code is known to work on the digital logic board and on the technologic
* systems ts5300
*/
int
staticmem(void){
int staticmem(void)
{
volatile unsigned long *zero = (unsigned long *) CACHELINESZ;
/* set up 0x18 .. **/
*drcbendadr = 0x88;
*drcmctl = 0x1e;
@@ -651,27 +628,27 @@ staticmem(void){
/* two autorefreshes */
*drcctl = 4;
*zero = 0;
print_err("one zero out on refresh\r\n");
print_debug("one zero out on refresh\r\n");
*zero = 0;
print_err("two zero out on refresh\r\n");
print_debug("two zero out on refresh\r\n");
/* load mode register */
*drcctl = 3;
*zero = 0;
print_err("DONE the load mode reg\r\n");
print_debug("DONE the load mode reg\r\n");
/* normal mode */
*drcctl = 0x0;
*zero = 0;
print_err("DONE one last write and then turn on refresh etc\r\n");
print_debug("DONE one last write and then turn on refresh etc\r\n");
*drcctl = 0x18;
*zero = 0;
print_err("DONE the normal\r\n");
print_debug("DONE the normal\r\n");
*zero = 0xdeadbeef;
if (*zero != 0xdeadbeef)
print_err("NO LUCK\r\n");
print_debug("NO LUCK\r\n");
else
print_err("did a store and load ...\r\n");
print_debug("did a store and load ...\r\n");
//print_err_hex32(*zero);
// print_err(" zero is now "); print_err_hex32(*zero); print_err("\r\n");
}

22
src/cpu/amd/sc520/sc520.c
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@@ -1,3 +1,7 @@
/*
* This file needs a major cleanup. Too much #if 0 code
*/
#include <console/console.h>
#include <arch/io.h>
#include <stdint.h>
@@ -24,7 +28,8 @@ udelay(int microseconds) {
sc520_udelay(microseconds);
}
/*
* set up basic things ... PAR should NOT go here, as it might change with the mainboard.
* set up basic things ...
* PAR should NOT go here, as it might change with the mainboard.
*/
static void cpu_init(device_t dev)
{
@@ -210,11 +215,18 @@ void sc520_enable_resources(device_t dev) {
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
.enable_resources = enable_resources,
/*
* If enable_resources is set to the generic enable_resources
* function the whole thing will hang in an endless loop on
* the ts5300. If this is really needed on another platform,
* something is conceptionally wrong.
*/
.enable_resources = 0, //enable_resources,
.init = 0,
.scan_bus = pci_domain_scan_bus,
};
#if 0
static void cpu_bus_init(device_t dev)
{
printk_spew("cpu_bus_init\n");
@@ -231,6 +243,7 @@ static struct device_operations cpu_bus_ops = {
.init = cpu_bus_init,
.scan_bus = 0,
};
#endif
static void enable_dev(struct device *dev)
{
@@ -240,9 +253,14 @@ static void enable_dev(struct device *dev)
dev->ops = &pci_domain_ops;
pci_set_method(dev);
}
#if 0
/* This is never hit as none of the sc520 boards have
* an APIC cluster defined
*/
else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
dev->ops = &cpu_bus_ops;
}
#endif
}

9
targets/technologic/ts5300/Config.lb
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@@ -4,11 +4,9 @@
target technologic_ts5300
mainboard technologic/ts5300
option DEFAULT_CONSOLE_LOGLEVEL=10
option MAXIMUM_CONSOLE_LOGLEVEL=10
option DEFAULT_CONSOLE_LOGLEVEL=3
option MAXIMUM_CONSOLE_LOGLEVEL=3
option CONFIG_COMPRESS=1
#option CONFIG_COMPRESS=0
option CONFIG_CONSOLE_VGA=0
#romimage "normal"
@@ -27,7 +25,8 @@ romimage "fallback"
# option ROM_IMAGE_SIZE=48 * 1024 # 0x8000
# option ROM_IMAGE_SIZE=64 * 1024 # 0x10000
# option ROM_IMAGE_SIZE=512 * 1024 # 0x10000
option LINUXBIOS_EXTRA_VERSION=".0-Fallback"
# option LINUXBIOS_EXTRA_VERSION=".0-Fallback"
option LINUXBIOS_EXTRA_VERSION=".0"
payload /home/stepan/filo-ts5300.elf
end