cpu/x86/(sipi|smm): Pass on CR3 from ramstage

To allow for more flexibility like generating page tables at runtime or
page tables that are part of the ramstage, add a parameter to
sipi_vector.S and smm_stub.S so that APs use the same page tables as the
BSP during their initialization.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I1250ea6f63c65228178ee66e06d988dadfcc2a37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80335
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>

src/cpu/x86/mp_init.c

@@ -98,6 +98,7 @@ struct sipi_params {
 	uint32_t msr_table_ptr;
 	uint32_t msr_count;
 	uint32_t c_handler;
+	uint32_t cr3;
 	atomic_t ap_count;
 } __packed;
 
@@ -361,6 +362,7 @@ static atomic_t *load_sipi_vector(struct mp_params *mp_params)
 	else
 		sp->microcode_lock = 0;
 	sp->c_handler = (uintptr_t)&ap_init;
+	sp->cr3 = read_cr3();
 	ap_count = &sp->ap_count;
 	atomic_set(ap_count, 0);
 
@@ -763,6 +765,7 @@ static enum cb_err install_relocation_handler(int num_cpus, size_t save_state_si
 		.cpu_save_state_size = save_state_size,
 		.num_concurrent_save_states = 1,
 		.handler = smm_do_relocation,
+		.cr3 = read_cr3(),
 	};
 
 	if (smm_setup_relocation_handler(&smm_params)) {
@@ -787,6 +790,7 @@ static enum cb_err install_permanent_handler(int num_cpus, uintptr_t smbase,
 		.num_cpus = num_cpus,
 		.cpu_save_state_size = save_state_size,
 		.num_concurrent_save_states = num_cpus,
+		.cr3 = read_cr3(),
 	};
 
 	printk(BIOS_DEBUG, "Installing permanent SMM handler to 0x%08lx\n", smbase);

src/cpu/x86/sipi_vector.S

@@ -38,6 +38,8 @@ msr_count:
 .long 0
 c_handler:
 .long 0
+cr3:
+.long 0
 ap_count:
 .long 0
 
@@ -224,7 +226,7 @@ load_msr:
 
 #if ENV_X86_64
 	/* entry64.inc preserves ebx, esi, edi, ebp */
-	setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC)
+	setup_longmode cr3
 
 	movabs	c_handler, %eax
 	call	*%rax

src/cpu/x86/smm/smm_stub.S

@@ -23,6 +23,8 @@ stack_top:
 .long 0
 c_handler:
 .long 0
+cr3:
+.long 0
 /* apic_to_cpu_num is a table mapping the default APIC id to CPU num. If the
  * APIC id is found at the given index, the contiguous CPU number is index
  * into the table. */
@@ -196,7 +198,7 @@ align_stack:
 #if ENV_X86_64
 	mov	%ecx, %edi
 	/* entry64.inc preserves ebx, esi, edi, ebp */
-	setup_longmode $(CONFIG_ARCH_X86_64_PGTBL_LOC)
+	setup_longmode cr3
 	mov	%edi, %ecx
 
 

src/include/cpu/x86/smm.h

@@ -109,6 +109,7 @@ struct smm_stub_params {
 	u32 stack_size;
 	u32 stack_top;
 	u32 c_handler;
+	u32 cr3;
 	/* The apic_id_to_cpu provides a mapping from APIC id to CPU number.
 	 * The CPU number is indicated by the index into the array by matching
 	 * the default APIC id and value at the index. The stub loader
@@ -165,6 +166,7 @@ struct smm_loader_params {
 	size_t num_concurrent_save_states;
 
 	smm_handler_t handler;
+	uint32_t cr3;
 };
 
 /* All of these return 0 on success, < 0 on failure. */