sb/intel/lynxpoint/me_9.x.c: Rename to me.c
This code will eventually support both ME 9.x and ME 10. Change-Id: Idc02ab668a0b0d51c31f33f1266d983e64fb5505 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons
committed by
Patrick Georgi
Patrick Georgi
parent
da43737c4e
commit
3d3728b0d0
993
src/southbridge/intel/lynxpoint/me.c
Normal file
993
src/southbridge/intel/lynxpoint/me.c
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@@ -0,0 +1,993 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* This is a ramstage driver for the Intel Management Engine found in the
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* 6-series chipset. It handles the required boot-time messages over the
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* MMIO-based Management Engine Interface to tell the ME that the BIOS is
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* finished with POST. Additional messages are defined for debug but are
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* not used unless the console loglevel is high enough.
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*/
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#include <acpi/acpi.h>
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#include <device/mmio.h>
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#include <device/pci_ops.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_def.h>
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#include <string.h>
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#include <delay.h>
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#include <elog.h>
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#include <stdlib.h>
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#include "chip.h"
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#include "me.h"
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#include "pch.h"
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#include <vendorcode/google/chromeos/chromeos.h>
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/* Path that the BIOS should take based on ME state */
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static const char *const me_bios_path_values[] __unused = {
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[ME_NORMAL_BIOS_PATH] = "Normal",
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[ME_S3WAKE_BIOS_PATH] = "S3 Wake",
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[ME_ERROR_BIOS_PATH] = "Error",
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[ME_RECOVERY_BIOS_PATH] = "Recovery",
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[ME_DISABLE_BIOS_PATH] = "Disable",
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[ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update",
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};
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static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev);
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/* MMIO base address for MEI interface */
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static u32 *mei_base_address;
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#ifdef __SIMPLE_DEVICE__
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void intel_me_mbp_clear(pci_devfn_t dev);
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#else
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void intel_me_mbp_clear(struct device *dev);
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#endif
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static void mei_dump(void *ptr, int dword, int offset, const char *type)
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{
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struct mei_csr *csr;
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if (!CONFIG(DEBUG_INTEL_ME))
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return;
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printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset);
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switch (offset) {
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case MEI_H_CSR:
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case MEI_ME_CSR_HA:
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csr = ptr;
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if (!csr) {
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printk(BIOS_SPEW, "ERROR: 0x%08x\n", dword);
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break;
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}
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printk(BIOS_SPEW, "cbd=%u cbrp=%02u cbwp=%02u ready=%u "
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"reset=%u ig=%u is=%u ie=%u\n", csr->buffer_depth,
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csr->buffer_read_ptr, csr->buffer_write_ptr,
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csr->ready, csr->reset, csr->interrupt_generate,
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csr->interrupt_status, csr->interrupt_enable);
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break;
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case MEI_ME_CB_RW:
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case MEI_H_CB_WW:
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printk(BIOS_SPEW, "CB: 0x%08x\n", dword);
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break;
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default:
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printk(BIOS_SPEW, "0x%08x\n", offset);
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break;
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}
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}
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/*
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* ME/MEI access helpers using memcpy to avoid aliasing.
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*/
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static inline void mei_read_dword_ptr(void *ptr, int offset)
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{
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u32 dword = read32(mei_base_address + (offset/sizeof(u32)));
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memcpy(ptr, &dword, sizeof(dword));
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mei_dump(ptr, dword, offset, "READ");
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}
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static inline void mei_write_dword_ptr(void *ptr, int offset)
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{
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u32 dword = 0;
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memcpy(&dword, ptr, sizeof(dword));
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write32(mei_base_address + (offset/sizeof(u32)), dword);
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mei_dump(ptr, dword, offset, "WRITE");
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}
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#ifdef __SIMPLE_DEVICE__
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static inline void pci_read_dword_ptr(pci_devfn_t dev, void *ptr, int offset)
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#else
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static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)
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#endif
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{
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u32 dword = pci_read_config32(dev, offset);
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memcpy(ptr, &dword, sizeof(dword));
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mei_dump(ptr, dword, offset, "PCI READ");
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}
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static inline void read_host_csr(struct mei_csr *csr)
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{
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mei_read_dword_ptr(csr, MEI_H_CSR);
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}
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static inline void write_host_csr(struct mei_csr *csr)
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{
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mei_write_dword_ptr(csr, MEI_H_CSR);
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}
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static inline void read_me_csr(struct mei_csr *csr)
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{
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mei_read_dword_ptr(csr, MEI_ME_CSR_HA);
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}
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static inline void write_cb(u32 dword)
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{
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write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword);
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mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
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}
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static inline u32 read_cb(void)
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{
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u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32)));
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mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
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return dword;
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}
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/* Wait for ME ready bit to be asserted */
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static int mei_wait_for_me_ready(void)
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{
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struct mei_csr me;
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unsigned int try = ME_RETRY;
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while (try--) {
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read_me_csr(&me);
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if (me.ready)
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return 0;
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udelay(ME_DELAY);
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}
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printk(BIOS_ERR, "ME: failed to become ready\n");
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return -1;
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}
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static void mei_reset(void)
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{
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struct mei_csr host;
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if (mei_wait_for_me_ready() < 0)
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return;
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/* Reset host and ME circular buffers for next message */
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read_host_csr(&host);
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host.reset = 1;
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host.interrupt_generate = 1;
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write_host_csr(&host);
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if (mei_wait_for_me_ready() < 0)
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return;
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/* Re-init and indicate host is ready */
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read_host_csr(&host);
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host.interrupt_generate = 1;
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host.ready = 1;
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host.reset = 0;
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write_host_csr(&host);
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}
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static int mei_send_packet(struct mei_header *mei, void *req_data)
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{
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struct mei_csr host;
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unsigned int ndata, n;
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u32 *data;
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/* Number of dwords to write */
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ndata = mei->length >> 2;
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/* Pad non-dword aligned request message length */
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if (mei->length & 3)
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ndata++;
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if (!ndata) {
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printk(BIOS_DEBUG, "ME: request has no data\n");
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return -1;
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}
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ndata++; /* Add MEI header */
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/*
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* Make sure there is still room left in the circular buffer.
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* Reset the buffer pointers if the requested message will not fit.
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*/
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read_host_csr(&host);
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if ((host.buffer_depth - host.buffer_write_ptr) < ndata) {
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printk(BIOS_ERR, "ME: circular buffer full, resetting...\n");
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mei_reset();
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read_host_csr(&host);
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}
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/* Ensure the requested length will fit in the circular buffer. */
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if ((host.buffer_depth - host.buffer_write_ptr) < ndata) {
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printk(BIOS_ERR, "ME: message (%u) too large for buffer (%u)\n",
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ndata + 2, host.buffer_depth);
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return -1;
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}
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/* Write MEI header */
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mei_write_dword_ptr(mei, MEI_H_CB_WW);
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ndata--;
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/* Write message data */
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data = req_data;
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for (n = 0; n < ndata; ++n)
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write_cb(*data++);
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/* Generate interrupt to the ME */
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read_host_csr(&host);
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host.interrupt_generate = 1;
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write_host_csr(&host);
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/* Make sure ME is ready after sending request data */
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return mei_wait_for_me_ready();
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}
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static int mei_send_data(u8 me_address, u8 host_address,
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void *req_data, int req_bytes)
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{
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struct mei_header header = {
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.client_address = me_address,
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.host_address = host_address,
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};
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struct mei_csr host;
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int current = 0;
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u8 *req_ptr = req_data;
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while (!header.is_complete) {
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int remain = req_bytes - current;
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int buf_len;
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read_host_csr(&host);
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buf_len = host.buffer_depth - host.buffer_write_ptr;
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if (buf_len > remain) {
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/* Send all remaining data as final message */
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header.length = req_bytes - current;
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header.is_complete = 1;
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} else {
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/* Send as much data as the buffer can hold */
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header.length = buf_len;
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}
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mei_send_packet(&header, req_ptr);
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req_ptr += header.length;
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current += header.length;
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}
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return 0;
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}
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static int mei_send_header(u8 me_address, u8 host_address,
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void *header, int header_len, int complete)
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{
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struct mei_header mei = {
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.client_address = me_address,
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.host_address = host_address,
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.length = header_len,
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.is_complete = complete,
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};
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return mei_send_packet(&mei, header);
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}
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static int mei_recv_msg(void *header, int header_bytes,
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void *rsp_data, int rsp_bytes)
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{
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struct mei_header mei_rsp;
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struct mei_csr me, host;
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unsigned int ndata, n;
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unsigned int expected;
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u32 *data;
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/* Total number of dwords to read from circular buffer */
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expected = (rsp_bytes + sizeof(mei_rsp) + header_bytes) >> 2;
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if (rsp_bytes & 3)
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expected++;
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if (mei_wait_for_me_ready() < 0)
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return -1;
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/*
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* The interrupt status bit does not appear to indicate that the
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* message has actually been received. Instead we wait until the
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* expected number of dwords are present in the circular buffer.
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*/
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for (n = ME_RETRY; n; --n) {
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read_me_csr(&me);
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if ((me.buffer_write_ptr - me.buffer_read_ptr) >= expected)
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break;
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udelay(ME_DELAY);
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}
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if (!n) {
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printk(BIOS_ERR, "ME: timeout waiting for data: expected "
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"%u, available %u\n", expected,
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me.buffer_write_ptr - me.buffer_read_ptr);
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return -1;
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}
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/* Read and verify MEI response header from the ME */
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mei_read_dword_ptr(&mei_rsp, MEI_ME_CB_RW);
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if (!mei_rsp.is_complete) {
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printk(BIOS_ERR, "ME: response is not complete\n");
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return -1;
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}
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/* Handle non-dword responses and expect at least the header */
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ndata = mei_rsp.length >> 2;
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if (mei_rsp.length & 3)
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ndata++;
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if (ndata != (expected - 1)) {
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printk(BIOS_ERR, "ME: response is missing data %d != %d\n",
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ndata, (expected - 1));
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return -1;
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}
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/* Read response header from the ME */
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data = header;
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for (n = 0; n < (header_bytes >> 2); ++n)
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*data++ = read_cb();
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ndata -= header_bytes >> 2;
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/* Make sure caller passed a buffer with enough space */
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if (ndata != (rsp_bytes >> 2)) {
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printk(BIOS_ERR, "ME: not enough room in response buffer: "
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"%u != %u\n", ndata, rsp_bytes >> 2);
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return -1;
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}
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/* Read response data from the circular buffer */
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data = rsp_data;
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for (n = 0; n < ndata; ++n)
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*data++ = read_cb();
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/* Tell the ME that we have consumed the response */
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read_host_csr(&host);
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host.interrupt_status = 1;
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host.interrupt_generate = 1;
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write_host_csr(&host);
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return mei_wait_for_me_ready();
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}
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static inline int mei_sendrecv_mkhi(struct mkhi_header *mkhi,
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void *req_data, int req_bytes,
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void *rsp_data, int rsp_bytes)
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{
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struct mkhi_header mkhi_rsp;
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/* Send header */
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if (mei_send_header(MEI_ADDRESS_MKHI, MEI_HOST_ADDRESS,
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mkhi, sizeof(*mkhi), req_bytes ? 0 : 1) < 0)
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return -1;
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/* Send data if available */
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if (req_bytes && mei_send_data(MEI_ADDRESS_MKHI, MEI_HOST_ADDRESS,
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req_data, req_bytes) < 0)
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return -1;
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/* Return now if no response expected */
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if (!rsp_bytes)
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return 0;
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/* Read header and data */
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if (mei_recv_msg(&mkhi_rsp, sizeof(mkhi_rsp),
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rsp_data, rsp_bytes) < 0)
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return -1;
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if (!mkhi_rsp.is_response ||
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mkhi->group_id != mkhi_rsp.group_id ||
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mkhi->command != mkhi_rsp.command) {
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printk(BIOS_ERR, "ME: invalid response, group %u ?= %u,"
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"command %u ?= %u, is_response %u\n", mkhi->group_id,
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mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command,
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mkhi_rsp.is_response);
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return -1;
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}
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return 0;
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}
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/*
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* mbp give up routine. This path is taken if hfs.mpb_rdy is 0 or the read
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* state machine on the BIOS end doesn't match the ME's state machine.
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*/
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#ifdef __SIMPLE_DEVICE__
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static void intel_me_mbp_give_up(pci_devfn_t dev)
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#else
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static void intel_me_mbp_give_up(struct device *dev)
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#endif
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{
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struct mei_csr csr;
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pci_write_config32(dev, PCI_ME_H_GS2, PCI_ME_MBP_GIVE_UP);
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read_host_csr(&csr);
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csr.reset = 1;
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csr.interrupt_generate = 1;
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write_host_csr(&csr);
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}
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/*
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* mbp clear routine. This will wait for the ME to indicate that
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* the MBP has been read and cleared.
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*/
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#ifdef __SIMPLE_DEVICE__
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void intel_me_mbp_clear(pci_devfn_t dev)
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#else
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void intel_me_mbp_clear(struct device *dev)
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#endif
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{
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int count;
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struct me_hfs2 hfs2;
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/* Wait for the mbp_cleared indicator */
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for (count = ME_RETRY; count > 0; --count) {
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pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2);
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if (hfs2.mbp_cleared)
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break;
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udelay(ME_DELAY);
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}
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if (count == 0) {
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printk(BIOS_WARNING, "ME: Timeout waiting for mbp_cleared\n");
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intel_me_mbp_give_up(dev);
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} else {
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printk(BIOS_INFO, "ME: MBP cleared\n");
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}
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}
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static void __unused me_print_fw_version(mbp_fw_version_name *vers_name)
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{
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if (!vers_name) {
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printk(BIOS_ERR, "ME: mbp missing version report\n");
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return;
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}
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printk(BIOS_DEBUG, "ME: found version %d.%d.%d.%d\n",
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vers_name->major_version, vers_name->minor_version,
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vers_name->hotfix_version, vers_name->build_version);
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}
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static inline void print_cap(const char *name, int state)
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{
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printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n",
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name, state ? " en" : "dis");
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}
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/* Get ME Firmware Capabilities */
|
||||
static int mkhi_get_fwcaps(mbp_mefwcaps *cap)
|
||||
{
|
||||
u32 rule_id = 0;
|
||||
struct me_fwcaps cap_msg;
|
||||
struct mkhi_header mkhi = {
|
||||
.group_id = MKHI_GROUP_ID_FWCAPS,
|
||||
.command = MKHI_FWCAPS_GET_RULE,
|
||||
};
|
||||
|
||||
/* Send request and wait for response */
|
||||
if (mei_sendrecv_mkhi(&mkhi, &rule_id, sizeof(u32),
|
||||
&cap_msg, sizeof(cap_msg)) < 0) {
|
||||
printk(BIOS_ERR, "ME: GET FWCAPS message failed\n");
|
||||
return -1;
|
||||
}
|
||||
*cap = cap_msg.caps_sku;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Get ME Firmware Capabilities */
|
||||
static void __unused me_print_fwcaps(mbp_mefwcaps *cap)
|
||||
{
|
||||
mbp_mefwcaps local_caps;
|
||||
if (!cap) {
|
||||
cap = &local_caps;
|
||||
printk(BIOS_ERR, "ME: mbp missing fwcaps report\n");
|
||||
if (mkhi_get_fwcaps(cap))
|
||||
return;
|
||||
}
|
||||
|
||||
print_cap("Full Network manageability", cap->full_net);
|
||||
print_cap("Regular Network manageability", cap->std_net);
|
||||
print_cap("Manageability", cap->manageability);
|
||||
print_cap("IntelR Anti-Theft (AT)", cap->intel_at);
|
||||
print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls);
|
||||
print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc);
|
||||
print_cap("ICC Over Clocking", cap->icc_over_clocking);
|
||||
print_cap("Protected Audio Video Path (PAVP)", cap->pavp);
|
||||
print_cap("IPV6", cap->ipv6);
|
||||
print_cap("KVM Remote Control (KVM)", cap->kvm);
|
||||
print_cap("Outbreak Containment Heuristic (OCH)", cap->och);
|
||||
print_cap("Virtual LAN (VLAN)", cap->vlan);
|
||||
print_cap("TLS", cap->tls);
|
||||
print_cap("Wireless LAN (WLAN)", cap->wlan);
|
||||
}
|
||||
|
||||
/* Send END OF POST message to the ME */
|
||||
static int __unused mkhi_end_of_post(void)
|
||||
{
|
||||
struct mkhi_header mkhi = {
|
||||
.group_id = MKHI_GROUP_ID_GEN,
|
||||
.command = MKHI_END_OF_POST,
|
||||
};
|
||||
u32 eop_ack;
|
||||
|
||||
/* Send request and wait for response */
|
||||
printk(BIOS_NOTICE, "ME: %s\n", __func__);
|
||||
if (mei_sendrecv_mkhi(&mkhi, NULL, 0, &eop_ack, sizeof(eop_ack)) < 0) {
|
||||
printk(BIOS_ERR, "ME: END OF POST message failed\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "ME: END OF POST message successful (%d)\n", eop_ack);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef __SIMPLE_DEVICE__
|
||||
|
||||
void intel_me_finalize_smm(void)
|
||||
{
|
||||
struct me_hfs hfs;
|
||||
u32 reg32;
|
||||
|
||||
mei_base_address = (u32 *)
|
||||
(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
|
||||
|
||||
/* S3 path will have hidden this device already */
|
||||
if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0)
|
||||
return;
|
||||
|
||||
/* Wait for ME MBP Cleared indicator */
|
||||
intel_me_mbp_clear(PCH_ME_DEV);
|
||||
|
||||
/* Make sure ME is in a mode that expects EOP */
|
||||
reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
|
||||
memcpy(&hfs, ®32, sizeof(u32));
|
||||
|
||||
/* Abort and leave device alone if not normal mode */
|
||||
if (hfs.fpt_bad ||
|
||||
hfs.working_state != ME_HFS_CWS_NORMAL ||
|
||||
hfs.operation_mode != ME_HFS_MODE_NORMAL)
|
||||
return;
|
||||
|
||||
/* Try to send EOP command so ME stops accepting other commands */
|
||||
mkhi_end_of_post();
|
||||
|
||||
/* Make sure IO is disabled */
|
||||
pci_and_config16(PCH_ME_DEV, PCI_COMMAND,
|
||||
~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
|
||||
|
||||
/* Hide the PCI device */
|
||||
RCBA32_OR(FD2, PCH_DISABLE_MEI1);
|
||||
}
|
||||
|
||||
#else /* !__SIMPLE_DEVICE__ */
|
||||
|
||||
static inline int mei_sendrecv_icc(struct icc_header *icc,
|
||||
void *req_data, int req_bytes,
|
||||
void *rsp_data, int rsp_bytes)
|
||||
{
|
||||
struct icc_header icc_rsp;
|
||||
|
||||
/* Send header */
|
||||
if (mei_send_header(MEI_ADDRESS_ICC, MEI_HOST_ADDRESS,
|
||||
icc, sizeof(*icc), req_bytes ? 0 : 1) < 0)
|
||||
return -1;
|
||||
|
||||
/* Send data if available */
|
||||
if (req_bytes && mei_send_data(MEI_ADDRESS_ICC, MEI_HOST_ADDRESS,
|
||||
req_data, req_bytes) < 0)
|
||||
return -1;
|
||||
|
||||
/* Read header and data, if needed */
|
||||
if (rsp_bytes && mei_recv_msg(&icc_rsp, sizeof(icc_rsp),
|
||||
rsp_data, rsp_bytes) < 0)
|
||||
return -1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int me_icc_set_clock_enables(u32 mask)
|
||||
{
|
||||
struct icc_clock_enables_msg clk = {
|
||||
.clock_enables = 0, /* Turn off specified clocks */
|
||||
.clock_mask = mask,
|
||||
.no_response = 1, /* Do not expect response */
|
||||
};
|
||||
struct icc_header icc = {
|
||||
.api_version = ICC_API_VERSION_LYNXPOINT,
|
||||
.icc_command = ICC_SET_CLOCK_ENABLES,
|
||||
.length = sizeof(clk),
|
||||
};
|
||||
|
||||
/* Send request and wait for response */
|
||||
if (mei_sendrecv_icc(&icc, &clk, sizeof(clk), NULL, 0) < 0) {
|
||||
printk(BIOS_ERR, "ME: ICC SET CLOCK ENABLES message failed\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "ME: ICC SET CLOCK ENABLES 0x%08x\n", mask);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Determine the path that we should take based on ME status */
|
||||
static me_bios_path intel_me_path(struct device *dev)
|
||||
{
|
||||
me_bios_path path = ME_DISABLE_BIOS_PATH;
|
||||
struct me_hfs hfs;
|
||||
struct me_hfs2 hfs2;
|
||||
|
||||
pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS);
|
||||
pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2);
|
||||
|
||||
/* Check and dump status */
|
||||
intel_me_status(&hfs, &hfs2);
|
||||
|
||||
/* Check Current Working State */
|
||||
switch (hfs.working_state) {
|
||||
case ME_HFS_CWS_NORMAL:
|
||||
path = ME_NORMAL_BIOS_PATH;
|
||||
break;
|
||||
case ME_HFS_CWS_REC:
|
||||
path = ME_RECOVERY_BIOS_PATH;
|
||||
break;
|
||||
default:
|
||||
path = ME_DISABLE_BIOS_PATH;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Check Current Operation Mode */
|
||||
switch (hfs.operation_mode) {
|
||||
case ME_HFS_MODE_NORMAL:
|
||||
break;
|
||||
case ME_HFS_MODE_DEBUG:
|
||||
case ME_HFS_MODE_DIS:
|
||||
case ME_HFS_MODE_OVER_JMPR:
|
||||
case ME_HFS_MODE_OVER_MEI:
|
||||
default:
|
||||
path = ME_DISABLE_BIOS_PATH;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Check for any error code and valid firmware and MBP */
|
||||
if (hfs.error_code || hfs.fpt_bad)
|
||||
path = ME_ERROR_BIOS_PATH;
|
||||
|
||||
/* Check if the MBP is ready */
|
||||
if (!hfs2.mbp_rdy) {
|
||||
printk(BIOS_CRIT, "%s: mbp is not ready!\n",
|
||||
__func__);
|
||||
path = ME_ERROR_BIOS_PATH;
|
||||
}
|
||||
|
||||
if (CONFIG(ELOG) && path != ME_NORMAL_BIOS_PATH) {
|
||||
struct elog_event_data_me_extended data = {
|
||||
.current_working_state = hfs.working_state,
|
||||
.operation_state = hfs.operation_state,
|
||||
.operation_mode = hfs.operation_mode,
|
||||
.error_code = hfs.error_code,
|
||||
.progress_code = hfs2.progress_code,
|
||||
.current_pmevent = hfs2.current_pmevent,
|
||||
.current_state = hfs2.current_state,
|
||||
};
|
||||
elog_add_event_byte(ELOG_TYPE_MANAGEMENT_ENGINE, path);
|
||||
elog_add_event_raw(ELOG_TYPE_MANAGEMENT_ENGINE_EXT,
|
||||
&data, sizeof(data));
|
||||
}
|
||||
|
||||
return path;
|
||||
}
|
||||
|
||||
/* Prepare ME for MEI messages */
|
||||
static int intel_mei_setup(struct device *dev)
|
||||
{
|
||||
struct resource *res;
|
||||
struct mei_csr host;
|
||||
|
||||
/* Find the MMIO base for the ME interface */
|
||||
res = find_resource(dev, PCI_BASE_ADDRESS_0);
|
||||
if (!res || res->base == 0 || res->size == 0) {
|
||||
printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
|
||||
return -1;
|
||||
}
|
||||
mei_base_address = (u32 *)(uintptr_t)res->base;
|
||||
|
||||
/* Ensure Memory and Bus Master bits are set */
|
||||
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
|
||||
|
||||
/* Clean up status for next message */
|
||||
read_host_csr(&host);
|
||||
host.interrupt_generate = 1;
|
||||
host.ready = 1;
|
||||
host.reset = 0;
|
||||
write_host_csr(&host);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Read the Extend register hash of ME firmware */
|
||||
static int intel_me_extend_valid(struct device *dev)
|
||||
{
|
||||
struct me_heres status;
|
||||
u32 extend[8] = {0};
|
||||
int i, count = 0;
|
||||
|
||||
pci_read_dword_ptr(dev, &status, PCI_ME_HERES);
|
||||
if (!status.extend_feature_present) {
|
||||
printk(BIOS_ERR, "ME: Extend Feature not present\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (!status.extend_reg_valid) {
|
||||
printk(BIOS_ERR, "ME: Extend Register not valid\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
switch (status.extend_reg_algorithm) {
|
||||
case PCI_ME_EXT_SHA1:
|
||||
count = 5;
|
||||
printk(BIOS_DEBUG, "ME: Extend SHA-1: ");
|
||||
break;
|
||||
case PCI_ME_EXT_SHA256:
|
||||
count = 8;
|
||||
printk(BIOS_DEBUG, "ME: Extend SHA-256: ");
|
||||
break;
|
||||
default:
|
||||
printk(BIOS_ERR, "ME: Extend Algorithm %d unknown\n",
|
||||
status.extend_reg_algorithm);
|
||||
return -1;
|
||||
}
|
||||
|
||||
for (i = 0; i < count; ++i) {
|
||||
extend[i] = pci_read_config32(dev, PCI_ME_HER(i));
|
||||
printk(BIOS_DEBUG, "%08x", extend[i]);
|
||||
}
|
||||
printk(BIOS_DEBUG, "\n");
|
||||
|
||||
/* Save hash in NVS for the OS to verify */
|
||||
if (CONFIG(CHROMEOS))
|
||||
chromeos_set_me_hash(extend, count);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Check whether ME is present and do basic init */
|
||||
static void intel_me_init(struct device *dev)
|
||||
{
|
||||
struct southbridge_intel_lynxpoint_config *config = dev->chip_info;
|
||||
me_bios_path path = intel_me_path(dev);
|
||||
me_bios_payload mbp_data;
|
||||
|
||||
/* Do initial setup and determine the BIOS path */
|
||||
printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_bios_path_values[path]);
|
||||
|
||||
if (path == ME_NORMAL_BIOS_PATH) {
|
||||
/* Validate the extend register */
|
||||
intel_me_extend_valid(dev);
|
||||
}
|
||||
|
||||
memset(&mbp_data, 0, sizeof(mbp_data));
|
||||
|
||||
/*
|
||||
* According to the ME9 BWG, BIOS is required to fetch MBP data in
|
||||
* all boot flows except S3 Resume.
|
||||
*/
|
||||
|
||||
/* Prepare MEI MMIO interface */
|
||||
if (intel_mei_setup(dev) < 0)
|
||||
return;
|
||||
|
||||
if (intel_me_read_mbp(&mbp_data, dev))
|
||||
return;
|
||||
|
||||
if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) {
|
||||
me_print_fw_version(mbp_data.fw_version_name);
|
||||
|
||||
if (CONFIG(DEBUG_INTEL_ME))
|
||||
me_print_fwcaps(mbp_data.fw_capabilities);
|
||||
|
||||
if (mbp_data.plat_time) {
|
||||
printk(BIOS_DEBUG, "ME: Wake Event to ME Reset: %u ms\n",
|
||||
mbp_data.plat_time->wake_event_mrst_time_ms);
|
||||
printk(BIOS_DEBUG, "ME: ME Reset to Platform Reset: %u ms\n",
|
||||
mbp_data.plat_time->mrst_pltrst_time_ms);
|
||||
printk(BIOS_DEBUG, "ME: Platform Reset to CPU Reset: %u ms\n",
|
||||
mbp_data.plat_time->pltrst_cpurst_time_ms);
|
||||
}
|
||||
}
|
||||
|
||||
/* Set clock enables according to devicetree */
|
||||
if (config && config->icc_clock_disable)
|
||||
me_icc_set_clock_enables(config->icc_clock_disable);
|
||||
|
||||
/*
|
||||
* Leave the ME unlocked. It will be locked via SMI command later.
|
||||
*/
|
||||
}
|
||||
|
||||
static void intel_me_enable(struct device *dev)
|
||||
{
|
||||
/* Avoid talking to the device in S3 path */
|
||||
if (acpi_is_wakeup_s3()) {
|
||||
dev->enabled = 0;
|
||||
pch_disable_devfn(dev);
|
||||
}
|
||||
}
|
||||
|
||||
static struct device_operations device_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.enable = intel_me_enable,
|
||||
.init = intel_me_init,
|
||||
.ops_pci = &pci_dev_ops_pci,
|
||||
};
|
||||
|
||||
static const unsigned short pci_device_ids[] = {
|
||||
PCI_DEVICE_ID_INTEL_LPT_H_MEI,
|
||||
PCI_DEVICE_ID_INTEL_LPT_LP_MEI,
|
||||
0
|
||||
};
|
||||
|
||||
static const struct pci_driver intel_me __pci_driver = {
|
||||
.ops = &device_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.devices = pci_device_ids,
|
||||
};
|
||||
|
||||
#endif /* !__SIMPLE_DEVICE__ */
|
||||
|
||||
/******************************************************************************
|
||||
* */
|
||||
static u32 me_to_host_words_pending(void)
|
||||
{
|
||||
struct mei_csr me;
|
||||
read_me_csr(&me);
|
||||
if (!me.ready)
|
||||
return 0;
|
||||
return (me.buffer_write_ptr - me.buffer_read_ptr) &
|
||||
(me.buffer_depth - 1);
|
||||
}
|
||||
|
||||
struct mbp_payload {
|
||||
mbp_header header;
|
||||
u32 data[0];
|
||||
};
|
||||
|
||||
/*
|
||||
* mbp seems to be following its own flow, let's retrieve it in a dedicated
|
||||
* function.
|
||||
*/
|
||||
static int __unused intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev)
|
||||
{
|
||||
mbp_header mbp_hdr;
|
||||
u32 me2host_pending;
|
||||
struct mei_csr host;
|
||||
struct me_hfs2 hfs2;
|
||||
struct mbp_payload *mbp;
|
||||
int i;
|
||||
|
||||
#ifdef __SIMPLE_DEVICE__
|
||||
pci_read_dword_ptr(PCI_BDF(dev), &hfs2, PCI_ME_HFS2);
|
||||
#else
|
||||
pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2);
|
||||
#endif
|
||||
|
||||
if (!hfs2.mbp_rdy) {
|
||||
printk(BIOS_ERR, "ME: MBP not ready\n");
|
||||
goto mbp_failure;
|
||||
}
|
||||
|
||||
me2host_pending = me_to_host_words_pending();
|
||||
if (!me2host_pending) {
|
||||
printk(BIOS_ERR, "ME: no mbp data!\n");
|
||||
goto mbp_failure;
|
||||
}
|
||||
|
||||
/* we know for sure that at least the header is there */
|
||||
mei_read_dword_ptr(&mbp_hdr, MEI_ME_CB_RW);
|
||||
|
||||
if ((mbp_hdr.num_entries > (mbp_hdr.mbp_size / 2)) ||
|
||||
(me2host_pending < mbp_hdr.mbp_size)) {
|
||||
printk(BIOS_ERR, "ME: mbp of %d entries, total size %d words"
|
||||
" buffer contains %d words\n",
|
||||
mbp_hdr.num_entries, mbp_hdr.mbp_size,
|
||||
me2host_pending);
|
||||
goto mbp_failure;
|
||||
}
|
||||
mbp = malloc(mbp_hdr.mbp_size * sizeof(u32));
|
||||
if (!mbp)
|
||||
goto mbp_failure;
|
||||
|
||||
mbp->header = mbp_hdr;
|
||||
me2host_pending--;
|
||||
|
||||
i = 0;
|
||||
while (i != me2host_pending) {
|
||||
mei_read_dword_ptr(&mbp->data[i], MEI_ME_CB_RW);
|
||||
i++;
|
||||
}
|
||||
|
||||
/* Signal to the ME that the host has finished reading the MBP. */
|
||||
read_host_csr(&host);
|
||||
host.interrupt_generate = 1;
|
||||
write_host_csr(&host);
|
||||
|
||||
/* Dump out the MBP contents. */
|
||||
if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) {
|
||||
printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n",
|
||||
mbp->header.num_entries, mbp->header.mbp_size);
|
||||
if (CONFIG(DEBUG_INTEL_ME)) {
|
||||
for (i = 0; i < mbp->header.mbp_size - 1; i++) {
|
||||
printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#define ASSIGN_FIELD_PTR(field_,val_) \
|
||||
{ \
|
||||
mbp_data->field_ = (typeof(mbp_data->field_))(void *)val_; \
|
||||
break; \
|
||||
}
|
||||
/* Setup the pointers in the me_bios_payload structure. */
|
||||
for (i = 0; i < mbp->header.mbp_size - 1;) {
|
||||
mbp_item_header *item = (void *)&mbp->data[i];
|
||||
|
||||
switch (MBP_MAKE_IDENT(item->app_id, item->item_id)) {
|
||||
case MBP_IDENT(KERNEL, FW_VER):
|
||||
ASSIGN_FIELD_PTR(fw_version_name, &mbp->data[i+1]);
|
||||
|
||||
case MBP_IDENT(ICC, PROFILE):
|
||||
ASSIGN_FIELD_PTR(icc_profile, &mbp->data[i+1]);
|
||||
|
||||
case MBP_IDENT(INTEL_AT, STATE):
|
||||
ASSIGN_FIELD_PTR(at_state, &mbp->data[i+1]);
|
||||
|
||||
case MBP_IDENT(KERNEL, FW_CAP):
|
||||
ASSIGN_FIELD_PTR(fw_capabilities, &mbp->data[i+1]);
|
||||
|
||||
case MBP_IDENT(KERNEL, ROM_BIST):
|
||||
ASSIGN_FIELD_PTR(rom_bist_data, &mbp->data[i+1]);
|
||||
|
||||
case MBP_IDENT(KERNEL, PLAT_KEY):
|
||||
ASSIGN_FIELD_PTR(platform_key, &mbp->data[i+1]);
|
||||
|
||||
case MBP_IDENT(KERNEL, FW_TYPE):
|
||||
ASSIGN_FIELD_PTR(fw_plat_type, &mbp->data[i+1]);
|
||||
|
||||
case MBP_IDENT(KERNEL, MFS_FAILURE):
|
||||
ASSIGN_FIELD_PTR(mfsintegrity, &mbp->data[i+1]);
|
||||
|
||||
case MBP_IDENT(KERNEL, PLAT_TIME):
|
||||
ASSIGN_FIELD_PTR(plat_time, &mbp->data[i+1]);
|
||||
|
||||
case MBP_IDENT(NFC, SUPPORT_DATA):
|
||||
ASSIGN_FIELD_PTR(nfc_data, &mbp->data[i+1]);
|
||||
|
||||
default:
|
||||
printk(BIOS_ERR, "ME MBP: unknown item 0x%x @ "
|
||||
"dw offset 0x%x\n", mbp->data[i], i);
|
||||
break;
|
||||
}
|
||||
i += item->length;
|
||||
}
|
||||
#undef ASSIGN_FIELD_PTR
|
||||
|
||||
return 0;
|
||||
|
||||
mbp_failure:
|
||||
#ifdef __SIMPLE_DEVICE__
|
||||
intel_me_mbp_give_up(PCI_BDF(dev));
|
||||
#else
|
||||
intel_me_mbp_give_up(dev);
|
||||
#endif
|
||||
return -1;
|
||||
}
|
||||
Reference in New Issue
Block a user