From 3d37711899bf94d9c4233ce354256df1ed02db65 Mon Sep 17 00:00:00 2001
From: Jeremy Soller <jeremy@system76.com>
Date: Tue, 24 Nov 2020 14:40:41 -0700
Subject: [PATCH] Apply TCSS recommendations from 617016

Change-Id: Ia30fa057f3f03e8d7e82d067e09ea85a7bab3385
---
 src/mainboard/system76/galp5/gpio.h      | 8 ++++----
 src/mainboard/system76/galp5/ramstage.c  | 2 ++
 src/mainboard/system76/lemp10/gpio.h     | 8 ++++----
 src/mainboard/system76/lemp10/ramstage.c | 2 ++
 4 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/system76/galp5/gpio.h b/src/mainboard/system76/galp5/gpio.h
index 7efe025c69..263db1face 100644
--- a/src/mainboard/system76/galp5/gpio.h
+++ b/src/mainboard/system76/galp5/gpio.h
@@ -265,10 +265,10 @@ static const struct pad_config gpio_table[] = {
 		PAD_CFG_GPI(GPP_E16, DN_20K, DEEP),
 		// NC
 		PAD_NC(GPP_E17, NONE),
-		// GPP_E18_TBT_LSX0_TXD
-		_PAD_CFG_STRUCT(GPP_E18, 0x44001700, 0x3c00),
-		// GPP_E19_TBT_LSX0_RXD
-		_PAD_CFG_STRUCT(GPP_E19, 0x44001600, 0x3c00),
+		// GPP_E18_TBT_LSX0_TXD - programmed by FSP, see Intel document 617016
+		PAD_NC(GPP_E18, NONE),
+		// GPP_E19_TBT_LSX0_RXD - programmed by FSP, see Intel document 617016
+		PAD_NC(GPP_E19, NONE),
 		// NC
 		PAD_NC(GPP_E20, NONE),
 		// NC
diff --git a/src/mainboard/system76/galp5/ramstage.c b/src/mainboard/system76/galp5/ramstage.c
index f0985b38de..9cb4cbd798 100644
--- a/src/mainboard/system76/galp5/ramstage.c
+++ b/src/mainboard/system76/galp5/ramstage.c
@@ -11,6 +11,8 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) {
 
 	// IOM config
 	params->PchUsbOverCurrentEnable = 0;
+	params->PortResetMessageEnable[5] = 1; // J_TYPEC2
+	params->UsbTcPortEn = 1;
 
 	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
 }
diff --git a/src/mainboard/system76/lemp10/gpio.h b/src/mainboard/system76/lemp10/gpio.h
index 720aa87644..282b19c06a 100644
--- a/src/mainboard/system76/lemp10/gpio.h
+++ b/src/mainboard/system76/lemp10/gpio.h
@@ -258,10 +258,10 @@ static const struct pad_config gpio_table[] = {
 		_PAD_CFG_STRUCT(GPP_E16, 0x82840100, 0x0000),
 		// NC
 		PAD_NC(GPP_E17, NONE),
-		// TBT_LSX0_TXD
-		_PAD_CFG_STRUCT(GPP_E18, 0x44001700, 0x3c00),
-		// TBT_LSX0_RXD
-		_PAD_CFG_STRUCT(GPP_E19, 0x44001600, 0x3c00),
+		// TBT_LSX0_TXD - programmed by FSP, see Intel document 617016
+		PAD_NC(GPP_E18, NONE),
+		// TBT_LSX0_RXD - programmed by FSP, see Intel document 617016
+		PAD_NC(GPP_E19, NONE),
 		// SWI#
 		_PAD_CFG_STRUCT(GPP_E20, 0x40880100, 0x0000),
 		// GPP_E21 - DDP2 I2C / TBT_LSX1 pin voltage (L=1.8V, H=3.3V)
diff --git a/src/mainboard/system76/lemp10/ramstage.c b/src/mainboard/system76/lemp10/ramstage.c
index f0985b38de..71d90289dd 100644
--- a/src/mainboard/system76/lemp10/ramstage.c
+++ b/src/mainboard/system76/lemp10/ramstage.c
@@ -11,6 +11,8 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) {
 
 	// IOM config
 	params->PchUsbOverCurrentEnable = 0;
+	params->PortResetMessageEnable[2] = 1; // J_TYPEC1
+	params->UsbTcPortEn = 1;
 
 	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
 }