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mb/google/brya/var/crota: Fix codec reset pin in overridetree

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Crota360 is using a Cirrus CS42L42 for its audio codec; it requires the
reset pin to be deasserted in ramstage for proper power sequencing.

BUG=b:230074351
BRANCH=none
TEST=build coreboot without error

Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Ica3467fbc8639526bee071d56af854de5e07091e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Terry Chen
2022-05-04 16:03:12 +08:00
committed by Felix Held
parent 0405d8b3ef
commit 3d51519685
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/google/brya/variants/crota/overridetree.cb
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@@ -132,7 +132,7 @@ chip soc/intel/alderlake
device ref i2c0 on device ref i2c0 on
chip drivers/i2c/cs42l42 chip drivers/i2c/cs42l42
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B13)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B15)"
register "ts_inv" = "true" register "ts_inv" = "true"
register "ts_dbnc_rise" = "RISE_DEB_1000_MS" register "ts_dbnc_rise" = "RISE_DEB_1000_MS"
register "ts_dbnc_fall" = "FALL_DEB_0_MS" register "ts_dbnc_fall" = "FALL_DEB_0_MS"