soc/intel/jasperlake: Drop redundant PcieRpEnable

The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.

Thanks to Nicholas for doing all the mainboard legwork!

Change-Id: Iea7f616f6db579c06722369c08de7cf7261dece8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79919
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/dedede/variants/baseboard/devicetree.cb

@@ -107,17 +107,6 @@ chip soc/intel/jasperlake
 		[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
 	}"
 
-	# PCIE Root Port Configuration
-	register "PcieRpEnable[0]" = "0"
-	register "PcieRpEnable[1]" = "0"
-	register "PcieRpEnable[2]" = "0"
-	register "PcieRpEnable[3]" = "0"
-	register "PcieRpEnable[4]" = "0"
-	register "PcieRpEnable[5]" = "0"
-	register "PcieRpEnable[6]" = "0"
-	# PCIe Root Port 8 (index 7) hosts M.2 E-key WLAN.
-	register "PcieRpEnable[7]" = "1"
-
 	register "PcieClkSrcUsage[0]" = "0xff"
 	register "PcieClkSrcUsage[1]" = "0xff"
 	register "PcieClkSrcUsage[2]" = "0xff"
@@ -394,7 +383,7 @@ chip soc/intel/jasperlake
 		device pci 1c.5 off end # PCI Express Root Port 6
 		device pci 1c.6 off end # PCI Express Root Port 7
 		# External PCIe port 4 is mapped to PCIe Root port 8
-		device pci 1c.7 on  end # PCI Express Root Port 8 - WLAN
+		device pci 1c.7 on  end # PCI Express Root Port 8 - hosts M.2 E-key WLAN
 		device pci 1e.0 off end # UART 0
 		device pci 1e.1 off end # UART 1
 		device pci 1e.2 on

src/mainboard/google/dedede/variants/baseboard/ramstage.c

@@ -6,6 +6,7 @@
 #include <drivers/usb/acpi/chip.h>
 #include <fw_config.h>
 #include <gpio.h>
+#include <soc/pci_devs.h>
 #include <ec/google/chromeec/ec.h>
 #include <device/pci_ops.h>
 #include <intelblocks/power_limit.h>

src/mainboard/google/dedede/variants/boxy/overridetree.cb

@@ -46,19 +46,14 @@ chip soc/intel/jasperlake
 		.tdp_pl4 = 60,
 	}"
 
-	# Enable Root Port 3 (index 2) for LAN
+	# Root Port 3 (index 2) for LAN
 	# External PCIe port 7 is mapped to PCIe Root Port 3
-	register "PcieRpEnable[2]" = "1"
 	register "PcieClkSrcUsage[4]" = "2"
 
-	# Enable Root Port 7 (index 6) for WLAN
+	# Root Port 7 (index 6) for WLAN
 	# External PCIe port 3 is mapped to PCIe Root Port 7
-	register "PcieRpEnable[6]" = "1"
 	register "PcieClkSrcUsage[3]" = "6"
 
-	# Disable PCIe Root Port 8
-	register "PcieRpEnable[7]" = "0"
-
 	# Audio related configurations
 	register "PchHdaAudioLinkDmicEnable[0]" = "0"
 	register "PchHdaAudioLinkDmicEnable[1]" = "0"

src/mainboard/google/dedede/variants/bugzzy/overridetree.cb

@@ -8,8 +8,6 @@ chip soc/intel/jasperlake
 	register "SlowSlewRate" = "SlewRateFastBy8"
 	register "FastPkgCRampDisable" = "1"
 
-	# Disable PCIe Root Port 8 (index 7)
-	register "PcieRpEnable[7]" = "0"
 	# Disable PCIe Clock Source 4 (index 3)
 	register "PcieClkSrcUsage[3]" = "0xff"
 

src/mainboard/google/dedede/variants/dexi/overridetree.cb

@@ -38,19 +38,14 @@ chip soc/intel/jasperlake
 		.tdp_pl4 = 60,
 	}"
 
-	# Enable Root Port 3 (index 2) for LAN
+	# Root Port 3 (index 2) for LAN
 	# External PCIe port 7 is mapped to PCIe Root Port 3
-	register "PcieRpEnable[2]" = "1"
 	register "PcieClkSrcUsage[4]" = "2"
 
-	# Enable Root Port 7 (index 6) for WLAN
+	# Root Port 7 (index 6) for WLAN
 	# External PCIe port 3 is mapped to PCIe Root Port 7
-	register "PcieRpEnable[6]" = "1"
 	register "PcieClkSrcUsage[3]" = "6"
 
-	# Disable PCIe Root Port 8
-	register "PcieRpEnable[7]" = "0"
-
 	# Audio related configurations
 	register "PchHdaAudioLinkDmicEnable[0]" = "0"
 	register "PchHdaAudioLinkDmicEnable[1]" = "0"

src/mainboard/google/dedede/variants/dibbi/overridetree.cb

@@ -38,19 +38,14 @@ chip soc/intel/jasperlake
 		.tdp_pl4 = 60,
 	}"
 
-	# Enable Root Port 3 (index 2) for LAN
+	# Root Port 3 (index 2) for LAN
 	# External PCIe port 7 is mapped to PCIe Root Port 3
-	register "PcieRpEnable[2]" = "1"
 	register "PcieClkSrcUsage[4]" = "2"
 
-	# Enable Root Port 7 (index 6) for WLAN
+	# Root Port 7 (index 6) for WLAN
 	# External PCIe port 3 is mapped to PCIe Root Port 7
-	register "PcieRpEnable[6]" = "1"
 	register "PcieClkSrcUsage[3]" = "6"
 
-	# Disable PCIe Root Port 8
-	register "PcieRpEnable[7]" = "0"
-
 	# Audio related configurations
 	register "PchHdaAudioLinkDmicEnable[0]" = "0"
 	register "PchHdaAudioLinkDmicEnable[1]" = "0"

src/mainboard/google/dedede/variants/dita/overridetree.cb

@@ -38,19 +38,14 @@ chip soc/intel/jasperlake
 		.tdp_pl4 = 60,
 	}"
 
-	# Enable Root Port 3 (index 2) for LAN
+	# Root Port 3 (index 2) for LAN
 	# External PCIe port 7 is mapped to PCIe Root Port 3
-	register "PcieRpEnable[2]" = "1"
 	register "PcieClkSrcUsage[4]" = "2"
 
-	# Enable Root Port 7 (index 6) for WLAN
+	# Root Port 7 (index 6) for WLAN
 	# External PCIe port 3 is mapped to PCIe Root Port 7
-	register "PcieRpEnable[6]" = "1"
 	register "PcieClkSrcUsage[3]" = "6"
 
-	# Disable PCIe Root Port 8
-	register "PcieRpEnable[7]" = "0"
-
 	# Audio related configurations
 	register "PchHdaAudioLinkDmicEnable[0]" = "0"
 	register "PchHdaAudioLinkDmicEnable[1]" = "0"

src/mainboard/google/dedede/variants/sasuke/overridetree.cb

@@ -1,6 +1,4 @@
 chip soc/intel/jasperlake
-	# Disable PCIe Root Port 8 (index 7)
-	register "PcieRpEnable[7]" = "0"
 	# Disable PCIe Clock Source 4 (index 3)
 	register "PcieClkSrcUsage[3]" = "0xff"
 

src/mainboard/google/dedede/variants/sasukette/overridetree.cb

@@ -8,8 +8,6 @@ fw_config
 end
 
 chip soc/intel/jasperlake
-	# Disable PCIe Root Port 8 (index 7)
-	register "PcieRpEnable[7]" = "0"
 	# Disable PCIe Clock Source 4 (index 3)
 	register "PcieClkSrcUsage[3]" = "0xff"
 
@@ -227,6 +225,7 @@ chip soc/intel/jasperlake
 				end
 			end
 		end #I2C 4
+		device pci 1c.7 off end # PCI Express Root Port 8
 		device pci 1f.3 on
 			chip drivers/generic/alc1015
 				register "sdb" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)"

src/mainboard/google/dedede/variants/storo/overridetree.cb

@@ -7,8 +7,6 @@ fw_config
 end
 
 chip soc/intel/jasperlake
-	# Disable PCIe Root Port 8 (index 7)
-	register "PcieRpEnable[7]" = "0"
 	# Disable PCIe Clock Source 4 (index 3)
 	register "PcieClkSrcUsage[3]" = "0xff"
 
@@ -381,5 +379,6 @@ chip soc/intel/jasperlake
 				device i2c 28 on end
 			end
 		end # I2C 5
+		device pci 1c.7 off end # PCI Express Root Port 8
 	end
 end

src/mainboard/google/dedede/variants/taranza/overridetree.cb

@@ -38,19 +38,14 @@ chip soc/intel/jasperlake
 		.tdp_pl4 = 60,
 	}"
 
-	# Enable Root Port 3 (index 2) for LAN
+	# Root Port 3 (index 2) for LAN
 	# External PCIe port 7 is mapped to PCIe Root Port 3
-	register "PcieRpEnable[2]" = "1"
 	register "PcieClkSrcUsage[4]" = "2"
 
-	# Enable Root Port 7 (index 6) for WLAN
+	# Root Port 7 (index 6) for WLAN
 	# External PCIe port 3 is mapped to PCIe Root Port 7
-	register "PcieRpEnable[6]" = "1"
 	register "PcieClkSrcUsage[3]" = "6"
 
-	# Disable PCIe Root Port 8
-	register "PcieRpEnable[7]" = "0"
-
 	# Audio related configurations
 	register "PchHdaAudioLinkDmicEnable[0]" = "0"
 	register "PchHdaAudioLinkDmicEnable[1]" = "0"

src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb

@@ -63,11 +63,6 @@ chip soc/intel/jasperlake
 	register "PchHdaAudioLinkDmicEnable[0]" = "1"
 	register "PchHdaAudioLinkDmicEnable[1]" = "1"
 
-	# PCIe port 1 for M.2 E-key WLAN
-	# Enable Root Port 4(x4) for NVMe
-	register "PcieRpEnable[1]" = "1"
-	register "PcieRpEnable[4]" = "1"
-
 	# Enable ClkReqDetect 1 for WLAN
 	# Enable ClkReqDetect 4 for NVMe
 	register "PcieRpClkReqDetect[1]" = "1"
@@ -469,14 +464,8 @@ chip soc/intel/jasperlake
 
 		device pci 19.2 on  end # UART #2
 		device pci 1a.0 on  end # eMMC
-		device pci 1c.0 off end # PCI Express Port 1
-		device pci 1c.1 on  end # PCI Express Port 2 - WLAN
-		device pci 1c.2 off end # PCI Express Port 3
-		device pci 1c.3 off end # PCI Express Port 4
+		device pci 1c.1 on  end # PCI Express Port 2 - M.2 E-key WLAN
 		device pci 1c.4 on  end # PCI Express Port 5 - NVMe
-		device pci 1c.5 off end # PCI Express Port 6
-		device pci 1c.6 off end # PCI Express Port 7
-		device pci 1c.7 off end # PCI Express Port 8
 		device pci 1e.0 on  end # UART #0
 		device pci 1e.1 off end # UART #1
 		device pci 1e.2 off end # GSPI #0

src/mainboard/purism/librem_jsl/devicetree.cb

@@ -159,7 +159,6 @@ chip soc/intel/jasperlake
 		device pci 1c.0 off end	# PCI Express Root Port 1
 		device pci 1c.1 off end	# PCI Express Root Port 2
 		device pci 1c.2 on	# PCI Express Root Port 3 - M.2 M-key, PCIe only
-			register "PcieRpEnable[2]" = "true"
 			register "PcieClkSrcUsage[0]" = "2"
 			register "PcieClkSrcClkReq[0]" = "0"
 			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth2X"

src/soc/intel/jasperlake/Makefile.mk

@@ -22,6 +22,7 @@ bootblock-y += p2sb.c
 romstage-y += espi.c
 romstage-y += gpio.c
 romstage-y += meminit.c
+romstage-y += pcie_rp.c
 romstage-y += reset.c
 
 ramstage-y += acpi.c
@@ -35,6 +36,7 @@ ramstage-y += gpio.c
 ramstage-y += graphics.c
 ramstage-y += lockdown.c
 ramstage-y += p2sb.c
+ramstage-y += pcie_rp.c
 ramstage-y += pmc.c
 ramstage-y += reset.c
 ramstage-y += systemagent.c

src/soc/intel/jasperlake/chip.c

@@ -14,14 +14,10 @@
 #include <soc/intel/common/vbt.h>
 #include <soc/itss.h>
 #include <soc/pci_devs.h>
+#include <soc/pcie.h>
 #include <soc/ramstage.h>
 #include <soc/soc_chip.h>
 
-static const struct pcie_rp_group pch_rp_groups[] = {
-	{ .slot = PCH_DEV_SLOT_PCIE,    .count = 8, .lcap_port_base = 1 },
-	{ 0 }
-};
-
 #if CONFIG(HAVE_ACPI_TABLES)
 const char *soc_acpi_name(const struct device *dev)
 {

src/soc/intel/jasperlake/chip.h

@@ -146,7 +146,6 @@ struct soc_intel_jasperlake_config {
 	bool PchHdaIDispCodecDisconnect;
 
 	/* PCIe Root Ports */
-	bool PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
 	/* PCIe output clocks type to PCIe devices.
 	 * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
 	 * 0xFF: not used */

src/soc/intel/jasperlake/include/soc/pcie.h

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_JASPERLAKE_PCIE_H__
+#define __SOC_JASPERLAKE_PCIE_H__
+
+#include <intelblocks/pcie_rp.h>
+
+extern const struct pcie_rp_group pch_rp_groups[];
+
+#endif /* __SOC_JASPERLAKE_PCIE_H__ */

src/soc/intel/jasperlake/pcie_rp.c

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <intelblocks/pcie_rp.h>
+#include <soc/pci_devs.h>
+#include <soc/pcie.h>
+
+const struct pcie_rp_group pch_rp_groups[] = {
+	{ .slot = PCH_DEV_SLOT_PCIE,    .count = 8, .lcap_port_base = 1 },
+	{ 0 }
+};

src/soc/intel/jasperlake/romstage/fsp_params.c

@@ -5,8 +5,10 @@
 #include <device/device.h>
 #include <fsp/util.h>
 #include <intelblocks/cpulib.h>
+#include <intelblocks/pcie_rp.h>
 #include <soc/iomap.h>
 #include <soc/pci_devs.h>
+#include <soc/pcie.h>
 #include <soc/romstage.h>
 #include <soc/soc_chip.h>
 
@@ -14,7 +16,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 		const struct soc_intel_jasperlake_config *config)
 {
 	unsigned int i;
-	uint32_t mask = 0;
 
 	/*
 	 * If IGD is enabled, set IGD stolen size to 60MB.
@@ -61,13 +62,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 		}
 	}
 
-	/* PCIe root port configuration */
-	for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
-		if (config->PcieRpEnable[i])
-			mask |= (1 << i);
-	}
-
-	m_cfg->PcieRpEnableMask = mask;
+	m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(pch_rp_groups);
 
 	FSP_ARRAY_LOAD(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage);
 	FSP_ARRAY_LOAD(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq);