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soc/amd/cezanne: Enable early LPC support in bootblock stage

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Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I739d97ddc5afd84a4bbc7e505b423158eb820767
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Zheng Bao
2021-01-26 18:30:18 +08:00
committed by Felix Held
parent 6e2f5f2ee7
commit 3da5569488
5 changed files with 27 additions and 0 deletions
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1
src/soc/amd/cezanne/Kconfig
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@@ -24,6 +24,7 @@ config SOC_SPECIFIC_OPTIONS
select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_ACPIMMIO
select SOC_AMD_COMMON_BLOCK_AOAC select SOC_AMD_COMMON_BLOCK_AOAC
select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
select SOC_AMD_COMMON_BLOCK_LPC
select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_NONCAR
select SOC_AMD_COMMON_BLOCK_PCI_MMCONF select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
select SOC_AMD_COMMON_BLOCK_PSP_GEN2 select SOC_AMD_COMMON_BLOCK_PSP_GEN2

3
src/soc/amd/cezanne/early_fch.c
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@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/acpimmio.h> #include <amdblocks/acpimmio.h>
#include <amdblocks/lpc.h>
#include <amdblocks/smbus.h> #include <amdblocks/smbus.h>
#include <console/console.h> #include <console/console.h>
#include <soc/southbridge.h> #include <soc/southbridge.h>
@@ -9,6 +10,8 @@
/* Before console init */ /* Before console init */
void fch_pre_init(void) void fch_pre_init(void)
{ {
lpc_early_init();
enable_acpimmio_decode_pm04(); enable_acpimmio_decode_pm04();
fch_smbus_init(); fch_smbus_init();
fch_enable_cf9_io(); fch_enable_cf9_io();

7
src/soc/amd/cezanne/include/soc/acpi.h Normal file
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@@ -0,0 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef AMD_CEZANNE_ACPI_H
#define AMD_CEZANNE_ACPI_H
#endif /* AMD_CEZANNE_ACPI_H */

1
src/soc/amd/cezanne/include/soc/iomap.h
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@@ -4,6 +4,7 @@
#define AMD_CEZANNE_IOMAP_H #define AMD_CEZANNE_IOMAP_H
/* MMIO Ranges */ /* MMIO Ranges */
#define SPI_BASE_ADDRESS 0xfec10000
/* FCH AL2AHB Registers */ /* FCH AL2AHB Registers */
#define ALINK_AHB_ADDRESS 0xfedc0000 #define ALINK_AHB_ADDRESS 0xfedc0000

15
src/soc/amd/cezanne/include/soc/southbridge.h
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@@ -8,6 +8,17 @@
/* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */ /* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */
#define PWR_RESET_CFG 0x10 #define PWR_RESET_CFG 0x10
#define TOGGLE_ALL_PWR_GOOD (1 << 1) #define TOGGLE_ALL_PWR_GOOD (1 << 1)
#define PM_SERIRQ_CONF 0x54
#define PM_SERIRQ_NUM_BITS_17 0x0000
#define PM_SERIRQ_NUM_BITS_18 0x0004
#define PM_SERIRQ_NUM_BITS_19 0x0008
#define PM_SERIRQ_NUM_BITS_20 0x000c
#define PM_SERIRQ_NUM_BITS_21 0x0010
#define PM_SERIRQ_NUM_BITS_22 0x0014
#define PM_SERIRQ_NUM_BITS_23 0x0018
#define PM_SERIRQ_NUM_BITS_24 0x001c
#define PM_SERIRQ_MODE BIT(6)
#define PM_SERIRQ_ENABLE BIT(7)
#define PM_EVT_BLK 0x60 #define PM_EVT_BLK 0x60
#define WAK_STS BIT(15) /*AcpiPmEvtBlkx00 Pm1Status */ #define WAK_STS BIT(15) /*AcpiPmEvtBlkx00 Pm1Status */
#define PCIEXPWAK_STS BIT(14) #define PCIEXPWAK_STS BIT(14)
@@ -39,6 +50,10 @@
#define PM_ACPI_WAKE_AS_GEVENT BIT(27) #define PM_ACPI_WAKE_AS_GEVENT BIT(27)
#define PM_ACPI_NB_PME_GEVENT BIT(28) #define PM_ACPI_NB_PME_GEVENT BIT(28)
#define PM_ACPI_RTC_WAKE_EN BIT(29) #define PM_ACPI_RTC_WAKE_EN BIT(29)
#define PM_LPC_GATING 0xec
#define PM_LPC_AB_NO_BYPASS_EN BIT(2)
#define PM_LPC_A20_EN BIT(1)
#define PM_LPC_ENABLE BIT(0)
#define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */ #define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */