From 5ebe4310875f5eb01bda69c144204ba8d89f967e Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 26 Sep 2019 08:47:40 +0200 Subject: [PATCH 01/75] lib/bootsplash: Fix compilation Add missing include. Tested on Supermicro X11SSH-TF. Change-Id: Id0c80ac646001a497e96cae4d48a0f09762eb936 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/35613 Reviewed-by: Arthur Heymans Reviewed-by: Patrick Georgi Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/lib/bootsplash.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/lib/bootsplash.c b/src/lib/bootsplash.c index 812a3b7ccc..8364afa0b9 100644 --- a/src/lib/bootsplash.c +++ b/src/lib/bootsplash.c @@ -18,6 +18,7 @@ #include #include #include +#include #include "jpeg.h" From 0c9d8a4ef57aa96773815d60ed8e08af27af12fb Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 26 Sep 2019 08:56:38 +0200 Subject: [PATCH 02/75] configs: Build test CONFIG_BOOTSPLASH Change-Id: I306d107720d51c2b378f739f68c31b8642f7354a Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/35615 Reviewed-by: Arthur Heymans Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- configs/config.emulation_qemu_x86_i440fx_noserial | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/config.emulation_qemu_x86_i440fx_noserial b/configs/config.emulation_qemu_x86_i440fx_noserial index 66b46c76b8..2902d02a95 100644 --- a/configs/config.emulation_qemu_x86_i440fx_noserial +++ b/configs/config.emulation_qemu_x86_i440fx_noserial @@ -4,3 +4,5 @@ CONFIG_COLLECT_TIMESTAMPS=y CONFIG_CONSOLE_POST=y CONFIG_LINEAR_FRAMEBUFFER=y # CONFIG_CONSOLE_SERIAL is not set +CONFIG_BOOTSPLASH=y +CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y From 99655530110135ebf9eeaf3532d90c38fafd9ce9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 22 Sep 2019 11:22:11 +0200 Subject: [PATCH 03/75] mb/supermicro/x11-lga1151-series: remove unneeded vendor id config MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The vendor id option set here is useless as most SSVID registers get filled with 0x8086 (their VID) by default, anyway. Besides that the Kconfig option isn't meant for retrofit ports, cf. commit 7e1c83e31bd (Add Kconfig options to override Subsystem Vendor and Device ID). The right place would be the devicetree. Signed-off-by: Michael Niewöhner Change-Id: If67c679bb342f63096902535734106e4f1651118 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35524 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/mainboard/supermicro/x11-lga1151-series/Kconfig | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index 54be4e0104..6fc9aed7f0 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -64,10 +64,6 @@ config MAX_CPUS int default 8 -config SUBSYSTEM_VENDOR_ID - hex - default 0x8086 - config CONSOLE_POST bool default y From 55ef0d25d32ecabfec7dcd425793f972cbca890d Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Thu, 26 Sep 2019 12:05:27 -0600 Subject: [PATCH 04/75] device: add commentary to dev_find_slot() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit dev_find_slot() can sometimes fail to return the desired device object prior to full PCI enumeration. Comment the declaration and implementation accordingly to help the user understand the problem and avoid its usage. Change-Id: I3fe1f24ff015d3e4f272323947f057e4c910186c Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/c/coreboot/+/35632 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/device/device_const.c | 6 ++++++ src/include/device/device.h | 9 ++++++++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/src/device/device_const.c b/src/device/device_const.c index 5143563a87..27197f251c 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -24,6 +24,12 @@ DEVTREE_CONST struct device * DEVTREE_CONST all_devices = &dev_root; /** * Given a PCI bus and a devfn number, find the device structure. * + * Note that this function can return the incorrect device prior + * to PCI enumeration because the secondary field of the bus object + * is 0. The failing scenario is determined by the order of the + * devices in all_devices singly-linked list as well as the time + * when this function is called (secondary reflecting topology). + * * @param bus The bus number. * @param devfn A device/function number. * @return Pointer to the device structure (if found), 0 otherwise. diff --git a/src/include/device/device.h b/src/include/device/device.h index b2221ccea2..f24e4b2157 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -298,7 +298,14 @@ DEVTREE_CONST struct device *pcidev_path_on_bus(unsigned int bus, pci_devfn_t de DEVTREE_CONST struct device *pcidev_on_root(uint8_t dev, uint8_t fn); DEVTREE_CONST struct bus *pci_root_bus(void); -/* To be deprecated, avoid using. */ +/* To be deprecated, avoid using. + * + * Note that this function can return the incorrect device prior + * to PCI enumeration because the secondary field of the bus object + * is 0. The failing scenario is determined by the order of the + * devices in all_devices singly-linked list as well as the time + * when this function is called (secondary reflecting topology). + */ DEVTREE_CONST struct device *dev_find_slot(unsigned int bus, unsigned int devfn); DEVTREE_CONST struct device *pcidev_path_on_root_debug(pci_devfn_t devfn, const char *func); From b33a2b05afe2b309da5a608f3d17ffcf112c120a Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 26 Sep 2019 23:51:46 -0700 Subject: [PATCH 05/75] fmap: Add get_fmap_flash_offset() CB:35377 changed the behavior of find_fmap_directory() to return pointer to CBMEM_ID_FMAP if fmap is cached in cbmem. lb_boot_media_params() calls find_fmap_directory to add offset of fmap in flash to coreboot table. However, because of the change in behavior of find_fmap_directory(), it ended up adding 0 as the offset. This change adds a new function get_fmap_flash_offset() which returns the offset of fmap in flash. Ideally, all payloads should move to using the FMAP from CBMEM. However, in order to maintain compatibility with payloads which are not updated, ensure that fmap_offset is updated correctly. Since find_fmap_directory() is no longer used outside fmap.c, this change also removes it from fmap.h and limits scope to fmap.c. In a follow up patch, we need to push a change to libpayload to expose the fmap cache pointer to lib_sysinfo. BUG=b:141723751 Change-Id: I7ff6e8199143d1a992a83d7de1e3b44813b733f4 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/35639 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Aaron Durbin Reviewed-by: Shelley Chen --- src/include/fmap.h | 7 ++++--- src/lib/coreboot_table.c | 5 +---- src/lib/fmap.c | 7 ++++++- 3 files changed, 11 insertions(+), 8 deletions(-) diff --git a/src/include/fmap.h b/src/include/fmap.h index ab7e5ab895..649ecc0000 100644 --- a/src/include/fmap.h +++ b/src/include/fmap.h @@ -19,9 +19,6 @@ #include #include -/* Locate the fmap directory. Return 0 on success, < 0 on error. */ -int find_fmap_directory(struct region_device *fmrd); - /* Locate the named area in the fmap and fill in a region device representing * that area. The region is a sub-region of the readonly boot media. Return * 0 on success, < 0 on error. */ @@ -48,4 +45,8 @@ ssize_t fmap_read_area(const char *name, void *buffer, size_t size); /* Write provided buffer into fmap area. * Return size written on success, < 0 on error. */ ssize_t fmap_overwrite_area(const char *name, const void *buffer, size_t size); + +/* Get offset of FMAP in flash. */ +uint64_t get_fmap_flash_offset(void); + #endif diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 9c5942fa9d..d3576e6a32 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -256,7 +256,6 @@ static void lb_boot_media_params(struct lb_header *header) struct lb_boot_media_params *bmp; struct cbfs_props props; const struct region_device *boot_dev; - struct region_device fmrd; boot_device_init(); @@ -275,9 +274,7 @@ static void lb_boot_media_params(struct lb_header *header) bmp->cbfs_size = props.size; bmp->boot_media_size = region_device_sz(boot_dev); - bmp->fmap_offset = ~(uint64_t)0; - if (find_fmap_directory(&fmrd) == 0) - bmp->fmap_offset = region_device_offset(&fmrd); + bmp->fmap_offset = get_fmap_flash_offset(); } static void lb_ram_code(struct lb_header *header) diff --git a/src/lib/fmap.c b/src/lib/fmap.c index f0074186da..a427102210 100644 --- a/src/lib/fmap.c +++ b/src/lib/fmap.c @@ -31,7 +31,12 @@ static int fmap_print_once CAR_GLOBAL; static struct mem_region_device fmap_cache CAR_GLOBAL; -int find_fmap_directory(struct region_device *fmrd) +uint64_t get_fmap_flash_offset(void) +{ + return FMAP_OFFSET; +} + +static int find_fmap_directory(struct region_device *fmrd) { const struct region_device *boot; struct fmap *fmap; From 59de112995523f52cedbdbd5d1dd770f6f53b5d3 Mon Sep 17 00:00:00 2001 From: James Ye Date: Fri, 1 Feb 2019 13:29:02 +1100 Subject: [PATCH 06/75] mb/lenovo/x131e: correct USB port config Based on schematic and register dumps. Change-Id: I91fc47022988cfe986fb8c1ed21dc073ee7d16bc Signed-off-by: James Ye Reviewed-on: https://review.coreboot.org/c/coreboot/+/31365 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens Reviewed-by: Paul Menzel --- src/mainboard/lenovo/x131e/romstage.c | 28 +++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/src/mainboard/lenovo/x131e/romstage.c b/src/mainboard/lenovo/x131e/romstage.c index 79a2276fd0..5fc5df6b85 100644 --- a/src/mainboard/lenovo/x131e/romstage.c +++ b/src/mainboard/lenovo/x131e/romstage.c @@ -33,20 +33,20 @@ void mainboard_rcba_config(void) } const struct southbridge_usb_port mainboard_usb_ports[] = { - {1, 1, 0}, - {1, 1, 0}, - {0, 1, 1}, - {1, 1, 1}, - {1, 0, 2}, - {1, 0, 2}, - {0, 0, 3}, - {0, 0, 3}, - {0, 1, 4}, - {1, 1, 4}, - {0, 0, 5}, - {0, 0, 5}, - {0, 0, 6}, - {1, 0, 6}, + {1, 1, 0}, /* P0: USB 3.0 1 (OC0) */ + {1, 1, 0}, /* P1: USB 3.0 2 (OC0) */ + {0, 0, 0}, + {1, 1, -1}, /* P3: Camera (no OC) */ + {1, 0, -1}, /* P4: WLAN (no OC) */ + {1, 0, -1}, /* P5: WWAN (no OC) */ + {0, 0, 0}, + {0, 0, 0}, + {0, 0, 0}, + {1, 1, 4}, /* P9: USB 2.0 (AUO4) (OC4) */ + {0, 0, 0}, + {0, 0, 0}, + {0, 0, 0}, + {1, 0, -1}, /* P13: Bluetooth (no OC) */ }; void mainboard_get_spd(spd_raw_data *spd, bool id_only) From ef2e86edeba667dcb41fb5a752f695d603e5e5f0 Mon Sep 17 00:00:00 2001 From: James Ye Date: Tue, 12 Feb 2019 22:17:52 +1100 Subject: [PATCH 07/75] mb/lenovo/x131e: enable mSATA slot Per google/stout. Tested with SanDisk SSD U110. Change-Id: I7cc9837f572236acac2007e95990e64c25a5d6e2 Signed-off-by: James Ye Reviewed-on: https://review.coreboot.org/c/coreboot/+/31364 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens --- src/mainboard/lenovo/x131e/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index 2a98a60cac..2d15d87176 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -49,8 +49,8 @@ chip northbridge/intel/sandybridge register "gpi6_routing" = "2" register "gpi13_routing" = "2" - # Enable SATA ports - register "sata_port_map" = "0x1" + # Enable SATA ports 0 (2.5 inch) and 1 (mSATA) + register "sata_port_map" = "0x3" # Set max SATA speed to 6.0 Gb/s register "sata_interface_speed_support" = "0x3" From 965881b7ce202b8d1e114d23d90a156b9d6e2573 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 25 Sep 2019 13:18:52 +0200 Subject: [PATCH 08/75] Kconfig: Hide CONFIG_CBFS_SIZE when an FMDFILE is provided CONFIG_CBFS_SIZE should only be used as a parameter to generate the default FMAP. This also swaps around FMDFILE and CBFS_SIZE to avoid that the CBFS_SIZE entry disappears when filling in the FMDFILE entry below it. One advantage is that if code references CONFIG_CBFS_SIZE the jenkins buildtest will most likely fail as many boards provide an FMD file. Change-Id: Ic7926e1638d7fb49ba61af28d682315786c3c39e Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/35597 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Werner Zeh --- src/Kconfig | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index a1c016e30f..8fcb3ae8a3 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -346,18 +346,6 @@ config OVERRIDE_DEVICETREE Examples: "devicetree.variant-override.cb" "variant/devicetree-override.cb" -config CBFS_SIZE - hex "Size of CBFS filesystem in ROM" - # Default value set at the end of the file - help - This is the part of the ROM actually managed by CBFS, located at the - end of the ROM (passed through cbfstool -o) on x86 and at at the start - of the ROM (passed through cbfstool -s) everywhere else. It defaults - to span the whole ROM on all but Intel systems that use an Intel Firmware - Descriptor. It can be overridden to make coreboot live alongside other - components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE - binaries. - config FMDFILE string "fmap description file in fmd format" default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS @@ -367,6 +355,20 @@ config FMDFILE but in some cases more complex setups are required. When an fmd is specified, it overrides the default format. +config CBFS_SIZE + hex "Size of CBFS filesystem in ROM" + depends on FMDFILE = "" + # Default value set at the end of the file + help + This is the part of the ROM actually managed by CBFS, located at the + end of the ROM (passed through cbfstool -o) on x86 and at at the start + of the ROM (passed through cbfstool -s) everywhere else. It defaults + to span the whole ROM on all but Intel systems that use an Intel Firmware + Descriptor. It can be overridden to make coreboot live alongside other + components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE + binaries. This symbol should only be used to generate a default FMAP and + is unused when a non-default fmd file is provided via CONFIG_FMDFILE. + endmenu # load site-local kconfig to allow user specific defaults and overrides From 78d6ce45d4ec5a447ae5837497856c5af236a8d2 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Fri, 27 Sep 2019 07:13:46 +0530 Subject: [PATCH 09/75] mb/google/drallion: Set UART for console to UART controller 0 Drallion uses UART 0 for console, change the config accordindly. BUG=b:139095062 Change-Id: I0ae2f8459b6225b99b758180413afa22386355d4 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/35633 Reviewed-by: Bora Guvendik Reviewed-by: EricR Lai Tested-by: build bot (Jenkins) --- src/mainboard/google/drallion/Kconfig | 2 +- src/mainboard/google/drallion/variants/drallion/devicetree.cb | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index a2ed3d86f9..97d0b51a8d 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -91,7 +91,7 @@ config MAX_CPUS config UART_FOR_CONSOLE int - default 2 + default 0 config VARIANT_DIR string diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index d824a552d0..956e54edf9 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -389,7 +389,7 @@ chip soc/intel/cannonlake end end # I2C #4 device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 + device pci 19.2 off end # UART #2 device pci 1a.0 off end # eMMC device pci 1c.0 off end # PCI Express Port 1 (USB) device pci 1c.1 off end # PCI Express Port 2 (USB) @@ -408,7 +408,7 @@ chip soc/intel/cannonlake device pci 1d.4 on smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" end # PCI Express Port 13 (x4) - device pci 1e.0 off end # UART #0 + device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 From f3c485e21f2c23421da7ed33fc466efe1e52ddc0 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Fri, 27 Sep 2019 10:20:48 +0530 Subject: [PATCH 10/75] mb/google/variants/drallion: Update the spd index map BUG=b:141575294 Change-Id: I1b2b4362b84b170bd73b760828ca300ec86c4534 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/35636 Tested-by: build bot (Jenkins) Reviewed-by: EricR Lai --- src/mainboard/google/drallion/variants/drallion/memory.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/drallion/variants/drallion/memory.c b/src/mainboard/google/drallion/variants/drallion/memory.c index 10996a3e7b..37d009adf9 100644 --- a/src/mainboard/google/drallion/variants/drallion/memory.c +++ b/src/mainboard/google/drallion/variants/drallion/memory.c @@ -23,8 +23,8 @@ static const int spd_index[32] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 4, 3, 6, 1, 0, 0, 0, 0, - 5, 0, 7, 2, 0, 0, 0, 0 + 0, 4, 3, 6, 1, 0, 0, 0, + 0, 5, 0, 7, 2, 0, 0, 0 }; const struct cnl_mb_cfg *get_variant_memory_cfg(struct cnl_mb_cfg *mem_cfg) From 3b8deeefa500a79958b0dd3428e2919ecfb794b1 Mon Sep 17 00:00:00 2001 From: Alexander Couzens Date: Fri, 16 Jun 2017 14:45:08 +0200 Subject: [PATCH 11/75] superiotool: add basic support for SCH5545 Based on the SCH5627 datasheet which is similiar SCH5545 id 0xc4, SCH5627 id 0xc6. Change-Id: I81f3f68690d2000a4fa8a1e703c01f54ebbce953 Signed-off-by: Alexander Couzens Reviewed-on: https://review.coreboot.org/c/coreboot/+/20237 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- util/superiotool/smsc.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/util/superiotool/smsc.c b/util/superiotool/smsc.c index 2fe940c97f..ab61ba4d19 100644 --- a/util/superiotool/smsc.c +++ b/util/superiotool/smsc.c @@ -972,6 +972,39 @@ static const struct superio_registers reg_table[] = { {0x66, "FDC37C666GT", { /* Init: 0x55, 0x55. Exit: 0xaa. Port: 0x3f0. Chiprev: 0x02. */ {EOT}}}, + {0xc4, "SCH5545", { + /* based on SCH5627 datasheet */ + /* Init: 0x55. Exit: 0xaa. */ + {0x7, "COM1", + {0x30, 0xf0, EOT}, + {0x00, 0x00, EOT}}, + {0x0c, "LPC Interface", + {0x30, + /* IRQ config */ + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, + 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, + /* DMA Channel 0 - 7 */ + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, + 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, + /* BAR configuration port */ + 0x60, 0x61, 0x62, 0x63, + /* BAR EMI */ + 0x64, 0x65, 0x66, 0x67, + /* BAR UART1 */ + 0x68, 0x69, 0x6a, 0x6b, + /* BAR UART2 */ + 0x6c, 0x6d, 0x6e, 0x6f, + /* BAR Runtime Registers */ + 0x70, 0x71, 0x72, 0x73, + /* BAR 8042 */ + 0x78, 0x79, 0x7a, 0x7b, + /* BAR Floppy Disk Controller */ + 0x7c, 0x7d, 0x7e, 0x7f, + /* BAR Parallel Port */ + 0x80, 0x81, 0x82, 0x83, + EOT}, + {EOT}}, + {EOT}}}, {EOT} }; @@ -1043,6 +1076,13 @@ static void probe_idregs_smsc_helper(uint16_t port, uint8_t idreg, else printf("Runtime Register Block not mapped on this Super I/O.\n"); break; + case 0xc4: /* SMSC5545 */ + /* choose LPC interface */ + regwrite(port, LDN_SEL, 0x0c); + runtime_base = regval(port, 0x73) << 8; + runtime_base |= regval(port, 0x72); + dump_io(runtime_base, 0x34); + break; default: printf("No extra registers known for this chip.\n"); } From 197a3c6cea86cb92c10c05c710dd4184c0e7ba72 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 27 Sep 2019 14:32:20 +0300 Subject: [PATCH 12/75] nb/intel/x4x: Avoid x4x.h header with romcc-bootblock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: If8b70298bffd72d1de7f74917131d648c5fcab66 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35641 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/x4x/bootblock.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c index 1dfdf19ea4..e733287e93 100644 --- a/src/northbridge/intel/x4x/bootblock.c +++ b/src/northbridge/intel/x4x/bootblock.c @@ -16,7 +16,10 @@ #include #include "iomap.h" -#include "x4x.h" + +/* Just re-define these instead of including x4x.h. It blows up romcc. */ +#define D0F0_PCIEXBAR_LO 0x60 +#define D0F0_PCIEXBAR_HI 0x64 static void bootblock_northbridge_init(void) { From d7205bebd53761e17e22701ca0573ffa5629d38e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 27 Sep 2019 07:24:17 +0300 Subject: [PATCH 13/75] nb,sb/intel: Clean up some __BOOTBLOCK__ and __SIMPLE_DEVICE__ use MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ie3f3c043daa6ec18ed14929668e5acae172177b3 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35603 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/northbridge/intel/fsp_rangeley/northbridge.h | 2 -- src/northbridge/intel/gm45/gm45.h | 2 -- src/northbridge/intel/haswell/haswell.h | 6 +----- src/northbridge/intel/sandybridge/sandybridge.h | 2 -- src/northbridge/intel/x4x/x4x.h | 6 ++---- src/southbridge/intel/i82801dx/i82801dx.h | 9 ++++----- 6 files changed, 7 insertions(+), 20 deletions(-) diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h index 160d75477a..8375fbf38c 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.h +++ b/src/northbridge/intel/fsp_rangeley/northbridge.h @@ -63,9 +63,7 @@ void rangeley_late_initialization(void); u32 sideband_read(int port, int reg); void sideband_write(int port, int reg, long data); -#ifndef __SIMPLE_DEVICE__ void northbridge_acpi_fill_ssdt_generator(struct device *device); -#endif #endif /* #ifndef __ASSEMBLER__ */ #endif /* #ifndef __ACPI__ */ diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 5d437583f2..430afe4077 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -449,12 +449,10 @@ int get_blc_values(const struct blc_pwm_t **entries); u16 get_blc_pwm_freq_value(const char *edid_ascii_string); -#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) #include struct acpi_rsdp; unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long start, struct acpi_rsdp *rsdp); -#endif #endif /* !__ACPI__ */ #endif /* __NORTHBRIDGE_INTEL_GM45_GM45_H__ */ diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 55c0b4b24b..9de0cfb2c3 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -208,24 +208,20 @@ #ifndef __ASSEMBLER__ static inline void barrier(void) { asm("" ::: "memory"); } -#ifdef __SMM__ void intel_northbridge_haswell_finalize_smm(void); -#else /* !__SMM__ */ + void haswell_early_initialization(int chipset_type); void haswell_late_initialization(void); void set_translation_table(int start, int end, u64 base, int inc); void haswell_unhide_peg(void); void report_platform_info(void); -#endif /* !__SMM__ */ -#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) #include struct acpi_rsdp; unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long start, struct acpi_rsdp *rsdp); -#endif #endif #endif diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index b488f2c249..b598c9b6e9 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -227,12 +227,10 @@ int mainboard_should_reset_usb(int s3resume); void perform_raminit(int s3resume); enum platform_type get_platform_type(void); -#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) #include struct acpi_rsdp; unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long start, struct acpi_rsdp *rsdp); -#endif #endif #endif diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 57723364ab..05479a1602 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -368,7 +368,6 @@ enum ddr2_signals { CTRL3, }; -#ifndef __BOOTBLOCK__ void x4x_early_init(void); void x4x_late_init(int s3resume); u32 decode_igd_memory_size(u32 gms); @@ -411,10 +410,9 @@ extern const u32 ddr3_c2_tab[2][3][6][2]; extern const u8 ddr3_c2_x264[3][6]; extern const u16 ddr3_c2_x23c[3][6]; +#include struct acpi_rsdp; -#ifndef __SIMPLE_DEVICE__ unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long start, struct acpi_rsdp *rsdp); -#endif /* __SIMPLE_DEVICE__ */ -#endif + #endif /* __NORTHBRIDGE_INTEL_X4X_H__ */ diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index ac53ae13a3..9aa3017b00 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -30,14 +30,13 @@ #include #if !defined(__ASSEMBLER__) -#if !defined(__SIMPLE_DEVICE__) + +#include #include "chip.h" -extern void i82801dx_enable(struct device *dev); -#else + +void i82801dx_enable(struct device *dev); void enable_smbus(void); int smbus_read_byte(unsigned device, unsigned address); -#endif - void aseg_smm_lock(void); #endif From 13ad74070165d2d48f8546f9dd9da7e354e5ee4a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 27 Sep 2019 11:59:21 +0300 Subject: [PATCH 14/75] device/pci: Replace some __SIMPLE_DEVICE__ use MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ide9df46b5ff47fea54b9de0e365638a6223c8267 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35642 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/include/device/pci_ops.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index 5cc803c737..5371e07419 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -178,7 +178,7 @@ void pci_update_config32(const struct device *dev, u16 reg, u32 mask, u32 or) u16 pci_s_find_next_capability(pci_devfn_t dev, u16 cap, u16 last); u16 pci_s_find_capability(pci_devfn_t dev, u16 cap); -#ifndef __SIMPLE_DEVICE__ +#ifndef __ROMCC__ static __always_inline u16 pci_find_next_capability(const struct device *dev, u16 cap, u16 last) { From f485d91141950dbb094d167f7f57118f5564fa22 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 27 Sep 2019 16:54:44 +0300 Subject: [PATCH 15/75] nb/via/vx900: Remove some __SIMPLE_DEVICE__ use MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I840131f91e79c740c0c8784c252723ae90ded458 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35647 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/northbridge/via/vx900/chrome9hd.c | 2 +- src/northbridge/via/vx900/lpc.c | 2 +- src/northbridge/via/vx900/pci_util.c | 6 +----- src/northbridge/via/vx900/vx900.h | 4 ---- 4 files changed, 3 insertions(+), 11 deletions(-) diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c index 163f6b1da0..fef53502f8 100644 --- a/src/northbridge/via/vx900/chrome9hd.c +++ b/src/northbridge/via/vx900/chrome9hd.c @@ -240,7 +240,7 @@ static void chrome9hd_init(struct device *dev) printk(BIOS_DEBUG, "Enable VGA console\n"); - dump_pci_device(dev); + dump_pci_device(PCI_BDF(dev)); } static void chrome9hd_enable(struct device *dev) diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c index 41ea1545cf..cab783e5ba 100644 --- a/src/northbridge/via/vx900/lpc.c +++ b/src/northbridge/via/vx900/lpc.c @@ -180,7 +180,7 @@ static void vx900_lpc_init(struct device *dev) { vx900_lpc_interrupt_stuff(dev); vx900_lpc_misc_stuff(dev); - dump_pci_device(dev); + dump_pci_device(PCI_BDF(dev)); } static void vx900_lpc_read_resources(struct device *dev) diff --git a/src/northbridge/via/vx900/pci_util.c b/src/northbridge/via/vx900/pci_util.c index e6eb91ac95..57b08e7586 100644 --- a/src/northbridge/via/vx900/pci_util.c +++ b/src/northbridge/via/vx900/pci_util.c @@ -19,11 +19,7 @@ #include "vx900.h" -#ifdef __SIMPLE_DEVICE__ void dump_pci_device(pci_devfn_t dev) -#else -void dump_pci_device(struct device *dev) -#endif { int i; for (i = 0; i <= 0xff; i++) { @@ -34,7 +30,7 @@ void dump_pci_device(struct device *dev) if ((i & 0x0f) == 0x08) printk(BIOS_DEBUG, " |"); - val = pci_read_config8(dev, i); + val = pci_s_read_config8(dev, i); printk(BIOS_DEBUG, " %.2x", val); if ((i & 0x0f) == 0x0f) diff --git a/src/northbridge/via/vx900/vx900.h b/src/northbridge/via/vx900/vx900.h index 96d821ac4d..1f611535aa 100644 --- a/src/northbridge/via/vx900/vx900.h +++ b/src/northbridge/via/vx900/vx900.h @@ -39,10 +39,6 @@ uint64_t get_uma_memory_base(void); /* We use these throughout the code. They really belong in a generic part of * coreboot, but until bureaucracy gets them there, we still need them */ -#ifdef __SIMPLE_DEVICE__ void dump_pci_device(pci_devfn_t dev); -#else -void dump_pci_device(struct device *dev); -#endif #endif /* __VX900_H */ From a67eaec0d03213ccfbac2f1805b4de900fe9b123 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 27 Sep 2019 11:59:21 +0300 Subject: [PATCH 16/75] arch/arm,mips: Use generic PCI MMCONF MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We need the stub header file. If PCI was implemented, assume generic MMIO mapped configuration space would work here. Change-Id: Ia731e5c5a6725fe22ab8b0398cafa1127ed90891 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35648 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/arch/arm/include/arch/pci_ops.h | 12 +----------- src/arch/mips/include/arch/pci_ops.h | 12 +----------- 2 files changed, 2 insertions(+), 22 deletions(-) diff --git a/src/arch/arm/include/arch/pci_ops.h b/src/arch/arm/include/arch/pci_ops.h index 4cb05e7c88..8389f3c4e4 100644 --- a/src/arch/arm/include/arch/pci_ops.h +++ b/src/arch/arm/include/arch/pci_ops.h @@ -14,16 +14,6 @@ #ifndef ARCH_ARM_PCI_OPS_H #define ARCH_ARM_PCI_OPS_H -#include -#include - -#ifdef __SIMPLE_DEVICE__ -u8 pci_read_config8(pci_devfn_t dev, unsigned int where); -u16 pci_read_config16(pci_devfn_t dev, unsigned int where); -u32 pci_read_config32(pci_devfn_t dev, unsigned int where); -void pci_write_config8(pci_devfn_t dev, unsigned int where, u8 val); -void pci_write_config16(pci_devfn_t dev, unsigned int where, u16 val); -void pci_write_config32(pci_devfn_t dev, unsigned int where, u32 val); -#endif +#include #endif diff --git a/src/arch/mips/include/arch/pci_ops.h b/src/arch/mips/include/arch/pci_ops.h index 5be52aa3fb..da397cf3b8 100644 --- a/src/arch/mips/include/arch/pci_ops.h +++ b/src/arch/mips/include/arch/pci_ops.h @@ -14,16 +14,6 @@ #ifndef ARCH_MIPS_PCI_OPS_H #define ARCH_MIPS_PCI_OPS_H -#include -#include - -#ifdef __SIMPLE_DEVICE__ -u8 pci_read_config8(pci_devfn_t dev, unsigned int where); -u16 pci_read_config16(pci_devfn_t dev, unsigned int where); -u32 pci_read_config32(pci_devfn_t dev, unsigned int where); -void pci_write_config8(pci_devfn_t dev, unsigned int where, u8 val); -void pci_write_config16(pci_devfn_t dev, unsigned int where, u16 val); -void pci_write_config32(pci_devfn_t dev, unsigned int where, u32 val); -#endif +#include #endif From 8f5138d8a510d98e13e49d84afeaa8a075563571 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 27 Sep 2019 18:08:20 +0300 Subject: [PATCH 17/75] drivers/net/ne2k: Remove some __SIMPLE_DEVICE__ use MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Note that the code assumes mainboard code to configure any PCI bridges prior to calling console_init(). Change-Id: I0312d359f153c02e4afcf1c09d79f9eb3019a8b2 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35650 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/drivers/net/ne2k.c | 31 ++++++++++++------------------- 1 file changed, 12 insertions(+), 19 deletions(-) diff --git a/src/drivers/net/ne2k.c b/src/drivers/net/ne2k.c index e3dd948a83..c7b53e4e7b 100644 --- a/src/drivers/net/ne2k.c +++ b/src/drivers/net/ne2k.c @@ -197,7 +197,8 @@ static void ns8390_tx_header(unsigned int eth_nic_base, int pktlen) eth_pio_write(hdr, (TX_START << 8), sizeof(hdr), eth_nic_base); } -void ne2k_transmit(unsigned int eth_nic_base) { +void ne2k_transmit(unsigned int eth_nic_base) +{ unsigned int pktsize; unsigned int len = get_count(eth_nic_base); @@ -226,8 +227,6 @@ void ne2k_transmit(unsigned int eth_nic_base) { set_count(eth_nic_base, 0); } -#if !ENV_RAMSTAGE - static void ns8390_reset(unsigned int eth_nic_base) { int i; @@ -267,24 +266,23 @@ static void ns8390_reset(unsigned int eth_nic_base) set_count(eth_nic_base, 0); } -int ne2k_init(unsigned int eth_nic_base) { - -#ifdef __SIMPLE_DEVICE__ +int ne2k_init(unsigned int eth_nic_base) +{ pci_devfn_t dev; -#else - struct device *dev; -#endif unsigned char c; - /* Power management controller */ - dev = pci_locate_device(PCI_ID(0x10ec, - 0x8029), 0); + /* FIXME: This console is not enabled for bootblock. */ + if (!ENV_ROMSTAGE) + return 0; + /* For this to work, mainboard code must have configured + PCI bridges prior to calling console_init(). */ + dev = pci_locate_device(PCI_ID(0x10ec, 0x8029), 0); if (dev == PCI_DEV_INVALID) return 0; - pci_write_config32(dev, 0x10, eth_nic_base | 1); - pci_write_config8(dev, 0x4, 0x1); + pci_s_write_config32(dev, 0x10, eth_nic_base | 1); + pci_s_write_config8(dev, 0x4, 0x1); c = inb(eth_nic_base + NE_ASIC_OFFSET + NE_RESET); outb(c, eth_nic_base + NE_ASIC_OFFSET + NE_RESET); @@ -302,9 +300,6 @@ int ne2k_init(unsigned int eth_nic_base) { return 1; } -#else -int ne2k_init(unsigned int eth_nic_base) { return 0; } // dummy symbol for ramstage - static void read_resources(struct device *dev) { struct resource *res; @@ -333,5 +328,3 @@ static const struct pci_driver ne2k_driver __pci_driver = { .vendor = 0x10ec, .device = 0x8029, }; - -#endif /* !ENV_RAMSTAGE */ From f2cc3dd8eaa14f1253cdab0326d5aa575d6ac354 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 27 Sep 2019 18:09:52 +0300 Subject: [PATCH 18/75] usbdebug: Remove some __SIMPLE_DEVICE__ use MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We can always PCI config accessors with pci_devfn_t. Change-Id: I6d98c2441cc870cdcadbe8fabc9f35b9ffc652d8 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35651 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/drivers/usb/pci_ehci.c | 33 +++++++++++---------------------- 1 file changed, 11 insertions(+), 22 deletions(-) diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c index 34684cb09a..1e755249b1 100644 --- a/src/drivers/usb/pci_ehci.c +++ b/src/drivers/usb/pci_ehci.c @@ -33,45 +33,39 @@ static struct device_operations ehci_dbg_ops; int ehci_debug_hw_enable(unsigned int *base, unsigned int *dbg_offset) { - pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX); + pci_devfn_t dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX); /* We only support controllers on bus 0. */ - if (PCI_DEV2SEGBUS(dbg_dev) != 0) + if (PCI_DEV2SEGBUS(dev) != 0) return -1; -#ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev = dbg_dev; -#else - struct device *dev = pcidev_path_on_root(PCI_DEV2DEVFN(dbg_dev)); -#endif - - u32 class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8; + u32 class = pci_s_read_config32(dev, PCI_CLASS_REVISION) >> 8; if (class != PCI_EHCI_CLASSCODE) return -1; - u8 pm_cap = pci_s_find_capability(dbg_dev, PCI_CAP_ID_PM); + u8 pm_cap = pci_s_find_capability(dev, PCI_CAP_ID_PM); if (pm_cap) { - u16 pm_ctrl = pci_read_config16(dev, pm_cap + PCI_PM_CTRL); + u16 pm_ctrl = pci_s_read_config16(dev, pm_cap + PCI_PM_CTRL); /* Set to D0 and disable PM events. */ pm_ctrl &= ~PCI_PM_CTRL_PME_ENABLE; pm_ctrl &= ~PCI_PM_CTRL_STATE_MASK; - pci_write_config16(dev, pm_cap + PCI_PM_CTRL, pm_ctrl); + pci_s_write_config16(dev, pm_cap + PCI_PM_CTRL, pm_ctrl); } - u8 pos = pci_s_find_capability(dbg_dev, PCI_CAP_ID_EHCI_DEBUG); + u8 pos = pci_s_find_capability(dev, PCI_CAP_ID_EHCI_DEBUG); if (!pos) return -1; - u32 cap = pci_read_config32(dev, pos); + u32 cap = pci_s_read_config32(dev, pos); /* FIXME: We should remove static EHCI_BAR_INDEX. */ u8 ehci_bar = 0x10 + 4 * ((cap >> 29) - 1); if (ehci_bar != EHCI_BAR_INDEX) return -1; - pci_write_config32(dev, ehci_bar, CONFIG_EHCI_BAR); + pci_s_write_config32(dev, ehci_bar, CONFIG_EHCI_BAR); - pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | + pci_s_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); *base = CONFIG_EHCI_BAR; @@ -125,11 +119,6 @@ void pci_ehci_read_resources(struct device *dev) u8 *pci_ehci_base_regs(pci_devfn_t sdev) { -#ifdef __SIMPLE_DEVICE__ - u8 *base = (u8 *)(pci_read_config32(sdev, EHCI_BAR_INDEX) & ~0x0f); -#else - struct device *dev = pcidev_path_on_root(PCI_DEV2DEVFN(sdev)); - u8 *base = (u8 *)(pci_read_config32(dev, EHCI_BAR_INDEX) & ~0x0f); -#endif + u8 *base = (u8 *)(pci_s_read_config32(sdev, EHCI_BAR_INDEX) & ~0x0f); return base + HC_LENGTH(read32(base)); } From 44da9e201c58faf94ad22ec0fe18b693fd9d1239 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 27 Sep 2019 15:02:32 +0300 Subject: [PATCH 19/75] cpu,device/: Remove some __SIMPLE_DEVICE__ and __ROMCC__ use MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I62d7450c8e83eec7bf4ad5d0709269a132fd0499 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35649 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/arch/x86/include/arch/cpu.h | 6 +++--- src/cpu/x86/mtrr/earlymtrr.c | 3 --- src/include/cpu/cpu.h | 9 +++++---- src/include/device/pci.h | 9 ++++----- 4 files changed, 12 insertions(+), 15 deletions(-) diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 263b734529..ffa532b47e 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -214,7 +214,8 @@ static inline bool cpu_is_intel(void) return CONFIG(CPU_INTEL_COMMON) || CONFIG(SOC_INTEL_COMMON); } -#ifndef __SIMPLE_DEVICE__ +#ifndef __ROMCC__ +/* romcc does not support anonymous structs. */ struct device; @@ -258,9 +259,8 @@ static inline struct cpu_info *cpu_info(void) ); return ci; } -#endif -#ifndef __ROMCC__ // romcc is segfaulting in some cases +/* romcc is segfaulting in some cases. */ struct cpuinfo_x86 { uint8_t x86; /* CPU family */ uint8_t x86_vendor; /* CPU vendor */ diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index 5d7ff2cf45..02dfbdc80d 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -38,9 +38,6 @@ int get_free_var_mtrr(void) return -1; } -#ifdef __ROMCC__ -static -#endif void set_var_mtrr( unsigned int reg, unsigned int base, unsigned int size, unsigned int type) diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index 9a283735d3..cdb681729e 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -3,7 +3,6 @@ #include -#if !defined(__ROMCC__) void cpu_initialize(unsigned int cpu_index); /* Returns default APIC id based on logical_cpu number or < 0 on failure. */ int cpu_get_apic_id(int logical_cpu); @@ -14,13 +13,15 @@ void initialize_cpus(struct bus *cpu_bus); asmlinkage void secondary_cpu_init(unsigned int cpu_index); int cpu_phys_address_size(void); +#if ENV_RAMSTAGE #define __cpu_driver __attribute__((used, __section__(".rodata.cpu_driver"))) -#ifndef __SIMPLE_DEVICE__ +#else +#define __cpu_driver __attribute__((unused)) +#endif + /** start of compile time generated pci driver array */ extern struct cpu_driver _cpu_drivers[]; /** end of compile time generated pci driver array */ extern struct cpu_driver _ecpu_drivers[]; -#endif -#endif /* !__ROMCC__ */ #endif /* CPU_CPU_H */ diff --git a/src/include/device/pci.h b/src/include/device/pci.h index fa695d440f..8d6a9ae520 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -55,11 +55,12 @@ struct msix_entry { u32 vec_control; }; -#ifdef __SIMPLE_DEVICE__ -#define __pci_driver __attribute__((unused)) -#else +#if ENV_RAMSTAGE #define __pci_driver __attribute__((used, __section__(".rodata.pci_driver"))) +#else +#define __pci_driver __attribute__((unused)) #endif + /** start of compile time generated pci driver array */ extern struct pci_driver _pci_drivers[]; /** end of compile time generated pci driver array */ @@ -119,12 +120,10 @@ void pci_early_mmio_window(pci_devfn_t p2p_bridge, u32 mmio_base, u32 mmio_size); int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base); -#ifndef __ROMCC__ static inline int pci_base_address_is_memory_space(unsigned int attr) { return (attr & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY; } -#endif #endif /* CONFIG_PCI */ From 32d47eb688390d08e0f3f839df69371b55af8889 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 28 Sep 2019 00:00:30 +0300 Subject: [PATCH 20/75] soc/intel: Rename MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The filename chip.h has a special purpose with the generation of static devicetree, where the configuration structure name matches the path to the chip.h file. For example, soc/intel/skylake/chip.h defines struct soc_intel_skylake_config. The renamed file did not follow this convention and the structure it defines would conflict with one defined soc/intel/common/chip.h if such is ever added. Change-Id: Id3d56bf092c6111d2293136865b053b095e92d6b Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35657 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Furquan Shaikh --- src/soc/intel/apollolake/chip.c | 2 +- src/soc/intel/apollolake/chip.h | 2 +- src/soc/intel/cannonlake/chip.c | 2 +- src/soc/intel/cannonlake/chip.h | 2 +- src/soc/intel/cannonlake/lockdown.c | 2 +- src/soc/intel/cannonlake/romstage/romstage.c | 2 +- src/soc/intel/common/block/cpu/mp_init.c | 2 +- src/soc/intel/common/block/gspi/gspi.c | 2 +- src/soc/intel/common/block/i2c/i2c.c | 2 +- .../common/block/include/intelblocks/{chip.h => cfg.h} | 6 +++--- src/soc/intel/common/block/scs/mmc.c | 2 +- src/soc/intel/common/block/thermal/thermal.c | 2 +- src/soc/intel/common/pch/lockdown/lockdown.c | 2 +- src/soc/intel/icelake/chip.c | 2 +- src/soc/intel/icelake/chip.h | 2 +- src/soc/intel/icelake/lockdown.c | 2 +- src/soc/intel/icelake/romstage/romstage.c | 2 +- src/soc/intel/skylake/chip.c | 2 +- src/soc/intel/skylake/chip.h | 2 +- src/soc/intel/skylake/chip_fsp20.c | 2 +- src/soc/intel/skylake/i2c.c | 2 +- src/soc/intel/skylake/lockdown.c | 2 +- 22 files changed, 24 insertions(+), 24 deletions(-) rename src/soc/intel/common/block/include/intelblocks/{chip.h => cfg.h} (92%) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index b69f9eeeef..b7159efaec 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -28,7 +28,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index b9e368cddc..85cfff9af5 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -20,7 +20,7 @@ #define _SOC_APOLLOLAKE_CHIP_H_ #include -#include +#include #include #include #include diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 4e0dba5cea..c0810fb2ea 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 451c920fae..b937699c3c 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -18,7 +18,7 @@ #ifndef _SOC_CHIP_H_ #define _SOC_CHIP_H_ -#include +#include #include #include #include diff --git a/src/soc/intel/cannonlake/lockdown.c b/src/soc/intel/cannonlake/lockdown.c index e2fcc3a46e..ba68aa385c 100644 --- a/src/soc/intel/cannonlake/lockdown.c +++ b/src/soc/intel/cannonlake/lockdown.c @@ -14,7 +14,7 @@ */ #include -#include +#include #include #include diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index ba583b9a6e..f782f63622 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index e0cee1771e..2c5061f1d6 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index f937bd6eed..33f376ee77 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index 854a61a884..fb7aea2c17 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -21,7 +21,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/intel/common/block/include/intelblocks/chip.h b/src/soc/intel/common/block/include/intelblocks/cfg.h similarity index 92% rename from src/soc/intel/common/block/include/intelblocks/chip.h rename to src/soc/intel/common/block/include/intelblocks/cfg.h index 1e830d5d17..e7e381bfe4 100644 --- a/src/soc/intel/common/block/include/intelblocks/chip.h +++ b/src/soc/intel/common/block/include/intelblocks/cfg.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef SOC_INTEL_COMMON_BLOCK_CHIP_H -#define SOC_INTEL_COMMON_BLOCK_CHIP_H +#ifndef SOC_INTEL_COMMON_BLOCK_CFG_H +#define SOC_INTEL_COMMON_BLOCK_CFG_H #include #include @@ -42,4 +42,4 @@ struct soc_intel_common_config { /* This function to retrieve soc config structure required by common code */ const struct soc_intel_common_config *chip_get_common_soc_structure(void); -#endif /* SOC_INTEL_COMMON_BLOCK_CHIP_H */ +#endif /* SOC_INTEL_COMMON_BLOCK_CFG_H */ diff --git a/src/soc/intel/common/block/scs/mmc.c b/src/soc/intel/common/block/scs/mmc.c index 5b2e2c7d33..4ff3ac5e7e 100644 --- a/src/soc/intel/common/block/scs/mmc.c +++ b/src/soc/intel/common/block/scs/mmc.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include static int mmc_write_dll_reg(void *bar, uint32_t reg, uint32_t val) diff --git a/src/soc/intel/common/block/thermal/thermal.c b/src/soc/intel/common/block/thermal/thermal.c index 39a98a41d8..8f2fd49da2 100644 --- a/src/soc/intel/common/block/thermal/thermal.c +++ b/src/soc/intel/common/block/thermal/thermal.c @@ -15,7 +15,7 @@ #include #include -#include +#include #include #include diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index 99d8a35ea7..4a3209e03e 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -14,7 +14,7 @@ */ #include -#include +#include #include #include #include diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index c4abb0c3f7..e71c573f98 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index 72596c46e2..fc9341c58b 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -16,7 +16,7 @@ #ifndef _SOC_CHIP_H_ #define _SOC_CHIP_H_ -#include +#include #include #include #include diff --git a/src/soc/intel/icelake/lockdown.c b/src/soc/intel/icelake/lockdown.c index 8fa5e154f2..85a93c7c8e 100644 --- a/src/soc/intel/icelake/lockdown.c +++ b/src/soc/intel/icelake/lockdown.c @@ -14,7 +14,7 @@ */ #include -#include +#include #include #include diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 3d21a45e33..2c4ba67e04 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 212c24467e..ddb29327a1 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index fee14d8d7e..70fb045baf 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index d1d7d6f50a..e46e52ccd2 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -23,7 +23,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/intel/skylake/i2c.c b/src/soc/intel/skylake/i2c.c index 9fd9bf39e6..316c633c4d 100644 --- a/src/soc/intel/skylake/i2c.c +++ b/src/soc/intel/skylake/i2c.c @@ -15,7 +15,7 @@ */ #include -#include +#include #include #include diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c index 864cefe0b9..69459e7e03 100644 --- a/src/soc/intel/skylake/lockdown.c +++ b/src/soc/intel/skylake/lockdown.c @@ -14,7 +14,7 @@ */ #include -#include +#include #include #include #include From 91f2f03759a0b558be52a98037beeeb2812c93ed Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 28 Sep 2019 13:47:58 +0300 Subject: [PATCH 21/75] intel/fsp_baytrail: Drop unnecessary lookup for PCI 0:0.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It is safe to assume this to be copy-paste from eg. i945 where registers of said PCI device were read. Change-Id: I387b7fd6caf317543a6438f973d9e1d96e418de3 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35668 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/intel/fsp_baytrail/northcluster.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c index 416746d79e..797039a27e 100644 --- a/src/soc/intel/fsp_baytrail/northcluster.c +++ b/src/soc/intel/fsp_baytrail/northcluster.c @@ -87,15 +87,10 @@ uint32_t nc_read_top_of_low_memory(void) static int get_pcie_bar(u32 *base) { - struct device *dev; u32 pciexbar_reg; *base = 0; - dev = pcidev_on_root(0, 0); - if (!dev) - return 0; - pciexbar_reg = iosf_bunit_read(BUNIT_MMCONF_REG); if (!(pciexbar_reg & (1 << 0))) From 9d5af5b0c2dd2c9455f8094f10e649b92094c4a3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 27 Sep 2019 12:01:15 +0300 Subject: [PATCH 22/75] device/pci_ops: Add ENV_PCI_SIMPLE_DEVICE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Source files including this may have locally defined __SIMPLE_DEVICE__ so this cannot be placed in . Change-Id: If700dd10fd5e082568cd6866bfd802fc2e021806 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35652 Reviewed-by: Furquan Shaikh Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/include/device/pci_ops.h | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index 5371e07419..9d64f037f6 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -39,7 +39,13 @@ static __always_inline pci_devfn_t pcidev_assert(const struct device *dev) } #endif -#ifdef __SIMPLE_DEVICE__ +#if defined(__SIMPLE_DEVICE__) +#define ENV_PCI_SIMPLE_DEVICE 1 +#else +#define ENV_PCI_SIMPLE_DEVICE 0 +#endif + +#if ENV_PCI_SIMPLE_DEVICE /* Avoid name collisions as different stages have different signature * for these functions. The _s_ stands for simple, fundamental IO or @@ -91,7 +97,7 @@ void pci_write_config32(const struct device *dev, u16 reg, u32 val) #endif -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static __always_inline void pci_or_config8(pci_devfn_t dev, u16 reg, u8 ormask) #else @@ -103,7 +109,7 @@ void pci_or_config8(const struct device *dev, u16 reg, u8 ormask) pci_write_config8(dev, reg, value | ormask); } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static __always_inline void pci_or_config16(pci_devfn_t dev, u16 reg, u16 ormask) #else @@ -115,7 +121,7 @@ void pci_or_config16(const struct device *dev, u16 reg, u16 ormask) pci_write_config16(dev, reg, value | ormask); } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static __always_inline void pci_or_config32(pci_devfn_t dev, u16 reg, u32 ormask) #else @@ -127,7 +133,7 @@ void pci_or_config32(const struct device *dev, u16 reg, u32 ormask) pci_write_config32(dev, reg, value | ormask); } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static __always_inline void pci_update_config8(pci_devfn_t dev, u16 reg, u8 mask, u8 or) #else @@ -143,7 +149,7 @@ void pci_update_config8(const struct device *dev, u16 reg, u8 mask, u8 or) pci_write_config8(dev, reg, reg8); } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static __always_inline void pci_update_config16(pci_devfn_t dev, u16 reg, u16 mask, u16 or) #else @@ -159,7 +165,7 @@ void pci_update_config16(const struct device *dev, u16 reg, u16 mask, u16 or) pci_write_config16(dev, reg, reg16); } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static __always_inline void pci_update_config32(pci_devfn_t dev, u16 reg, u32 mask, u32 or) #else From 0f639750a10cad0b6bd6d44626f71e457ea62349 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 27 Sep 2019 12:01:15 +0300 Subject: [PATCH 23/75] device/pnp_ops: Add ENV_PNP_SIMPLE_DEVICE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Source files including this may have locally defined __SIMPLE_DEVICE__ so this cannot be placed in . Change-Id: I2336111b871203f1628c3c47027d4052c37899dc Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35653 Reviewed-by: Furquan Shaikh Reviewed-by: Aaron Durbin Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/include/device/pnp.h | 5 +++-- src/include/device/pnp_ops.h | 4 ++-- src/include/device/pnp_type.h | 6 ++++++ 3 files changed, 11 insertions(+), 4 deletions(-) diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index ee92a32d08..69a0667445 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -4,9 +4,10 @@ #include #include #include +#include #include -#ifndef __SIMPLE_DEVICE__ +#if !ENV_PNP_SIMPLE_DEVICE /* Primitive PNP resource manipulation */ void pnp_write_config(struct device *dev, u8 reg, u8 value); @@ -18,7 +19,7 @@ void pnp_set_iobase(struct device *dev, u8 index, u16 iobase); void pnp_set_irq(struct device *dev, u8 index, u8 irq); void pnp_set_drq(struct device *dev, u8 index, u8 drq); -#endif /* __SIMPLE_DEVICE */ +#endif /* PNP device operations */ void pnp_read_resources(struct device *dev); diff --git a/src/include/device/pnp_ops.h b/src/include/device/pnp_ops.h index 9086fdf67c..61d05a86ad 100644 --- a/src/include/device/pnp_ops.h +++ b/src/include/device/pnp_ops.h @@ -19,7 +19,7 @@ #include #include -#ifdef __SIMPLE_DEVICE__ +#if ENV_PNP_SIMPLE_DEVICE static __always_inline void pnp_write_config( pnp_devfn_t dev, uint8_t reg, uint8_t value) @@ -82,6 +82,6 @@ void pnp_set_drq(pnp_devfn_t dev, unsigned int index, unsigned int drq) pnp_write_config(dev, index, drq & 0xff); } -#endif /* __SIMPLE_DEVICE__ */ +#endif #endif diff --git a/src/include/device/pnp_type.h b/src/include/device/pnp_type.h index db26f2f259..dc2d27c84d 100644 --- a/src/include/device/pnp_type.h +++ b/src/include/device/pnp_type.h @@ -20,4 +20,10 @@ typedef u32 pnp_devfn_t; #define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC)) +#if defined(__SIMPLE_DEVICE__) +#define ENV_PNP_SIMPLE_DEVICE 1 +#else +#define ENV_PNP_SIMPLE_DEVICE 0 +#endif + #endif /* __DEVICE_PNP_TYPE_H__ */ From 23d4d9f36882dbca1fea9b4430210eef73a0eb71 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 27 Sep 2019 15:32:22 +0300 Subject: [PATCH 24/75] amdfam_10h-15h: Use ENV_PCI_SIMPLE_DEVICE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I265d50af1099ae4449b5adebcf21e2043aa02c7a Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35654 Reviewed-by: Furquan Shaikh Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/cpu/amd/family_10h-family_15h/ram_calc.c | 2 +- src/cpu/amd/quadcore/quadcore_id.c | 4 +-- src/northbridge/amd/amdfam10/amdfam10.h | 2 -- src/northbridge/amd/amdfam10/amdfam10_util.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 14 +++++----- src/southbridge/amd/sr5650/cmn.h | 28 +++++++++---------- 6 files changed, 25 insertions(+), 27 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/ram_calc.c b/src/cpu/amd/family_10h-family_15h/ram_calc.c index 5b97232cb4..3946b67b2d 100644 --- a/src/cpu/amd/family_10h-family_15h/ram_calc.c +++ b/src/cpu/amd/family_10h-family_15h/ram_calc.c @@ -65,7 +65,7 @@ uint64_t get_cc6_memory_size() if (is_fam15h()) { enable_cc6 = 0; -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE if (pci_read_config32(PCI_DEV(0, 0x18, 2), 0x118) & (0x1 << 18)) enable_cc6 = 1; #else diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c index 2c4d60dd05..7ec1bdb4f6 100644 --- a/src/cpu/amd/quadcore/quadcore_id.c +++ b/src/cpu/amd/quadcore/quadcore_id.c @@ -42,7 +42,7 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54) uint32_t family; uint32_t model; -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE f3xe8 = pci_read_config32(NODE_PCI(0, 3), 0xe8); #else f3xe8 = pci_read_config32(get_node_pci(0, 3), 0xe8); @@ -109,7 +109,7 @@ struct node_core_id get_node_core_id(u32 nb_cfg_54) uint32_t f5x84; uint8_t core_count; -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE f5x84 = pci_read_config32(NODE_PCI(0, 5), 0x84); #else f5x84 = pci_read_config32(get_node_pci(0, 5), 0x84); diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index 96938b2c63..ad8d01365d 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -1017,11 +1017,9 @@ BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, const u8 **List); struct acpi_rsdp; -#ifndef __SIMPLE_DEVICE__ unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long start, struct acpi_rsdp *rsdp); void northbridge_acpi_write_vars(struct device *device); -#endif #endif /* AMDFAM10_H */ diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.c b/src/northbridge/amd/amdfam10/amdfam10_util.c index 3e8c2fbeac..23e92323a8 100644 --- a/src/northbridge/amd/amdfam10/amdfam10_util.c +++ b/src/northbridge/amd/amdfam10/amdfam10_util.c @@ -21,7 +21,7 @@ #include "raminit.h" #include -#ifndef __SIMPLE_DEVICE__ +#if !ENV_PCI_SIMPLE_DEVICE u32 Get_NB32(u32 dev, u32 reg) { return pci_read_config32(pcidev_path_on_root(PCI_DEV2DEVFN(dev)), reg); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index 1fdbc169e4..52032e9362 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -69,7 +69,7 @@ ssize_t get_s3nv_file_offset(void) return s3nv_region.region.offset; } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static uint32_t read_config32_dct(pci_devfn_t dev, uint8_t node, uint8_t dct, uint32_t reg) #else @@ -79,7 +79,7 @@ static uint32_t read_config32_dct(struct device *dev, uint8_t node, uint8_t dct, { if (is_fam15h()) { uint32_t dword; -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); #else struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1); @@ -98,7 +98,7 @@ static uint32_t read_config32_dct(struct device *dev, uint8_t node, uint8_t dct, return pci_read_config32(dev, reg); } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static void write_config32_dct(pci_devfn_t dev, uint8_t node, uint8_t dct, uint32_t reg, uint32_t value) #else @@ -108,7 +108,7 @@ static void write_config32_dct(struct device *dev, uint8_t node, uint8_t dct, { if (is_fam15h()) { uint32_t dword; -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); #else struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1); @@ -127,7 +127,7 @@ static void write_config32_dct(struct device *dev, uint8_t node, uint8_t dct, pci_write_config32(dev, reg, value); } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static uint32_t read_amd_dct_index_register(pci_devfn_t dev, uint32_t index_ctl_reg, uint32_t index) #else @@ -147,7 +147,7 @@ static uint32_t read_amd_dct_index_register(struct device *dev, return dword; } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static uint32_t read_amd_dct_index_register_dct(pci_devfn_t dev, uint8_t node, uint8_t dct, uint32_t index_ctl_reg, uint32_t index) #else @@ -158,7 +158,7 @@ static uint32_t read_amd_dct_index_register_dct(struct device *dev, { if (is_fam15h()) { uint32_t dword; -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE pci_devfn_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); #else struct device *dev_fn1 = pcidev_on_root(0x18 + node, 1); diff --git a/src/southbridge/amd/sr5650/cmn.h b/src/southbridge/amd/sr5650/cmn.h index d70e7a9c9b..9588105c5a 100644 --- a/src/southbridge/amd/sr5650/cmn.h +++ b/src/southbridge/amd/sr5650/cmn.h @@ -34,7 +34,7 @@ #define AB_INDX 0xCD8 #define AB_DATA (AB_INDX+4) -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static inline u32 nb_read_index(pci_devfn_t dev, u32 index_reg, u32 index) #else static inline u32 nb_read_index(struct device *dev, u32 index_reg, u32 index) @@ -44,7 +44,7 @@ static inline u32 nb_read_index(struct device *dev, u32 index_reg, u32 index) return pci_read_config32(dev, index_reg + 0x4); } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static inline void nb_write_index(pci_devfn_t dev, u32 index_reg, u32 index, u32 data) #else @@ -56,7 +56,7 @@ static inline void nb_write_index(struct device *dev, u32 index_reg, u32 index, pci_write_config32(dev, index_reg + 0x4, data); } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static inline u32 nbmisc_read_index(pci_devfn_t nb_dev, u32 index) #else static inline u32 nbmisc_read_index(struct device *nb_dev, u32 index) @@ -65,7 +65,7 @@ static inline u32 nbmisc_read_index(struct device *nb_dev, u32 index) return nb_read_index((nb_dev), NBMISC_INDEX, (index)); } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static inline void nbmisc_write_index(pci_devfn_t nb_dev, u32 index, u32 data) #else static inline void nbmisc_write_index(struct device *nb_dev, u32 index, @@ -75,7 +75,7 @@ static inline void nbmisc_write_index(struct device *nb_dev, u32 index, nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data)); } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static inline void set_nbmisc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, u32 val) #else @@ -92,7 +92,7 @@ static inline void set_nbmisc_enable_bits(struct device *nb_dev, u32 reg_pos, } } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static inline u32 htiu_read_index(pci_devfn_t nb_dev, u32 index) #else static inline u32 htiu_read_index(struct device *nb_dev, u32 index) @@ -101,7 +101,7 @@ static inline u32 htiu_read_index(struct device *nb_dev, u32 index) return nb_read_index((nb_dev), NBHTIU_INDEX, (index)); } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static inline void htiu_write_index(pci_devfn_t nb_dev, u32 index, u32 data) #else static inline void htiu_write_index(struct device *nb_dev, u32 index, u32 data) @@ -110,7 +110,7 @@ static inline void htiu_write_index(struct device *nb_dev, u32 index, u32 data) nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data)); } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static inline u32 nbmc_read_index(pci_devfn_t nb_dev, u32 index) #else static inline u32 nbmc_read_index(struct device *nb_dev, u32 index) @@ -119,7 +119,7 @@ static inline u32 nbmc_read_index(struct device *nb_dev, u32 index) return nb_read_index((nb_dev), NBMC_INDEX, (index)); } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static inline void nbmc_write_index(pci_devfn_t nb_dev, u32 index, u32 data) #else static inline void nbmc_write_index(struct device *nb_dev, u32 index, u32 data) @@ -128,7 +128,7 @@ static inline void nbmc_write_index(struct device *nb_dev, u32 index, u32 data) nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data)); } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static inline void set_htiu_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, u32 val) #else @@ -145,7 +145,7 @@ static inline void set_htiu_enable_bits(struct device *nb_dev, u32 reg_pos, } } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static inline void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, u32 val) #else @@ -162,7 +162,7 @@ static inline void set_nbcfg_enable_bits(struct device *nb_dev, u32 reg_pos, } } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static inline void set_nbcfg_enable_bits_8(pci_devfn_t nb_dev, u32 reg_pos, u8 mask, u8 val) #else @@ -179,7 +179,7 @@ static inline void set_nbcfg_enable_bits_8(struct device *nb_dev, u32 reg_pos, } } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static inline void set_nbmc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos, u32 mask, u32 val) #else @@ -196,7 +196,7 @@ static inline void set_nbmc_enable_bits(struct device *nb_dev, u32 reg_pos, } } -#ifdef __SIMPLE_DEVICE__ +#if ENV_PCI_SIMPLE_DEVICE static inline void set_pcie_enable_bits(pci_devfn_t dev, u32 reg_pos, u32 mask, u32 val) #else From b09d44ef2d6faf9c0f7762b8385b894224d5929a Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Sat, 28 Sep 2019 08:25:35 +0530 Subject: [PATCH 25/75] mb/google/drallion: De-assert WWAN reset signal BUG=b:141734594 Change-Id: I419f7d11dffebe6c44eefa05750834d07d19857b Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/35665 Tested-by: build bot (Jenkins) Reviewed-by: Bora Guvendik Reviewed-by: EricR Lai --- src/mainboard/google/drallion/variants/drallion/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index 5fba04b0b2..c7b005370c 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -131,7 +131,7 @@ static const struct pad_config gpio_table[] = { EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ /* DMIC_CLK0 */ PAD_NC(GPP_D19, NONE), /* DMIC_DATA0 */ PAD_NC(GPP_D20, NONE), -/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */ +/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 1, DEEP), /* WWAN_BB_RST# */ /* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* WWAN_GPIO_PERST# */ /* I2S_MCLK */ PAD_CFG_GPI_SCI_LOW(GPP_D23, NONE, DEEP, EDGE_SINGLE), /* WWAN_GPIO_WAKE# */ From 6aeed16422df88c697d034ed4688ab44e41fa070 Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Fri, 27 Sep 2019 22:26:49 -0700 Subject: [PATCH 26/75] mb/google/drallion: Adjust GPD3 pin termination Internal pull up need to be enabled for GPD3 as power button pin for PCH according cometlake pch EDS vol1 section 17-1. Without that pin will stay floating and hook up XDP can cause system shutdown as power buttone event will trigger. BUG=N/A TEST=Hook up XDP on drallion platform, able to boot up into OS and stay at power up state. Change-Id: Idd1befeb14a251b7c0542ca1f99049d07b28fb98 Signed-off-by: Bora Guvendik Reviewed-on: https://review.coreboot.org/c/coreboot/+/35666 Tested-by: build bot (Jenkins) Reviewed-by: Aamir Bohra Reviewed-by: Subrata Banik Reviewed-by: Lijian Zhao --- src/mainboard/google/drallion/variants/drallion/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index c7b005370c..154fc5a7f2 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -214,7 +214,6 @@ static const struct pad_config gpio_table[] = { /* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* BATLOW# */ /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* AC_PRESENT */ /* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* LAN_WAKE# */ -/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), /* SIO_PWRBTN# */ /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SIO_SLP_S3# */ /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SIO_SLP_S4# */ /* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* SIO_SLP_A# */ @@ -250,6 +249,7 @@ static const struct pad_config early_gpio_table[] = { /* EMMC_DATA3 */ PAD_CFG_GPI(GPP_F15, NONE, DEEP), /* MEM_CONFIGO_1P8 */ /* EMMC_DATA4 */ PAD_CFG_GPI(GPP_F16, NONE, DEEP), /* MEM_CONFIGO_1P8 */ /* I2C2_SCL */ PAD_CFG_GPI(GPP_H5, NONE, PLTRST), /* 360_SENSOR_DET# */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* SIO_PWRBTN# */ }; const struct pad_config *variant_gpio_table(size_t *num) From f553ae4bf39891b0758f5609d707289d26e75d5e Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Wed, 25 Sep 2019 13:48:31 +0200 Subject: [PATCH 27/75] fsp_broadwell_de: Enable early write access to the SPI flash If VBOOT is used on a mainboard based on fsp_broadwell_de then VBOOT needs to be able to write to its NV data which may be stored on the SPI flash. Enable write access to the SPI flash on SoC level. If the mainboard does not use VBOOT the linker will drop the extra code. The benefit is that this code is at least compiled and therefore build tested with fsp_broadwell_de. Change-Id: I90a2d30f5749c75df2b286dce6779f10dde62632 Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/c/coreboot/+/35598 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks Reviewed-by: Arthur Heymans --- src/soc/intel/fsp_broadwell_de/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index 9c91d7c5fc..94eff07bab 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -29,6 +29,8 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_IMC + select BOOT_DEVICE_SUPPORTS_WRITES + select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY config VBOOT select VBOOT_STARTS_IN_ROMSTAGE From 3356305ca6cd72b6b92dd4e8ebbba2b828574b8e Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Wed, 25 Sep 2019 08:54:44 +0200 Subject: [PATCH 28/75] mb/siemens/mc_bdx1: Enable VBOOT Enable VBOOT in Kconfig and provide a flashmap that includes all the needed sections for VBOOT support. Change-Id: Iee12a5d1781c869b20bc14a52ecbf23474caa3fd Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/c/coreboot/+/35594 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/siemens/mc_bdx1/Kconfig | 15 +++++++++++++- src/mainboard/siemens/mc_bdx1/mc_bdx1.fmd | 25 +++++++++++++++++++++++ 2 files changed, 39 insertions(+), 1 deletion(-) create mode 100644 src/mainboard/siemens/mc_bdx1/mc_bdx1.fmd diff --git a/src/mainboard/siemens/mc_bdx1/Kconfig b/src/mainboard/siemens/mc_bdx1/Kconfig index 6feb1cf563..006758219a 100644 --- a/src/mainboard/siemens/mc_bdx1/Kconfig +++ b/src/mainboard/siemens/mc_bdx1/Kconfig @@ -16,6 +16,19 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_LPC_TPM +config VBOOT + select VBOOT_MEASURED_BOOT + select VBOOT_VBNV_FLASH + select VBOOT_NO_BOARD_SUPPORT + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/mc_bdx1.fmd" if VBOOT + config MAINBOARD_DIR string default "siemens/mc_bdx1" @@ -30,7 +43,7 @@ config IRQ_SLOT_COUNT config CBFS_SIZE hex - default 0x00D00000 + default 0x00D00000 if !VBOOT config VIRTUAL_ROM_SIZE hex diff --git a/src/mainboard/siemens/mc_bdx1/mc_bdx1.fmd b/src/mainboard/siemens/mc_bdx1/mc_bdx1.fmd new file mode 100644 index 0000000000..cb7ef391e1 --- /dev/null +++ b/src/mainboard/siemens/mc_bdx1/mc_bdx1.fmd @@ -0,0 +1,25 @@ +FLASH@0xff000000 0x1000000 { + SI_ALL@0x0 0x300000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x2ff000 + } + SI_BIOS@0x300000 0xd00000 { + RW_MRC_CACHE 0x10000 + RW_SHARED 0x4000 { + SHARED_DATA 0x2000 + VBLOCK_DEV 0x2000 + } + RW_VPD 0x2000 + RW_NVRAM 0x2000 + WP_RO 0xce8000 { + RO_VPD 0x4000 + RO_SECTION 0xce4000 { + FMAP 0x800 + RO_FRID 0x40 + RO_FRID_PAD 0x7c0 + GBB 0xef000 + COREBOOT(CBFS) + } + } + } +} From 01b60633a85495bf9041f61176fa26198a4eca54 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 25 Sep 2019 15:22:42 +0300 Subject: [PATCH 29/75] soc/intel/fsp_baytrail: Drop some __BOOTBLOCK__ guards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change in ssus_disable_internal_pull() is for romcc compatibility. Change-Id: Ib72a669a3b5cd90e74d917f74f35453a85941658 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35600 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- src/soc/intel/fsp_baytrail/include/soc/gpio.h | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/include/soc/gpio.h b/src/soc/intel/fsp_baytrail/include/soc/gpio.h index 68c62350ce..137ec95f14 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/gpio.h +++ b/src/soc/intel/fsp_baytrail/include/soc/gpio.h @@ -313,8 +313,6 @@ #define GPSSUS_GPIO_F1_RANGE_START 11 #define GPSSUS_GPIO_F1_RANGE_END 21 -#ifndef __BOOTBLOCK__ - struct soc_gpio_map { u32 pad_conf0; u32 pad_conf1; @@ -360,8 +358,6 @@ void write_ssus_gpio(uint8_t gpio_num, uint8_t val); void configure_ssus_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val); void configure_score_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val); -#endif /* #ifndef __BOOTBLOCK__ */ - /* Functions / defines for changing GPIOs in romstage */ /* SCORE Pad definitions. */ #define UART_RXD_PAD 82 @@ -401,7 +397,6 @@ static inline void ssus_select_func(int pad, int func) write32(pconf0_addr, reg); } -#ifndef __BOOTBLOCK__ /* These functions require that the input pad be configured as an input GPIO */ static inline int score_get_gpio(int pad) @@ -436,10 +431,12 @@ static inline void ssus_set_gpio(int pad, int val) static inline void ssus_disable_internal_pull(int pad) { - const uint32_t pull_mask = ~(0xf << 7); - write32(ssus_pconf0(pad), read32(ssus_pconf0(pad)) & pull_mask); + uint32_t reg; + uint32_t *pconf0_addr = ssus_pconf0(pad); + + reg = read32(pconf0_addr); + reg &= ~(0xf << 7); + write32(pconf0_addr, reg); } -#endif /* #ifndef __BOOTBLOCK__ */ - #endif /* _BAYTRAIL_GPIO_H_ */ From 92bb8320d62449207b45f5a76a011f1eacfdbd4f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 24 Sep 2019 22:40:43 +0300 Subject: [PATCH 30/75] console: Declare empty printk() for __ROMCC__ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The typical do { } while (0) did not work, so provide empty stub function instead. Change-Id: Ieb0c33b082b4c4453d29d917f46561c0e672d09a Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35588 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/cpu/intel/microcode/microcode.c | 18 ++---------------- src/include/console/console.h | 8 +++++++- 2 files changed, 9 insertions(+), 17 deletions(-) diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index feb73c8b42..80470bf236 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -17,11 +17,11 @@ #include #if !defined(__ROMCC__) #include -#include #else #include #endif #include +#include #include #include #include @@ -84,9 +84,7 @@ void intel_microcode_load_unlocked(const void *microcode_patch) /* No use loading the same revision. */ if (current_rev == m->rev) { -#if !defined(__ROMCC__) printk(BIOS_INFO, "microcode: Update skipped, already up-to-date\n"); -#endif return; } @@ -104,18 +102,14 @@ void intel_microcode_load_unlocked(const void *microcode_patch) current_rev = read_microcode_rev(); if (current_rev == m->rev) { -#if !defined(__ROMCC__) printk(BIOS_INFO, "microcode: updated to revision " "0x%x date=%04x-%02x-%02x\n", read_microcode_rev(), m->date & 0xffff, (m->date >> 24) & 0xff, (m->date >> 16) & 0xff); -#endif return; } -#if !defined(__ROMCC__) printk(BIOS_INFO, "microcode: Update failed\n"); -#endif } uint32_t get_current_microcode_rev(void) @@ -180,13 +174,9 @@ const void *intel_microcode_find(void) msr = rdmsr(IA32_PLATFORM_ID); pf = 1 << ((msr.hi >> 18) & 7); } -#if !defined(__ROMCC__) - /* If this code is compiled with ROMCC we're probably in - * the bootblock and don't have console output yet. - */ + printk(BIOS_DEBUG, "microcode: sig=0x%x pf=0x%x revision=0x%x\n", sig, pf, rev); -#endif while (microcode_len >= sizeof(*ucode_updates)) { /* Newer microcode updates include a size field, whereas older @@ -194,17 +184,13 @@ const void *intel_microcode_find(void) if (ucode_updates->total_size) { update_size = ucode_updates->total_size; } else { - #if !defined(__ROMCC__) printk(BIOS_SPEW, "Microcode size field is 0\n"); - #endif update_size = 2048; } /* Checkpoint 1: The microcode update falls within CBFS */ if (update_size > microcode_len) { -#if !defined(__ROMCC__) printk(BIOS_WARNING, "Microcode header corrupted!\n"); -#endif break; } diff --git a/src/include/console/console.h b/src/include/console/console.h index e5b753e8b6..1c2a276af0 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -19,7 +19,6 @@ #include #include #include -#include /* console.h is supposed to provide the log levels defined in here: */ #include @@ -29,6 +28,8 @@ #ifndef __ROMCC__ +#include + void post_code(u8 value); #if CONFIG(CMOS_POST_EXTRA) void post_log_extra(u32 value); @@ -93,6 +94,11 @@ int do_printk(int msg_level, const char *fmt, ...) int do_vprintk(int msg_level, const char *fmt, va_list args); +#else + +static inline void romcc_printk(void) { } +#define printk(...) romcc_printk() + #endif /* !__ROMCC__ */ #endif /* CONSOLE_CONSOLE_H_ */ From 1463a2a04d4ffcf7afbb7870502bf65d4ebcdca1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 29 Sep 2019 07:03:14 +0300 Subject: [PATCH 31/75] getac/p470: Drop unused PCI secondary bus reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I959cdc08d43fea28f8bbc649cd46bab5656d6ca8 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35674 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/getac/p470/romstage.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index ff4c99ed4d..a7c64bd98b 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -237,13 +237,6 @@ void mainboard_romstage_entry(void) enable_lapic(); -#if 0 - /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); -#endif - ich7_enable_lpc(); early_superio_config(); From e088721f715602df84503c960deb562064af5718 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 26 Sep 2019 22:33:51 +0300 Subject: [PATCH 32/75] device,drivers/: Drop some __SIMPLE_DEVICE__ use MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The simple PCI config accessors are always available under names pci_s_[read|write]_configX. Change-Id: Ic1b67695b7f72e4f1fa29e2d56698276b15024e1 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35669 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/commonlib/storage/pci_sdhci.c | 8 ++------ src/device/pci_ops.c | 2 -- src/drivers/uart/oxpcie_early.c | 12 +++++------- 3 files changed, 7 insertions(+), 15 deletions(-) diff --git a/src/commonlib/storage/pci_sdhci.c b/src/commonlib/storage/pci_sdhci.c index de248b7720..abc093f777 100644 --- a/src/commonlib/storage/pci_sdhci.c +++ b/src/commonlib/storage/pci_sdhci.c @@ -12,10 +12,6 @@ * GNU General Public License for more details. */ -#if ENV_RAMSTAGE -#define __SIMPLE_DEVICE__ 1 -#endif - #include #include #include @@ -54,11 +50,11 @@ struct sd_mmc_ctrlr *new_mem_sdhci_controller(void *ioaddr) return car_get_var_ptr(&sdhci_ctrlr.sd_mmc_ctrlr); } -struct sd_mmc_ctrlr *new_pci_sdhci_controller(uint32_t dev) +struct sd_mmc_ctrlr *new_pci_sdhci_controller(pci_devfn_t dev) { uint32_t addr; - addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0); + addr = pci_s_read_config32(dev, PCI_BASE_ADDRESS_0); if (addr == ((uint32_t)~0)) { sdhc_error("Error: PCI SDHCI not found\n"); return NULL; diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index 6f42978e82..431160e5cb 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -11,8 +11,6 @@ * GNU General Public License for more details. */ -#define __SIMPLE_DEVICE__ - #include #include #include diff --git a/src/drivers/uart/oxpcie_early.c b/src/drivers/uart/oxpcie_early.c index b99040116a..eb6f8804a0 100644 --- a/src/drivers/uart/oxpcie_early.c +++ b/src/drivers/uart/oxpcie_early.c @@ -13,8 +13,6 @@ * GNU General Public License for more details. */ -#define __SIMPLE_DEVICE__ - #include #include #include @@ -31,7 +29,7 @@ int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base) { pci_devfn_t device = PCI_DEV(bus, dev, 0); - u32 id = pci_read_config32(device, PCI_VENDOR_ID); + u32 id = pci_s_read_config32(device, PCI_VENDOR_ID); switch (id) { case 0xc1181415: /* e.g. Startech PEX1S1PMINI function 0 */ /* On this device function 0 is the parallel port, and @@ -39,7 +37,7 @@ int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base) * the UART. */ device = PCI_DEV(bus, dev, 3); - id = pci_read_config32(device, PCI_VENDOR_ID); + id = pci_s_read_config32(device, PCI_VENDOR_ID); if (id != 0xc11b1415) return -1; break; @@ -56,12 +54,12 @@ int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base) return -1; /* Setup base address on device */ - pci_write_config32(device, PCI_BASE_ADDRESS_0, mmio_base); + pci_s_write_config32(device, PCI_BASE_ADDRESS_0, mmio_base); /* Enable memory on device */ - u16 reg16 = pci_read_config16(device, PCI_COMMAND); + u16 reg16 = pci_s_read_config16(device, PCI_COMMAND); reg16 |= PCI_COMMAND_MEMORY; - pci_write_config16(device, PCI_COMMAND, reg16); + pci_s_write_config16(device, PCI_COMMAND, reg16); car_set_var(oxpcie_present, 1); return 0; From 544bc2693a515b5fa72c767d637a9f99f998a572 Mon Sep 17 00:00:00 2001 From: Hung-Te Lin Date: Sat, 28 Sep 2019 10:23:28 +0800 Subject: [PATCH 33/75] util/chromeos: revise description for more utility scripts in future The description.md and README.md was explicitly made for downloading or extracting some resources, but we need to add more Chrome OS related scripts soon; so the description should be revised. Also changed README.md for better markdown style, for example - Use #, ## to replace the old '-' headers - Use code format for file names - Use code block for example of shell execution Change-Id: Icc3677fa318b03f4aee1b0f5fb13b2095f2afe64 Signed-off-by: Hung-Te Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/35664 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/chromeos/README.md | 25 +++++++++++++------------ util/chromeos/description.md | 6 +++--- 2 files changed, 16 insertions(+), 15 deletions(-) diff --git a/util/chromeos/README.md b/util/chromeos/README.md index 3c3d721a3c..7a3897d8a0 100644 --- a/util/chromeos/README.md +++ b/util/chromeos/README.md @@ -1,27 +1,28 @@ -Chrome OS binary extraction -=========================== +# Chrome OS Scripts -These scripts can be used to extract System Agent reference code -and other blobs (e.g. mrc.bin, refcode, VGA option roms) from a -Chrome OS recovery image. +These scripts can be used to access or generate Chrome OS resources, for example +to extract System Agent reference code and other blobs (e.g. `mrc.bin`, refcode, +VGA option roms) from a Chrome OS recovery image. -crosfirmware.sh ---------------- +## crosfirmware.sh -crosfirmware.sh downloads a Chrome OS recovery image from the recovery +`crosfirmware.sh` downloads a Chrome OS recovery image from the recovery image server, unpacks it, extracts the firmware update shell archive, extracts the firmware images from the shell archive. To download all Chrome OS firmware images, run +``` $ ./crosfirmware.sh +``` To download, e.g. the Panther firmware image, run +``` $ ./crosfirmware.sh panther +``` -extract_blobs.sh ----------------- +## extract_blobs.sh -extract_blobs.sh extracts the blobs from a Chrome OS firmware image. +`extract_blobs.sh` extracts the blobs from a Chrome OS firmware image. Right now it will produce the ME firmware blob, IFD, VGA option rom, -and mrc.bin +and `mrc.bin`. diff --git a/util/chromeos/description.md b/util/chromeos/description.md index d2da57770e..840e58927e 100644 --- a/util/chromeos/description.md +++ b/util/chromeos/description.md @@ -1,3 +1,3 @@ -These scripts can be used to extract System Agent reference code and -other blobs (e.g. mrc.bin, refcode, VGA option roms) from a Chrome OS -recovery image. `C` +These scripts can be used to access Chrome OS resources, for example to extract +System Agent reference code and other blobs (e.g. mrc.bin, refcode, VGA option +roms) from a Chrome OS recovery image. `C` From 117453e89010069561f15117ff8279dca1f635e4 Mon Sep 17 00:00:00 2001 From: Hung-Te Lin Date: Fri, 27 Sep 2019 12:23:20 +0800 Subject: [PATCH 34/75] vboot: create board-specific test-only GBB HWID if not set The HWID in vboot GBB is an identifier for machine model. On Chrome OS, that should be provisioned in manufacturing process (by collecting real hardware information), and will be checked in system startup. For bring up developers, they usually prefer to generate a test-only string for HWID. However that format was not well documented and cause problems. Further more, most Chromebooks are using HWID v3+ today while the test-only HWID is usually v2. Non-Chrome OS developers may also prefer their own format. To simplify development process, the GBB_CONFIG now defaults to empty string, and will be replaced by a board-specific test-only v2 HWID automatically. Developers can still override that in mainboard Kconfig if they prefer v3 or other arbitrary format. BUG=b:140067412 TEST=Built 'kukui' successfully. Removed kukui GBB config and built again, still seeing correct test HWID. Change-Id: I0cda17a374641589291ec8dfb1d66c553f7cbf35 Signed-off-by: Hung-Te Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/35634 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/security/vboot/Kconfig | 7 ++++++- src/security/vboot/Makefile.inc | 5 +++++ util/chromeos/README.md | 16 ++++++++++++++++ util/chromeos/gen_test_hwid.sh | 31 +++++++++++++++++++++++++++++++ 4 files changed, 58 insertions(+), 1 deletion(-) create mode 100755 util/chromeos/gen_test_hwid.sh diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index 1e372d86ba..d6d74cac73 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -228,7 +228,12 @@ menu "GBB configuration" config GBB_HWID string "Hardware ID" - default "NOCONF HWID" + default "" + help + A hardware identifier for device. On Chrome OS this is used for auto + update and recovery, and will be generated when manufacturing by the + factory software, in a strictly defined format. + Leave empty to get a test-only Chrome OS HWID v2 string generated. config GBB_BMPFV_FILE string "Path to bmpfv image" diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 3078e30e21..abb8863c02 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -239,6 +239,11 @@ $(obj)/gbb.stub: $(obj)/coreboot.rom $(FUTILITY) mv $@.tmp $@ endif +# Generate a test-only HWID +ifeq ($(CONFIG_GBB_HWID),) +CONFIG_GBB_HWID := $$($(top)/util/chromeos/gen_test_hwid.sh "$(CONFIG_MAINBOARD_PART_NUMBER)") +endif + $(obj)/gbb.region: $(obj)/gbb.stub @printf " SETUP GBB\n" cp $< $@.tmp diff --git a/util/chromeos/README.md b/util/chromeos/README.md index 7a3897d8a0..0b9a7d74d8 100644 --- a/util/chromeos/README.md +++ b/util/chromeos/README.md @@ -26,3 +26,19 @@ $ ./crosfirmware.sh panther Right now it will produce the ME firmware blob, IFD, VGA option rom, and `mrc.bin`. + +## gen_test_hwid.sh + +`gen_test_hwid.sh` generates a test-only identifier in Chrome OS HWID v2 +compatible format. + +Usage: +``` +$ ./gen_test_hwid.sh BOARD_NAME +``` + +Example: +``` +$ ./gen_test_hwid.sh Kukui +KUKUI TEST 9847 +``` diff --git a/util/chromeos/gen_test_hwid.sh b/util/chromeos/gen_test_hwid.sh new file mode 100755 index 0000000000..849ff6a8c0 --- /dev/null +++ b/util/chromeos/gen_test_hwid.sh @@ -0,0 +1,31 @@ +#!/bin/sh +# +# This file is part of the coreboot project. +# +# Copyright 2019 Google Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +main() { + if [ "$#" != 1 ]; then + echo "Usage: $0 MAINBOARD_PARTNUMBER" >&2 + exit 1 + fi + + # Generate a test-only Chrome OS HWID v2 string + local board="$1" + local prefix="$(echo "${board}" | tr a-z A-Z) TEST" + # gzip has second-to-last 4 bytes in CRC32. + local crc32="$(printf "${prefix}" | gzip -1 | tail -c 8 | head -c 4 | \ + hexdump -e '1/4 "%04u" ""' | tail -c 4)" + + echo "${prefix}" "${crc32}" +} +main "$@" From 4b5d17ebb3431271b2783e53637c02bbdf5b3c38 Mon Sep 17 00:00:00 2001 From: Hung-Te Lin Date: Fri, 27 Sep 2019 12:34:25 +0800 Subject: [PATCH 35/75] mb: remove test-only HWIDs The CONFIG_GBB_HWID can be generated automatically now so we can remove the test-only HWIDs set in board config files. BUG=b:140067412 TEST=Built few boards (kukui, cheza, octopus) and checked HWID: futility gbb -g coreboot.rom Change-Id: I4070f09d29c5601dff1587fed8c60714eb2558b7 Signed-off-by: Hung-Te Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/35635 Reviewed-by: Paul Fagerburg Tested-by: build bot (Jenkins) --- src/mainboard/google/auron/Kconfig | 10 ---------- src/mainboard/google/beltino/Kconfig | 9 --------- src/mainboard/google/cheza/Kconfig | 5 ----- src/mainboard/google/cyan/Kconfig | 15 --------------- src/mainboard/google/daisy/Kconfig | 4 ---- src/mainboard/google/dragonegg/Kconfig | 5 ----- src/mainboard/google/drallion/Kconfig | 7 ------- src/mainboard/google/eve/Kconfig | 5 ----- src/mainboard/google/fizz/Kconfig | 6 ------ src/mainboard/google/foster/Kconfig | 5 ----- src/mainboard/google/gale/Kconfig | 5 ----- src/mainboard/google/glados/Kconfig | 11 ----------- src/mainboard/google/gru/Kconfig | 10 ---------- src/mainboard/google/hatch/Kconfig | 10 ---------- src/mainboard/google/jecht/Kconfig | 8 -------- src/mainboard/google/kahlee/Kconfig | 9 --------- src/mainboard/google/kukui/Kconfig | 9 --------- src/mainboard/google/link/Kconfig | 5 ----- src/mainboard/google/mistral/Kconfig | 5 ----- src/mainboard/google/nyan/Kconfig | 4 ---- src/mainboard/google/nyan_big/Kconfig | 4 ---- src/mainboard/google/nyan_blaze/Kconfig | 4 ---- src/mainboard/google/oak/Kconfig | 7 ------- src/mainboard/google/octopus/Kconfig | 14 -------------- src/mainboard/google/peach_pit/Kconfig | 4 ---- src/mainboard/google/poppy/Kconfig | 11 ----------- src/mainboard/google/rambi/Kconfig | 20 -------------------- src/mainboard/google/reef/Kconfig | 10 ---------- src/mainboard/google/sarien/Kconfig | 6 ------ src/mainboard/google/slippy/Kconfig | 8 -------- src/mainboard/google/smaug/Kconfig | 4 ---- src/mainboard/google/storm/Kconfig | 4 ---- src/mainboard/google/urara/Kconfig | 5 ----- src/mainboard/google/veyron/Kconfig | 9 --------- src/mainboard/google/veyron_mickey/Kconfig | 5 ----- src/mainboard/google/veyron_rialto/Kconfig | 4 ---- src/mainboard/intel/glkrvp/Kconfig | 5 ----- src/mainboard/intel/kblrvp/Kconfig | 5 ----- src/mainboard/intel/kunimitsu/Kconfig | 5 ----- src/mainboard/intel/strago/Kconfig | 5 ----- 40 files changed, 286 deletions(-) diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index 69b086fefe..171418e4fa 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -45,16 +45,6 @@ config MAINBOARD_PART_NUMBER default "Lulu" if BOARD_GOOGLE_LULU default "Samus" if BOARD_GOOGLE_SAMUS -config GBB_HWID - string - depends on CHROMEOS - default "PAINE TEST A-A 8843" if BOARD_GOOGLE_AURON_PAINE - default "YUNA TEST A-A 3347" if BOARD_GOOGLE_AURON_YUNA - default "BUDDY TEST A-A 6186" if BOARD_GOOGLE_BUDDY - default "GANDOF TEST A-A 7705" if BOARD_GOOGLE_GANDOF - default "LULU TEST A-A 7705" if BOARD_GOOGLE_LULU - default "SAMUS TEST 8028" if BOARD_GOOGLE_SAMUS - config DEVICETREE string default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig index df5da9df20..9de141f539 100644 --- a/src/mainboard/google/beltino/Kconfig +++ b/src/mainboard/google/beltino/Kconfig @@ -42,15 +42,6 @@ config MAINBOARD_FAMILY string default "Google_Beltino" -config GBB_HWID - string - depends on CHROMEOS - default "X86 MCCLOUD TEST 5268" if BOARD_GOOGLE_MCCLOUD - default "X86 MONROE TEST 9962" if BOARD_GOOGLE_MONROE - default "X86 PANTHER TEST 6287" if BOARD_GOOGLE_PANTHER - default "X86 TRICKY TEST 4487" if BOARD_GOOGLE_TRICKY - default "X86 ZAKO TEST 8602" if BOARD_GOOGLE_ZAKO - config MAX_CPUS int default 8 diff --git a/src/mainboard/google/cheza/Kconfig b/src/mainboard/google/cheza/Kconfig index 59f78a8e56..ce69fe07e7 100644 --- a/src/mainboard/google/cheza/Kconfig +++ b/src/mainboard/google/cheza/Kconfig @@ -47,9 +47,4 @@ config MAINBOARD_PART_NUMBER string default "Cheza" if BOARD_GOOGLE_CHEZA -config GBB_HWID - string - depends on CHROMEOS - default "CHEZA TEST 1859" if BOARD_GOOGLE_CHEZA - endif # BOARD_GOOGLE_CHEZA_COMMON diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index bf0cd095f7..6f830b208e 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -93,21 +93,6 @@ config VGA_BIOS_ID The VGA_BIOS_ID for the C0 version of the video bios is hardcoded in soc/intel/braswell/Makefile.inc as 8086,22b1 -config GBB_HWID - string - depends on CHROMEOS - default "BANON TEST A-A 8050" if BOARD_GOOGLE_BANON - default "CELES TEST A-A 5441" if BOARD_GOOGLE_CELES - default "CYAN TEST A-A 1829" if BOARD_GOOGLE_CYAN - default "EDGAR TEST A-A 2507" if BOARD_GOOGLE_EDGAR - default "KEFKA TEST A-A 5397" if BOARD_GOOGLE_KEFKA - default "REKS TEST A-A 3004" if BOARD_GOOGLE_REKS - default "RELM TEST A-A 2323" if BOARD_GOOGLE_RELM - default "SETZER TEST A-A 8721" if BOARD_GOOGLE_SETZER - default "TERRA TEST A-A 1650" if BOARD_GOOGLE_TERRA - default "ULTIMA TEST A-A 6017" if BOARD_GOOGLE_ULTIMA - default "WIZPIG TEST A-A 0597" if BOARD_GOOGLE_WIZPIG - config CBFS_SIZE hex default 0x200000 diff --git a/src/mainboard/google/daisy/Kconfig b/src/mainboard/google/daisy/Kconfig index 55e0978ab7..ec09d5e199 100644 --- a/src/mainboard/google/daisy/Kconfig +++ b/src/mainboard/google/daisy/Kconfig @@ -58,8 +58,4 @@ config UART_FOR_CONSOLE int default 3 -config GBB_HWID - string - depends on CHROMEOS - default "DAISY TEST A-A 9382" endif # BOARD_GOOGLE_DAISY diff --git a/src/mainboard/google/dragonegg/Kconfig b/src/mainboard/google/dragonegg/Kconfig index 39228f45a9..dc6146c18b 100644 --- a/src/mainboard/google/dragonegg/Kconfig +++ b/src/mainboard/google/dragonegg/Kconfig @@ -38,11 +38,6 @@ config DRIVER_TPM_SPI_BUS depends on DRAGONEGG_USE_SPI_TPM default 0x1 -config GBB_HWID - string - depends on CHROMEOS - default "DRAGONEGG TEST 1394" - config MAINBOARD_DIR string default "google/dragonegg" diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index 97d0b51a8d..35f7150836 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -58,13 +58,6 @@ config POWER_OFF_ON_CR50_UPDATE bool default n -config GBB_HWID - string - depends on CHROMEOS - default "ARCADACML TEST 2699" if BOARD_GOOGLE_ARCADA_CML - default "SARIENCML TEST 3111" if BOARD_GOOGLE_SARIEN_CML - default "DRALLION TEST 4932" if BOARD_GOOGLE_DRALLION - config MAINBOARD_DIR string default "google/drallion" diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig index 022493c35f..e646f23d26 100644 --- a/src/mainboard/google/eve/Kconfig +++ b/src/mainboard/google/eve/Kconfig @@ -44,11 +44,6 @@ config TPM_TIS_ACPI_INTERRUPT int default 64 # GPE0_DW2_00 (GPP_E0) -config GBB_HWID - string - depends on CHROMEOS - default "EVE TEST 1394" - config IRQ_SLOT_COUNT int default 18 diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index b05cb6c16d..44ac064bd1 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -44,12 +44,6 @@ config VBOOT config DRIVER_TPM_SPI_BUS default 0x1 -config GBB_HWID - string - depends on CHROMEOS - default "FIZZ TEST 5997" if BOARD_GOOGLE_FIZZ - default "KARMA TEST 5022" if BOARD_GOOGLE_KARMA - config MAINBOARD_DIR string default "google/fizz" diff --git a/src/mainboard/google/foster/Kconfig b/src/mainboard/google/foster/Kconfig index f3e7808208..6157519434 100644 --- a/src/mainboard/google/foster/Kconfig +++ b/src/mainboard/google/foster/Kconfig @@ -80,11 +80,6 @@ config DRIVER_TPM_I2C_ADDR # string # default "nyan" -config GBB_HWID - string - depends on CHROMEOS - default "FOSTER TEST 1184" - config VBOOT_FWID_MODEL string default "Nvidia_Foster" diff --git a/src/mainboard/google/gale/Kconfig b/src/mainboard/google/gale/Kconfig index f8def87ca2..5e00be0ef4 100644 --- a/src/mainboard/google/gale/Kconfig +++ b/src/mainboard/google/gale/Kconfig @@ -48,11 +48,6 @@ config MAINBOARD_PART_NUMBER default "DK01" if BOARD_VARIANT_DK01 default "Gale" -config GBB_HWID - string - depends on CHROMEOS - default "Gale TEST 1" - config DRAM_SIZE_MB int default 512 if BOARD_VARIANT_DK01 diff --git a/src/mainboard/google/glados/Kconfig b/src/mainboard/google/glados/Kconfig index b75b726dc1..8e48dc710f 100644 --- a/src/mainboard/google/glados/Kconfig +++ b/src/mainboard/google/glados/Kconfig @@ -87,17 +87,6 @@ config EC_GOOGLE_CHROMEEC_PD_BOARDNAME default "glados_pd" if BOARD_GOOGLE_GLADOS default "" -config GBB_HWID - string - depends on CHROMEOS - default "ASUKA TEST 2547" if BOARD_GOOGLE_ASUKA - default "CAROLINE TEST 0958" if BOARD_GOOGLE_CAROLINE - default "CAVE TEST 9629" if BOARD_GOOGLE_CAVE - default "CHELL TEST 6297" if BOARD_GOOGLE_CHELL - default "GLADOS TEST 1988" if BOARD_GOOGLE_GLADOS - default "LARS TEST 5001" if BOARD_GOOGLE_LARS - default "SENTRY TEST 6297" if BOARD_GOOGLE_SENTRY - config UART_FOR_CONSOLE int default 2 diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig index 49944a855e..e7db1858db 100644 --- a/src/mainboard/google/gru/Kconfig +++ b/src/mainboard/google/gru/Kconfig @@ -115,14 +115,4 @@ config MAINBOARD_PART_NUMBER default "Nefario" if BOARD_GOOGLE_NEFARIO default "Rainier" if BOARD_GOOGLE_RAINIER -config GBB_HWID - string - depends on CHROMEOS - default "SCARLET TEST 7598" if BOARD_GOOGLE_SCARLET - default "BOB TEST 7422" if BOARD_GOOGLE_BOB - default "GRU TEST 5431" if BOARD_GOOGLE_GRU - default "KEVIN TEST 1422" if BOARD_GOOGLE_KEVIN - default "NEFARIO TEST 3735" if BOARD_GOOGLE_NEFARIO - default "RAINIER TEST 9752" if BOARD_GOOGLE_RAINIER - endif # BOARD_GOOGLE_GRU_COMMON diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index d4cf83dfe9..8bb0207e19 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -69,16 +69,6 @@ config FMDFILE default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-16MiB.fmd" if BOARD_ROMSIZE_KB_16384 default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if BOARD_ROMSIZE_KB_32768 -config GBB_HWID - string - depends on CHROMEOS - default "AKEMI TEST 4326" if BOARD_GOOGLE_AKEMI - default "DRATINI TEST 4583" if BOARD_GOOGLE_DRATINI - default "HATCH TEST 1823" if BOARD_GOOGLE_HATCH - default "HELIOS TEST 0878" if BOARD_GOOGLE_HELIOS - default "KINDRED TEST 2636" if BOARD_GOOGLE_KINDRED - default "KOHAKU TEST 1953" if BOARD_GOOGLE_KOHAKU - config MAINBOARD_DIR string default "google/hatch" diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index 5ffc1bc435..041ffcebc8 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -37,14 +37,6 @@ config MAINBOARD_PART_NUMBER default "Rikku" if BOARD_GOOGLE_RIKKU default "Tidus" if BOARD_GOOGLE_TIDUS -config GBB_HWID - string - depends on CHROMEOS - default "GUADO TEST A-A 7416" if BOARD_GOOGLE_GUADO - default "JECHT TEST A-A 8958" if BOARD_GOOGLE_JECHT - default "RIKKU TEST A-A 0702" if BOARD_GOOGLE_RIKKU - default "TIDUS TEST A-A 0595" if BOARD_GOOGLE_TIDUS - config MAX_CPUS int default 8 diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index b675f33fc5..a83b07a6b7 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -110,15 +110,6 @@ config VBOOT_VBNV_OFFSET config CHROMEOS select LP_DEFCONFIG_OVERRIDE if PAYLOAD_DEPTHCHARGE -config GBB_HWID - string - depends on CHROMEOS - default "ALEENA TEST 7281" if BOARD_GOOGLE_ALEENA - default "CAREENA TEST 8777" if BOARD_GOOGLE_CAREENA - default "GRUNT TEST 8296" if BOARD_GOOGLE_GRUNT - default "LIARA TEST 0464" if BOARD_GOOGLE_LIARA - default "TREEYA TEST 0307" if BOARD_GOOGLE_TREEYA - config AMD_FWM_POSITION_INDEX int default 1 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 282891846b..542ee108a7 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -70,13 +70,4 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS hex default 0x2 -config GBB_HWID - string - depends on CHROMEOS - default "KUKUI TEST 9847" if BOARD_GOOGLE_KUKUI - default "KRANE TEST 5417" if BOARD_GOOGLE_KRANE - default "KODAMA TEST 7122" if BOARD_GOOGLE_KODAMA - default "FLAPJACK TEST 4147" if BOARD_GOOGLE_FLAPJACK - default "JACUZZI TEST 6792" if BOARD_GOOGLE_JACUZZI - default "JUNIPER TEST 4819" if BOARD_GOOGLE_JUNIPER endif diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index 6d62f64e3e..b7421900dc 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -39,11 +39,6 @@ config VGA_BIOS_FILE string default "pci8086,0166.rom" -config GBB_HWID - string - depends on CHROMEOS - default "X86 LINK TEST 6638" - config MAINBOARD_SMBIOS_MANUFACTURER string default "GOOGLE" diff --git a/src/mainboard/google/mistral/Kconfig b/src/mainboard/google/mistral/Kconfig index a2ba7cc24a..d6f9b169a3 100644 --- a/src/mainboard/google/mistral/Kconfig +++ b/src/mainboard/google/mistral/Kconfig @@ -36,9 +36,4 @@ config MAINBOARD_PART_NUMBER string default "Mistral" if BOARD_GOOGLE_MISTRAL -config GBB_HWID - string - depends on CHROMEOS - default "MISTRAL TEST 1859" if BOARD_GOOGLE_MISTRAL - endif # BOARD_GOOGLE_MISTRAL_COMMON diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig index 9f4720f583..5ad945e12d 100644 --- a/src/mainboard/google/nyan/Kconfig +++ b/src/mainboard/google/nyan/Kconfig @@ -79,8 +79,4 @@ config DRIVER_TPM_I2C_ADDR hex default 0x20 -config GBB_HWID - string - depends on CHROMEOS - default "NYAN TEST 9382" endif # BOARD_GOOGLE_NYAN diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig index 9a050c44a0..bef25577a9 100644 --- a/src/mainboard/google/nyan_big/Kconfig +++ b/src/mainboard/google/nyan_big/Kconfig @@ -81,8 +81,4 @@ config DRIVER_TPM_I2C_ADDR hex default 0x20 -config GBB_HWID - string - depends on CHROMEOS - default "BIG TEST 9382" endif # BOARD_GOOGLE_NYAN_BIG diff --git a/src/mainboard/google/nyan_blaze/Kconfig b/src/mainboard/google/nyan_blaze/Kconfig index 1e91da9d9e..cb001538c9 100644 --- a/src/mainboard/google/nyan_blaze/Kconfig +++ b/src/mainboard/google/nyan_blaze/Kconfig @@ -81,8 +81,4 @@ config DRIVER_TPM_I2C_ADDR hex default 0x20 -config GBB_HWID - string - depends on CHROMEOS - default "BLAZE TEST 9xxx" endif # BOARD_GOOGLE_NYAN_BLAZE diff --git a/src/mainboard/google/oak/Kconfig b/src/mainboard/google/oak/Kconfig index c383fa4597..f943a4f437 100644 --- a/src/mainboard/google/oak/Kconfig +++ b/src/mainboard/google/oak/Kconfig @@ -90,13 +90,6 @@ config MAINBOARD_PART_NUMBER default "Elm" if BOARD_GOOGLE_ELM default "Hana" if BOARD_GOOGLE_HANA -config GBB_HWID - string - depends on CHROMEOS - default "OAK TEST 6858" if BOARD_GOOGLE_OAK - default "ELM TEST 3839" if BOARD_GOOGLE_ELM - default "HANA TEST 5855" if BOARD_GOOGLE_HANA - # All Oak-derivatives count their board IDs as 0 being equivalent to Oak rev6. config BOARD_ID_ADJUSTMENT int diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 8ca9251cfc..81204188b1 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -86,20 +86,6 @@ config MAINBOARD_FAMILY string default "Google_Octopus" -config GBB_HWID - string - depends on CHROMEOS - default "YORP TEST 7755" if BOARD_GOOGLE_YORP - default "PHASER TEST 7167" if BOARD_GOOGLE_PHASER - default "FLEEX TEST 7423" if BOARD_GOOGLE_FLEEX - default "BOBBA TEST 4516" if BOARD_GOOGLE_BOBBA - default "MEEP TEST 1118" if BOARD_GOOGLE_MEEP - default "AMPTON TEST 1285" if BOARD_GOOGLE_AMPTON - default "CASTA TEST 8105" if BOARD_GOOGLE_CASTA - default "BLOOG TEST 2509" if BOARD_GOOGLE_BLOOG - default "OCTOPUS TEST 6859" if BOARD_GOOGLE_OCTOPUS - default "GARG TEST 1337" if BOARD_GOOGLE_GARG - config MAX_CPUS int default 4 diff --git a/src/mainboard/google/peach_pit/Kconfig b/src/mainboard/google/peach_pit/Kconfig index 75f0f0a1e5..fc2ceb83ad 100644 --- a/src/mainboard/google/peach_pit/Kconfig +++ b/src/mainboard/google/peach_pit/Kconfig @@ -52,8 +52,4 @@ config UART_FOR_CONSOLE int default 3 -config GBB_HWID - string - depends on CHROMEOS - default "PEACH TEST A-A 9382" endif # BOARD_GOOGLE_PEACH_PIT diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index fda8c9e8b8..91de9a8c71 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -47,17 +47,6 @@ config DRIVER_TPM_SPI_BUS depends on MAINBOARD_HAS_SPI_TPM_CR50 default 0x1 -config GBB_HWID - string - depends on CHROMEOS - default "ATLAS TEST 1412" if BOARD_GOOGLE_ATLAS - default "POPPY TEST 8294" if BOARD_GOOGLE_POPPY - default "NAMI TEST 1669" if BOARD_GOOGLE_NAMI - default "NAUTILUS TEST 3013" if BOARD_GOOGLE_NAUTILUS - default "NOCTURNE TEST 3421" if BOARD_GOOGLE_NOCTURNE - default "RAMMUS TEST 2130" if BOARD_GOOGLE_RAMMUS - default "SORAKA TEST 1869" if BOARD_GOOGLE_SORAKA - config INCLUDE_NHLT_BLOBS bool "Include blobs for audio." select NHLT_DMIC_2CH diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 56d44bcea0..63e0d5676c 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -62,26 +62,6 @@ config MAINBOARD_PART_NUMBER default "Swanky" if BOARD_GOOGLE_SWANKY default "Winky" if BOARD_GOOGLE_WINKY -config GBB_HWID - string - depends on CHROMEOS - default "BANJO TEST A-A 8843" if BOARD_GOOGLE_BANJO - default "CANDY TEST A-A 3347" if BOARD_GOOGLE_CANDY - default "CLAPPER TEST A-A 7705" if BOARD_GOOGLE_CLAPPER - default "ENGUARDE TEST A-A 0128" if BOARD_GOOGLE_ENGUARDE - default "GLIMMER TEST 8028" if BOARD_GOOGLE_GLIMMER - default "GNAWTY TEST A-A 3347" if BOARD_GOOGLE_GNAWTY - default "HELI TEST A-A 7705" if BOARD_GOOGLE_HELI - default "KIP TEST A-A 0128" if BOARD_GOOGLE_KIP - default "NINJA TEST A-A 0653" if BOARD_GOOGLE_NINJA - default "ORCO TEST 8028" if BOARD_GOOGLE_ORCO - default "QUAWKS TEST A-A 3347" if BOARD_GOOGLE_QUAWKS - default "RAMBI TEST A-A 0128" if BOARD_GOOGLE_RAMBI - default "SQUAWKS TEST A-A 7705" if BOARD_GOOGLE_SQUAWKS - default "SUMO TEST A-A 8843" if BOARD_GOOGLE_SUMO - default "SWANKY TEST A-A 0653" if BOARD_GOOGLE_SWANKY - default "WINKY TEST 0128" if BOARD_GOOGLE_WINKY - config DEVICETREE string default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index d2240a8397..520b78819f 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -81,16 +81,6 @@ config MAINBOARD_FAMILY default "Google_Coral" if BOARD_GOOGLE_CORAL default "Google_Reef" -config GBB_HWID - string - depends on CHROMEOS - default "REEF TEST 3240" if BOARD_GOOGLE_REEF - default "PYRO TEST 0290" if BOARD_GOOGLE_PYRO - default "SAND TEST 1904" if BOARD_GOOGLE_SAND - default "SNAPPY TEST 1088" if BOARD_GOOGLE_SNAPPY - default "NASHER TEST 4258" if BOARD_GOOGLE_NASHER - default "CORAL TEST 8594" if BOARD_GOOGLE_CORAL - config MAX_CPUS int default 8 diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index e6d1f1f60f..455fbc205f 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -62,12 +62,6 @@ config POWER_OFF_ON_CR50_UPDATE bool default n -config GBB_HWID - string - depends on CHROMEOS - default "ARCADA TEST 3556" if BOARD_GOOGLE_ARCADA - default "SARIEN TEST 2787" if BOARD_GOOGLE_SARIEN - config MAINBOARD_DIR string default "google/sarien" diff --git a/src/mainboard/google/slippy/Kconfig b/src/mainboard/google/slippy/Kconfig index 35fced0231..68b92bb3f3 100644 --- a/src/mainboard/google/slippy/Kconfig +++ b/src/mainboard/google/slippy/Kconfig @@ -47,14 +47,6 @@ config MAINBOARD_FAMILY string default "Google_Slippy" -config GBB_HWID - string - depends on CHROMEOS - default "X86 FALCO TEST 0289" if BOARD_GOOGLE_FALCO - default "X86 LEON TEST 5181" if BOARD_GOOGLE_LEON - default "X86 PEPPY TEST 4211" if BOARD_GOOGLE_PEPPY - default "X86 WOLF TEST 6457" if BOARD_GOOGLE_WOLF - config DEVICETREE string default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" diff --git a/src/mainboard/google/smaug/Kconfig b/src/mainboard/google/smaug/Kconfig index 8a2927bbb4..2b9be0262a 100644 --- a/src/mainboard/google/smaug/Kconfig +++ b/src/mainboard/google/smaug/Kconfig @@ -86,8 +86,4 @@ config EC_GOOGLE_CHROMEEC_I2C_BUS hex default 0x1 -config GBB_HWID - string - depends on CHROMEOS - default "SMAUG TEST 2906" endif # BOARD_GOOGLE_SMAUG diff --git a/src/mainboard/google/storm/Kconfig b/src/mainboard/google/storm/Kconfig index e6240747cc..3abea56c86 100644 --- a/src/mainboard/google/storm/Kconfig +++ b/src/mainboard/google/storm/Kconfig @@ -59,8 +59,4 @@ config DRIVER_TPM_I2C_ADDR hex default 0x20 -config GBB_HWID - string - depends on CHROMEOS - default "Storm TEST 1" endif # BOARD_GOOGLE_STORM diff --git a/src/mainboard/google/urara/Kconfig b/src/mainboard/google/urara/Kconfig index 19d5c41795..3cbe7ed5f9 100644 --- a/src/mainboard/google/urara/Kconfig +++ b/src/mainboard/google/urara/Kconfig @@ -52,9 +52,4 @@ config CONSOLE_SERIAL_UART_ADDRESS config BOOT_DEVICE_SPI_FLASH_BUS int default 1 - -config GBB_HWID - string - depends on CHROMEOS - default "Urara TEST 1" endif diff --git a/src/mainboard/google/veyron/Kconfig b/src/mainboard/google/veyron/Kconfig index 9c126fd765..8e29661929 100644 --- a/src/mainboard/google/veyron/Kconfig +++ b/src/mainboard/google/veyron/Kconfig @@ -105,13 +105,4 @@ config EC_GOOGLE_CHROMEEC_BOARDNAME #default "minnie" if BOARD_GOOGLE_VEYRON_MINNIE #default "speedy" if BOARD_GOOGLE_VEYRON_SPEEDY -config GBB_HWID - string - depends on CHROMEOS - default "JAQ TEST A-A 8292" if BOARD_GOOGLE_VEYRON_JAQ - default "JERRY TEST A-A 1250" if BOARD_GOOGLE_VEYRON_JERRY - default "MIGHTY TEST A-A 4557" if BOARD_GOOGLE_VEYRON_MIGHTY - default "MINNIE TEST A-A 5151" if BOARD_GOOGLE_VEYRON_MINNIE - default "SPEEDY TEST A-A 8421" if BOARD_GOOGLE_VEYRON_SPEEDY - endif # BOARD_GOOGLE_VEYRON diff --git a/src/mainboard/google/veyron_mickey/Kconfig b/src/mainboard/google/veyron_mickey/Kconfig index 46bc0de7e6..876d70ea2b 100644 --- a/src/mainboard/google/veyron_mickey/Kconfig +++ b/src/mainboard/google/veyron_mickey/Kconfig @@ -63,9 +63,4 @@ config PMIC_BUS int default 0 -config GBB_HWID - string - depends on CHROMEOS - default "MICKEY TEST A-A 0352" - endif # BOARD_GOOGLE_VEYRON_MICKEY diff --git a/src/mainboard/google/veyron_rialto/Kconfig b/src/mainboard/google/veyron_rialto/Kconfig index 189f010a96..4550c5b822 100644 --- a/src/mainboard/google/veyron_rialto/Kconfig +++ b/src/mainboard/google/veyron_rialto/Kconfig @@ -63,8 +63,4 @@ config PMIC_BUS int default 0 -config GBB_HWID - string - depends on CHROMEOS - default "RIALTO TEST A-A 2322" endif # BOARD_GOOGLE_VEYRON_RIALTO diff --git a/src/mainboard/intel/glkrvp/Kconfig b/src/mainboard/intel/glkrvp/Kconfig index 920b446aad..f10a9f0fa4 100644 --- a/src/mainboard/intel/glkrvp/Kconfig +++ b/src/mainboard/intel/glkrvp/Kconfig @@ -68,11 +68,6 @@ config MAINBOARD_FAMILY string default "Intel_Glkrvp" if BOARD_INTEL_GLKRVP -config GBB_HWID - string - depends on CHROMEOS - default "GLKRVP TEST A-A 6939" if BOARD_INTEL_GLKRVP - config MAX_CPUS int default 4 diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index c0737cbce6..afc510fe4e 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -51,11 +51,6 @@ config TPM_PIRQ hex default 0x18 # GPP_E0_IRQ -config GBB_HWID - string - depends on CHROMEOS - default "KBLRVP TEST 8819" - config DEVICETREE string default "variants/baseboard/devicetree.cb" diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig index f4dd4b1057..63961513b9 100644 --- a/src/mainboard/intel/kunimitsu/Kconfig +++ b/src/mainboard/intel/kunimitsu/Kconfig @@ -69,11 +69,6 @@ config INCLUDE_NHLT_BLOBS select NHLT_NAU88L25 select NHLT_SSM4567 -config GBB_HWID - string - depends on CHROMEOS - default "KUNIMITSU TEST 8819" - config UART_FOR_CONSOLE int default 2 diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig index da04d78a05..1f6a73d474 100644 --- a/src/mainboard/intel/strago/Kconfig +++ b/src/mainboard/intel/strago/Kconfig @@ -54,11 +54,6 @@ config EC_GOOGLE_CHROMEEC_BOARDNAME string default "strago" -config GBB_HWID - string - depends on CHROMEOS - default "STRAGO TEST A-A 9657" - config CBFS_SIZE hex default 0x200000 From cc0dd5f8a2b017dbca8514b26697f5d3970c7ffe Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 22 Sep 2019 13:54:30 +0200 Subject: [PATCH 36/75] mb/supermicro/x11-lga1151-series: fix cmos layout and add default config MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes the warning that power_on_after_fail could not be found, adds a default config and adds the parameter hyper_threading. Change-Id: I10b0aa71fa7916b01e93e16cbd81e427fd14f6a4 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/35526 Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/mainboard/supermicro/x11-lga1151-series/Kconfig | 1 + .../supermicro/x11-lga1151-series/cmos.default | 3 +++ .../supermicro/x11-lga1151-series/cmos.layout | 13 ++++++++++++- 3 files changed, 16 insertions(+), 1 deletion(-) create mode 100644 src/mainboard/supermicro/x11-lga1151-series/cmos.default diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index 6fc9aed7f0..541b23d5b5 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -4,6 +4,7 @@ config BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT select SOC_INTEL_KABYLAKE select SKYLAKE_SOC_PCH_H select MAINBOARD_HAS_LPC_TPM diff --git a/src/mainboard/supermicro/x11-lga1151-series/cmos.default b/src/mainboard/supermicro/x11-lga1151-series/cmos.default new file mode 100644 index 0000000000..d56495357c --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/cmos.default @@ -0,0 +1,3 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Enable diff --git a/src/mainboard/supermicro/x11-lga1151-series/cmos.layout b/src/mainboard/supermicro/x11-lga1151-series/cmos.layout index 201ca3320c..03aea17f8f 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/cmos.layout +++ b/src/mainboard/supermicro/x11-lga1151-series/cmos.layout @@ -17,7 +17,6 @@ entries #start-bit length config config-ID name - 0 120 r 0 reserved_memory # ----------------------------------------------------------------- @@ -28,8 +27,20 @@ entries # ----------------------------------------------------------------- # coreboot config options: console 395 4 e 6 debug_level + +# ----------------------------------------------------------------- +# coreboot config options: cpu +400 1 e 2 hyper_threading + +# ----------------------------------------------------------------- +# coreboot config options: southbridge +409 2 e 7 power_on_after_fail + +# ----------------------------------------------------------------- +# coreboot config options: bootloader 448 128 r 0 vbnv +# ----------------------------------------------------------------- # coreboot config options: check sums 984 16 h 0 check_sum From 6ba9b5a86f0cf1362fa07079912a10a99ad9b079 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Mon, 23 Sep 2019 15:17:39 +0200 Subject: [PATCH 37/75] mb/supermicro/x11-lga1151-series: x11ssh-tf: remove unneeded ACPI ifdef MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This removes the "ifdef ACPI" which is not needed here as we currently don't include gpio.h in any asl file. Change-Id: I803bbee5933eda9423a9bc9fcaea9e905e3ac78e Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/35543 Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- .../variants/x11ssh-tf/include/variant/gpio.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h index a5eed6bd13..83fb22db7d 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h @@ -19,7 +19,6 @@ #include #include -#ifndef __ACPI__ static const struct pad_config gpio_table[] = { /* RCIN# */ _PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x00000000), /* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x00000000), @@ -244,5 +243,4 @@ static const struct pad_config early_gpio_table[] = { /* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000000), }; -#endif /* __ACPI__ */ #endif /* _GPIO_X11SSH_TF_H */ From 45ffee83464156a58a57570b22ba35ab2859e532 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 26 Sep 2019 14:45:29 +0200 Subject: [PATCH 38/75] soc/intel/skylake: Fix ACPI exception AE_NOT_FOUND Make sure to match devices on the root bus only. This fixes an issue where the SoC returned "MCHC" as ACPI name for devices behind bridge devices, as the DEVFN matched. Fixes observed "ACPI exception: AE_NOT_FOUND" in dmesg, as the ACPI path no longer contains invalid names. Tested on Supermicro X11SSH-TF. Change-Id: I6eca37a1792287502a46a90144f2f0d8e12ae5d4 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/35621 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Aaron Durbin --- src/soc/intel/skylake/acpi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index c3757b0bd3..d67b502ac8 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -760,6 +760,10 @@ const char *soc_acpi_name(const struct device *dev) if (dev->path.type != DEVICE_PATH_PCI) return NULL; + /* Only match devices on the root bus */ + if (dev->bus && dev->bus->secondary > 0) + return NULL; + switch (dev->path.pci.devfn) { case SA_DEVFN_ROOT: return "MCHC"; case SA_DEVFN_IGD: return "GFX0"; From 2422f8c21e4590dcf75239583099a467f79f9878 Mon Sep 17 00:00:00 2001 From: Dawei Chien Date: Thu, 30 May 2019 11:55:10 +0800 Subject: [PATCH 39/75] mediatek/mt8183: Init SPM driver To support mt8183 power saving during suspend to RAM, this patch loads SPM firmware to support SPM suspend. SPM needs its own firmware to do these power saving in the right timing under correct conditions. After linux PM suspends, SPM is able to turn off power for the last CPU and do more power saving for the SoC such as DRAM self-refresh mode and turning off 26M crystal. BUG=none BRANCH=none TEST=suspend/resume passes for LPDDR4 3200 Change-Id: I3393a772f025b0912a5a25a63a87512454fbc86e Signed-off-by: Dawei Chien Reviewed-on: https://review.coreboot.org/c/coreboot/+/34545 Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu Reviewed-by: Hung-Te Lin --- src/mainboard/google/kukui/mainboard.c | 4 + src/soc/mediatek/mt8183/Makefile.inc | 15 +- src/soc/mediatek/mt8183/include/soc/spm.h | 186 +++++++++--- src/soc/mediatek/mt8183/spm.c | 351 ++++++++++++++++++++++ 4 files changed, 507 insertions(+), 49 deletions(-) create mode 100644 src/soc/mediatek/mt8183/spm.c diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index 7b00d94ba6..844496d7a0 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -201,6 +202,9 @@ static void mainboard_init(struct device *dev) configure_emmc(); configure_usb(); configure_audio(); + if (spm_init()) + printk(BIOS_ERR, + "SPM initialization failed, suspend/resume may fail.\n"); register_reset_to_bl31(); } diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index b6c3a33819..d1171ef379 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -55,6 +55,7 @@ ramstage-y += ../common/pmic_wrap.c ramstage-y += ../common/rtc.c rtc.c ramstage-y += soc.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +ramstage-y += spm.c ramstage-y += sspm.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c @@ -62,8 +63,20 @@ ramstage-y += ../common/usb.c ramstage-y += ../common/wdt.c ramstage-y += md_ctrl.c +MT8183_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8183 + +cbfs-files-y += pcm_allinone_lp4_3200.bin +pcm_allinone_lp4_3200.bin-file := $(MT8183_BLOB_DIR)/pcm_allinone_lp4_3200.bin +pcm_allinone_lp4_3200.bin-type := raw +pcm_allinone_lp4_3200.bin-compression := $(CBFS_COMPRESS_FLAG) + +cbfs-files-y += pcm_allinone_lp4_3733.bin +pcm_allinone_lp4_3733.bin-file := $(MT8183_BLOB_DIR)/pcm_allinone_lp4_3733.bin +pcm_allinone_lp4_3733.bin-type := raw +pcm_allinone_lp4_3733.bin-compression := $(CBFS_COMPRESS_FLAG) + cbfs-files-y += sspm.bin -sspm.bin-file := 3rdparty/blobs/soc/mediatek/mt8183/sspm.bin +sspm.bin-file := $(MT8183_BLOB_DIR)/sspm.bin sspm.bin-type := raw sspm.bin-compression := $(CBFS_COMPRESS_FLAG) diff --git a/src/soc/mediatek/mt8183/include/soc/spm.h b/src/soc/mediatek/mt8183/include/soc/spm.h index 5e7770eecb..4ca72b632a 100644 --- a/src/soc/mediatek/mt8183/include/soc/spm.h +++ b/src/soc/mediatek/mt8183/include/soc/spm.h @@ -16,12 +16,122 @@ #ifndef SOC_MEDIATEK_MT8183_SPM_H #define SOC_MEDIATEK_MT8183_SPM_H +#include +#include #include +#include +#include #include -enum { - SPM_PROJECT_CODE = 0xb16 -}; +/* SPM READ/WRITE CFG */ +#define SPM_PROJECT_CODE 0xb16 +#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) + +/* POWERON_CONFIG_EN (0x10006000+0x000) */ +#define BCLK_CG_EN_LSB (1U << 0) /* 1b */ +#define MD_BCLK_CG_EN_LSB (1U << 1) /* 1b */ +#define PCM_IM_HOST_W_EN_LSB (1U << 30) /* 1b */ +#define PCM_IM_HOST_EN_LSB (1U << 31) /* 1b */ + +/* SPM_CLK_CON (0x10006000+0x00C) */ +#define SYSCLK0_EN_CTRL_LSB (1U << 0) /* 2b */ +#define SYSCLK1_EN_CTRL_LSB (1U << 2) /* 2b */ +#define SPM_LOCK_INFRA_DCM_LSB (1U << 5) /* 1b */ +#define EXT_SRCCLKEN_MASK (1U << 6) /* 1b */ +#define CXO32K_REMOVE_EN_MD1_LSB (1U << 9) /* 1b */ +#define CLKSQ1_SEL_CTRL_LSB (1U << 12) /* 1b */ +#define SRCLKEN0_EN_LSB (1U << 13) /* 1b */ + +/* PCM_CON0 (0x10006000+0x018) */ +#define PCM_KICK_L_LSB (1U << 0) /* 1b */ +#define IM_KICK_L_LSB (1U << 1) /* 1b */ +#define PCM_CK_EN_LSB (1U << 2) /* 1b */ +#define EN_IM_SLEEP_DVS_LSB (1U << 3) /* 1b */ +#define IM_AUTO_PDN_EN_LSB (1U << 4) /* 1b */ +#define PCM_SW_RESET_LSB (1U << 15) /* 1b */ + +/* PCM_CON1 (0x10006000+0x01C) */ +#define IM_SLAVE_LSB (1U << 0) /* 1b */ +#define IM_SLEEP_LSB (1U << 1) /* 1b */ +#define MIF_APBEN_LSB (1U << 3) /* 1b */ +#define IM_PDN_LSB (1U << 4) /* 1b */ +#define PCM_TIMER_EN_LSB (1U << 5) /* 1b */ +#define IM_NONRP_EN_LSB (1U << 6) /* 1b */ +#define DIS_MIF_PROT_LSB (1U << 7) /* 1b */ +#define PCM_WDT_EN_LSB (1U << 8) /* 1b */ +#define PCM_WDT_WAKE_MODE_LSB (1U << 9) /* 1b */ +#define SPM_SRAM_SLEEP_B_LSB (1U << 10) /* 1b */ +#define SPM_SRAM_ISOINT_B_LSB (1U << 11) /* 1b */ +#define EVENT_LOCK_EN_LSB (1U << 12) /* 1b */ +#define SRCCLKEN_FAST_RESP_LSB (1U << 13) /* 1b */ +#define SCP_APB_INTERNAL_EN_LSB (1U << 14) /* 1b */ + +/* SPM_IRQ_MASK (0x10006000+0x0B4) */ +#define PCM_IRQ_ROOT_MASK_LSB (1U << 3) /* 1b */ + +/* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0C4) */ +#define WAKEUP_EVENT_MASK_B_BIT0 (1U << 0) /* 1b */ + +/* SPARE_SRC_REQ_MASK (0x10006000+0x6C0) */ +#define SPARE1_DDREN_MASK_B_LSB (1U << 0) /* 1b */ + +/* SPM_PC_TRACE_CON (0x10006000+0x8C0) */ +#define SPM_PC_TRACE_OFFSET_LSB (1U << 0) /* 12b */ +#define SPM_PC_TRACE_OFFSET (1U << 3) /* 1b */ +#define SPM_PC_TRACE_HW_EN_LSB (1U << 16) /* 1b */ + +/* SPM_SPARE_ACK_MASK (0x10006000+0x6F4) */ +#define SPARE_ACK_MASK_B_BIT0 (1U << 0) /* 1b */ +#define SPARE_ACK_MASK_B_BIT1 (1U << 1) /* 1b */ + +/************************************** + * Config and Parameter + **************************************/ +#define CONN_DDR_EN_DBC_LEN (0x00000154 << 20) +#define IFR_SRAMROM_ROM_PDN (0x0000003f) +#define IM_STATE (0x4 << 7) +#define IM_STATE_MASK (0x7 << 7) +#define MD_DDR_EN_0_DBC_LEN (0x00000154) +#define MD_DDR_EN_1_DBC_LEN (0x00000154 << 10) +#define PCM_FSM_STA_DEF (0x00108490) +#define PCM_FSM_STA_MASK (0x7FFFFF) +#define POWER_ON_VAL1_DEF (0x00015800) +#define SPM_CORE_TIMEOUT (5000) +#define SPM_MAS_PAUSE_MASK_B_VAL (0xFFFFFFFF) +#define SPM_MAS_PAUSE2_MASK_B_VAL (0xFFFFFFFF) +#define SPM_PCM_REG1_DATA_CHECK (0x1) +#define SPM_PCM_REG15_DATA_CHECK (0x0) +#define SPM_WAKEUP_EVENT_MASK_DEF (0xF0F92218) +#define SYSCLK1_EN_CTRL (0x3 << 2) +#define SYSCLK1_SRC_MASK_B (0x10 << 23) + +/************************************** + * Define and Declare + **************************************/ +/* SPM_IRQ_MASK */ +#define ISRM_TWAM (1U << 2) +#define ISRM_PCM_RETURN (1U << 3) +#define ISRM_RET_IRQ_AUX (0x3FF00) +#define ISRM_ALL_EXC_TWAM (ISRM_RET_IRQ_AUX) +#define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM) + +/* SPM_IRQ_STA */ +#define ISRS_TWAM (1U << 2) +#define ISRS_PCM_RETURN (1U << 3) +#define ISRS_SW_INT0 (1U << 4) +#define ISRC_TWAM (ISRS_TWAM) +#define ISRC_ALL_EXC_TWAM (ISRS_PCM_RETURN) +#define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM) + +/* PCM_PWR_IO_EN */ +#define PCM_PWRIO_EN_R0 (1U << 0) +#define PCM_PWRIO_EN_R7 (1U << 7) +#define PCM_RF_SYNC_R0 (1U << 16) +#define PCM_RF_SYNC_R6 (1U << 22) +#define PCM_RF_SYNC_R7 (1U << 23) + +/* SPM_SWINT */ +#define PCM_SW_INT_ALL (0x3FF) enum { DISP_SRAM_PDN_MASK = 0x1 << 8, @@ -30,6 +140,8 @@ enum { AUDIO_SRAM_ACK_MASK = 0xf << 12, }; +#define PCM_EVENT_VECTOR_NUM 16 + struct mtk_spm_regs { u32 poweron_config_set; u32 spm_power_on_val0; @@ -47,22 +159,7 @@ struct mtk_spm_regs { u32 pcm_wdt_val; u32 pcm_im_host_rw_ptr; u32 pcm_im_host_rw_dat; - u32 pcm_event_vector0; - u32 pcm_event_vector1; - u32 pcm_event_vector2; - u32 pcm_event_vector3; - u32 pcm_event_vector4; - u32 pcm_event_vector5; - u32 pcm_event_vector6; - u32 pcm_event_vector7; - u32 pcm_event_vector8; - u32 pcm_event_vector9; - u32 pcm_event_vector10; - u32 pcm_event_vector11; - u32 pcm_event_vector12; - u32 pcm_event_vector13; - u32 pcm_event_vector14; - u32 pcm_event_vector15; + u32 pcm_event_vector[PCM_EVENT_VECTOR_NUM]; u32 pcm_event_vector_en; u32 reserved1[1]; u32 spm_sram_rsv_con; @@ -472,37 +569,30 @@ struct mtk_spm_regs { u32 spm_ack_chk_sta4; u32 spm_ack_chk_latch4; }; - -check_member(mtk_spm_regs, pcm_reg0_data, 0x0100); -check_member(mtk_spm_regs, src_ddren_sta, 0x01e0); -check_member(mtk_spm_regs, mcu_pwr_con, 0x0200); -check_member(mtk_spm_regs, mp0_cputop_l2_pdn, 0x0240); -check_member(mtk_spm_regs, cpu_ext_buck_iso, 0x0290); -check_member(mtk_spm_regs, dummy1_pwr_con, 0x02b0); -check_member(mtk_spm_regs, vde_pwr_con, 0x0300); -check_member(mtk_spm_regs, ufs_sram_con, 0x036c); -check_member(mtk_spm_regs, dummy_sram_con, 0x0380); -check_member(mtk_spm_regs, md_ext_buck_iso_con, 0x0390); -check_member(mtk_spm_regs, mbist_efuse_repair_ack_sta, 0x03d0); -check_member(mtk_spm_regs, spm_dvfs_con, 0x0400); -check_member(mtk_spm_regs, mp0_cpu0_wfi_en, 0x0530); -check_member(mtk_spm_regs, root_cputop_addr, 0x0570); -check_member(mtk_spm_regs, cpu_spare_con, 0x0580); -check_member(mtk_spm_regs, spm2sw_mailbox_0, 0x05d0); -check_member(mtk_spm_regs, spm_sw_rsv_18, 0x067c); -check_member(mtk_spm_regs, dvfsrc_event_mask_con, 0x0690); -check_member(mtk_spm_regs, spare_ack_sta, 0x06f0); -check_member(mtk_spm_regs, spm_dvfs_con1, 0x0700); -check_member(mtk_spm_regs, spm_dvfs_cmd0, 0x0710); -check_member(mtk_spm_regs, wdt_latch_spare0_fix, 0x0780); -check_member(mtk_spm_regs, pcm_wdt_latch_0, 0x0800); -check_member(mtk_spm_regs, spm_pc_trace_con, 0x08c0); -check_member(mtk_spm_regs, spm_ack_chk_con, 0x0900); -check_member(mtk_spm_regs, spm_ack_chk_con2, 0x0920); -check_member(mtk_spm_regs, spm_ack_chk_con3, 0x0940); -check_member(mtk_spm_regs, spm_ack_chk_con4, 0x0960); check_member(mtk_spm_regs, spm_ack_chk_latch4, 0x0974); static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE; +enum dyna_load_pcm_index { + DYNA_LOAD_PCM_SUSPEND_LP4_3733 = 0, + DYNA_LOAD_PCM_SUSPEND_LP4_3200, + DYNA_LOAD_PCM_MAX, +}; + +struct pcm_desc { + u16 size; /* binary array size */ + u8 sess; /* session number */ + u8 replace; /* replace mode */ + u16 addr_2nd; /* 2nd binary array size */ + u16 reserved; /* for 32bit alignment */ + u32 vector[PCM_EVENT_VECTOR_NUM]; /* event vector config */ +}; + +struct dyna_load_pcm { + u32 *buf; /* binary array */ + struct pcm_desc desc; +}; + +int spm_init(void); + #endif /* SOC_MEDIATEK_MT8183_SPM_H */ diff --git a/src/soc/mediatek/mt8183/spm.c b/src/soc/mediatek/mt8183/spm.c new file mode 100644 index 0000000000..669970fb2f --- /dev/null +++ b/src/soc/mediatek/mt8183/spm.c @@ -0,0 +1,351 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define BUF_SIZE (16 * KiB) +static uint8_t spm_bin[BUF_SIZE] __aligned(8); + +static int spm_register_init(void) +{ + u32 pcm_fsm_sta; + + write32(&mtk_spm->poweron_config_set, + SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB | MD_BCLK_CG_EN_LSB); + + write32(&mtk_spm->spm_power_on_val1, POWER_ON_VAL1_DEF); + write32(&mtk_spm->pcm_pwr_io_en, 0); + + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | + PCM_SW_RESET_LSB); + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + + pcm_fsm_sta = read32(&mtk_spm->pcm_fsm_sta); + + if ((pcm_fsm_sta & PCM_FSM_STA_MASK) != PCM_FSM_STA_DEF) { + printk(BIOS_ERR, "PCM reset failed\n"); + return -1; + } + + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | + EN_IM_SLEEP_DVS_LSB); + write32(&mtk_spm->pcm_con1, SPM_REGWR_CFG_KEY | EVENT_LOCK_EN_LSB | + SPM_SRAM_ISOINT_B_LSB | MIF_APBEN_LSB | + SCP_APB_INTERNAL_EN_LSB); + write32(&mtk_spm->pcm_im_ptr, 0); + write32(&mtk_spm->pcm_im_len, 0); + + write32(&mtk_spm->spm_clk_con, + read32(&mtk_spm->spm_clk_con) | SYSCLK1_EN_CTRL | + SPM_LOCK_INFRA_DCM_LSB | EXT_SRCCLKEN_MASK | + CXO32K_REMOVE_EN_MD1_LSB | + CLKSQ1_SEL_CTRL_LSB | SRCLKEN0_EN_LSB | SYSCLK1_SRC_MASK_B); + + write32(&mtk_spm->spm_wakeup_event_mask, SPM_WAKEUP_EVENT_MASK_DEF); + + write32(&mtk_spm->spm_irq_mask, ISRM_ALL); + write32(&mtk_spm->spm_irq_sta, ISRC_ALL); + write32(&mtk_spm->spm_swint_clr, PCM_SW_INT_ALL); + + write32(&mtk_spm->pcm_reg_data_ini, + read32(&mtk_spm->spm_power_on_val1)); + write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7); + write32(&mtk_spm->pcm_pwr_io_en, 0); + + write32(&mtk_spm->ddr_en_dbc_len, + MD_DDR_EN_0_DBC_LEN | + MD_DDR_EN_1_DBC_LEN | + CONN_DDR_EN_DBC_LEN); + + clrsetbits_le32(&mtk_spm->spare_ack_mask, + SPARE_ACK_MASK_B_BIT1, + SPARE_ACK_MASK_B_BIT0); + + write32(&mtk_spm->sysrom_con, IFR_SRAMROM_ROM_PDN); + write32(&mtk_spm->spm_pc_trace_con, + SPM_PC_TRACE_OFFSET | + SPM_PC_TRACE_HW_EN_LSB); + + setbits_le32(&mtk_spm->spare_src_req_mask, SPARE1_DDREN_MASK_B_LSB); + + return 0; +} + +static int spm_code_swapping(void) +{ + u32 con1; + + con1 = read32(&mtk_spm->spm_wakeup_event_mask); + + write32(&mtk_spm->spm_wakeup_event_mask, + con1 & ~WAKEUP_EVENT_MASK_B_BIT0); + write32(&mtk_spm->spm_cpu_wakeup_event, 1); + + if (!wait_us(SPM_CORE_TIMEOUT, + read32(&mtk_spm->spm_irq_sta) & PCM_IRQ_ROOT_MASK_LSB)) { + printk(BIOS_ERR, + "timeout: r15=%#x, pcmsta=%#x, irqsta=%#x [%d]\n", + read32(&mtk_spm->pcm_reg15_data), + read32(&mtk_spm->pcm_fsm_sta), + read32(&mtk_spm->spm_irq_sta), + SPM_CORE_TIMEOUT); + return -1; + } + + write32(&mtk_spm->spm_cpu_wakeup_event, 0); + write32(&mtk_spm->spm_wakeup_event_mask, con1); + return 0; +} + +static int spm_reset_and_init_pcm(const struct pcm_desc *pcmdesc) +{ + u32 con1, pcm_fsm_sta; + + if (read32(&mtk_spm->pcm_reg1_data) == SPM_PCM_REG1_DATA_CHECK && + read32(&mtk_spm->pcm_reg15_data) != SPM_PCM_REG15_DATA_CHECK) { + if (spm_code_swapping()) + return -1; + write32(&mtk_spm->spm_power_on_val0, + read32(&mtk_spm->pcm_reg0_data)); + } + + write32(&mtk_spm->pcm_pwr_io_en, 0); + + clrsetbits_le32(&mtk_spm->pcm_con1, + PCM_TIMER_EN_LSB, + SPM_REGWR_CFG_KEY); + + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | + PCM_SW_RESET_LSB); + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + + pcm_fsm_sta = read32(&mtk_spm->pcm_fsm_sta); + + if ((pcm_fsm_sta & PCM_FSM_STA_MASK) != PCM_FSM_STA_DEF) { + printk(BIOS_ERR, "reset pcm(PCM_FSM_STA=%#x)\n", + read32(&mtk_spm->pcm_fsm_sta)); + return -1; + } + + write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | + EN_IM_SLEEP_DVS_LSB); + + con1 = read32(&mtk_spm->pcm_con1) & PCM_WDT_WAKE_MODE_LSB; + write32(&mtk_spm->pcm_con1, con1 | SPM_REGWR_CFG_KEY | + EVENT_LOCK_EN_LSB | SPM_SRAM_ISOINT_B_LSB | + (pcmdesc->replace ? 0 : IM_NONRP_EN_LSB) | + MIF_APBEN_LSB | SCP_APB_INTERNAL_EN_LSB); + + return 0; +} + +static void spm_load_pcm_code(const struct dyna_load_pcm *pcm) +{ + int i; + + write32(&mtk_spm->pcm_con1, read32(&mtk_spm->pcm_con1) | + SPM_REGWR_CFG_KEY | IM_SLAVE_LSB); + + for (i = 0; i < pcm->desc.size; i++) { + write32(&mtk_spm->pcm_im_host_rw_ptr, + PCM_IM_HOST_EN_LSB | PCM_IM_HOST_W_EN_LSB | i); + write32(&mtk_spm->pcm_im_host_rw_dat, + (u32) *(pcm->buf + i)); + } + write32(&mtk_spm->pcm_im_host_rw_ptr, 0); +} + +static void spm_check_pcm_code(const struct dyna_load_pcm *pcm) +{ + int i; + + for (i = 0; i < pcm->desc.size; i++) { + write32(&mtk_spm->pcm_im_host_rw_ptr, PCM_IM_HOST_EN_LSB | i); + if ((read32(&mtk_spm->pcm_im_host_rw_dat)) != + (u32) *(pcm->buf + i)) + spm_load_pcm_code(pcm); + } + write32(&mtk_spm->pcm_im_host_rw_ptr, 0); +} + +static void spm_kick_im_to_fetch(const struct dyna_load_pcm *pcm) +{ + u32 con0; + + spm_load_pcm_code(pcm); + spm_check_pcm_code(pcm); + + printk(BIOS_DEBUG, "%s: ptr = %p\n", __func__, pcm->buf); + printk(BIOS_DEBUG, "%s: len = %d\n", __func__, pcm->desc.size); + + con0 = read32(&mtk_spm->pcm_con0) & ~(IM_KICK_L_LSB | PCM_KICK_L_LSB); + write32(&mtk_spm->pcm_con0, con0 | SPM_REGWR_CFG_KEY | + PCM_CK_EN_LSB | IM_KICK_L_LSB); + write32(&mtk_spm->pcm_con0, con0 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); +} + +static void spm_init_pcm_register(void) +{ + write32(&mtk_spm->pcm_reg_data_ini, + read32(&mtk_spm->spm_power_on_val0)); + write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R0); + write32(&mtk_spm->pcm_pwr_io_en, 0); + + write32(&mtk_spm->pcm_reg_data_ini, + read32(&mtk_spm->spm_power_on_val1)); + write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7); + write32(&mtk_spm->pcm_pwr_io_en, 0); +} + +static void spm_init_event_vector(const struct pcm_desc *pcmdesc) +{ + for (int i = 0; i < PCM_EVENT_VECTOR_NUM; i++) + write32(&mtk_spm->pcm_event_vector[i], pcmdesc->vector[i]); +} + +static const char * const dyna_load_pcm_path[] = { + [DYNA_LOAD_PCM_SUSPEND_LP4_3733] = "pcm_allinone_lp4_3733.bin", + [DYNA_LOAD_PCM_SUSPEND_LP4_3200] = "pcm_allinone_lp4_3200.bin", +}; + +static int spm_load_firmware(enum dyna_load_pcm_index index, + struct dyna_load_pcm *pcm) +{ + /* + * Layout: + * u16 firmware_size + * u32 binary[firmware_size] + * struct pcm_desc descriptor + * char *version + */ + u16 firmware_size; + int copy_size; + const char *file_name = dyna_load_pcm_path[index]; + struct stopwatch sw; + + stopwatch_init(&sw); + + size_t file_size = cbfs_boot_load_file(file_name, spm_bin, + sizeof(spm_bin), CBFS_TYPE_RAW); + + if (file_size == 0) { + printk(BIOS_ERR, "SPM binary %s not found\n", file_name); + return -1; + } + + int offset = 0; + + /* firmware size */ + copy_size = sizeof(firmware_size); + memcpy(&firmware_size, spm_bin + offset, copy_size); + printk(BIOS_DEBUG, "SPM: binary array size = %d\n", firmware_size); + offset += copy_size; + + /* binary */ + assert(offset < file_size); + copy_size = firmware_size * 4; + pcm->buf = (u32 *)(spm_bin + offset); + offset += copy_size; + + /* descriptor */ + assert(offset < file_size); + copy_size = sizeof(struct pcm_desc); + memcpy((void *)&(pcm->desc.size), spm_bin + offset, copy_size); + offset += copy_size; + + /* version */ + /* The termintating character should be contained in the spm binary */ + assert(spm_bin[file_size - 1] == '\0'); + assert(offset < file_size); + printk(BIOS_DEBUG, "SPM: version = %s\n", spm_bin + offset); + + printk(BIOS_INFO, "SPM binary loaded in %ld msecs\n", + stopwatch_duration_msecs(&sw)); + + return 0; +} + +static void spm_kick_pcm_to_run(void) +{ + uint32_t con0; + + write32(&mtk_spm->spm_mas_pause_mask_b, SPM_MAS_PAUSE_MASK_B_VAL); + write32(&mtk_spm->spm_mas_pause2_mask_b, SPM_MAS_PAUSE2_MASK_B_VAL); + write32(&mtk_spm->pcm_reg_data_ini, 0); + + write32(&mtk_spm->pcm_pwr_io_en, PCM_PWRIO_EN_R0 | PCM_PWRIO_EN_R7); + + printk(BIOS_DEBUG, "SPM: %s\n", __func__); + + /* check IM ready */ + while ((read32(&mtk_spm->pcm_fsm_sta) & IM_STATE_MASK) != IM_STATE) + ; + + /* kick PCM to run, and toggle PCM_KICK */ + con0 = read32(&mtk_spm->pcm_con0) & ~(IM_KICK_L_LSB | PCM_KICK_L_LSB); + write32(&mtk_spm->pcm_con0, con0 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | + PCM_KICK_L_LSB); + write32(&mtk_spm->pcm_con0, con0 | SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + + printk(BIOS_DEBUG, "SPM: %s done\n", __func__); +} + +int spm_init(void) +{ + struct pcm_desc *pcmdesc; + enum dyna_load_pcm_index index; + struct stopwatch sw; + + stopwatch_init(&sw); + + if (CONFIG(MT8183_DRAM_EMCP)) + index = DYNA_LOAD_PCM_SUSPEND_LP4_3733; + else + index = DYNA_LOAD_PCM_SUSPEND_LP4_3200; + + printk(BIOS_DEBUG, "SPM: pcm index = %d\n", index); + + struct dyna_load_pcm pcm; + if (spm_load_firmware(index, &pcm)) { + printk(BIOS_ERR, "SPM: firmware is not ready\n"); + printk(BIOS_ERR, "SPM: check dram type and firmware version\n"); + return -1; + } + + pcmdesc = &pcm.desc; + + if (spm_register_init()) + return -1; + + if (spm_reset_and_init_pcm(pcmdesc)) + return -1; + + spm_kick_im_to_fetch(&pcm); + spm_init_pcm_register(); + spm_init_event_vector(pcmdesc); + spm_kick_pcm_to_run(); + + printk(BIOS_INFO, "SPM: %s done in %ld msecs\n", __func__, + stopwatch_duration_msecs(&sw)); + + return 0; +} From cad708d210196690c2cc537004e556b075dc758c Mon Sep 17 00:00:00 2001 From: Paul Fagerburg Date: Wed, 25 Sep 2019 09:31:57 -0600 Subject: [PATCH 40/75] util/mb/google/hatch: fix style issues in shell script * Use all caps for variables. * Use a single exit code for failures. * No need to popd before exiting the script. * Do ${var,,} and ${var^^} into variables instead of using it everywhere. * Add more punctuation in comments. * Specify LC_ALL=C so that upper/lower case show the desired behavior. Signed-off-by: Paul Fagerburg Change-Id: I63aa0aa633f36b9543e809fc42fac955da5960a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35605 Tested-by: build bot (Jenkins) Reviewed-by: Andrew McRae Reviewed-by: Edward O'Callaghan --- .../google/hatch/create_coreboot_variant.sh | 52 +++++++++---------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/util/mainboard/google/hatch/create_coreboot_variant.sh b/util/mainboard/google/hatch/create_coreboot_variant.sh index d4256a6ccc..739c2f1ac0 100755 --- a/util/mainboard/google/hatch/create_coreboot_variant.sh +++ b/util/mainboard/google/hatch/create_coreboot_variant.sh @@ -13,6 +13,8 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. +export LC_ALL=C + if [[ "$#" -ne 1 ]]; then echo "Usage: $0 variant_name" echo "e.g. $0 kohaku" @@ -26,54 +28,52 @@ fi # you to specify the baseboard as one of the cmdline arguments. # # This is the name of the base board that we're cloning to make the variant. -base="hatch" -# This is the name of the variant that is being cloned -# ${var,,} converts to all lowercase -variant="${1,,}" +BASE="hatch" +# This is the name of the variant that is being cloned. +# ${var,,} converts to all lowercase; ${var^^} is all uppercase. +VARIANT="${1,,}" +VARIANT_UPPER="${VARIANT^^}" # This script and the templates live in util/mainboard/google/hatch # We need to create files in src/mainboard/google/hatch -pushd "${BASH_SOURCE%/*}" || exit +pushd "${BASH_SOURCE%/*}" || exit 1 SRC=$(pwd) -popd || exit -pushd "${SRC}/../../../../src/mainboard/google/${base}" || { - echo "The baseboard directory for ${base} does not exist."; - exit; } +popd || exit 1 +pushd "${SRC}/../../../../src/mainboard/google/${BASE}" || { + echo "The baseboard directory for ${BASE} does not exist."; + exit 1; } -# Make sure the variant doesn't already exist -if [[ -e variants/${variant} ]]; then - echo "variants/${variant} already exists." +# Make sure the variant doesn't already exist. +if [[ -e variants/${VARIANT} ]]; then + echo "variants/${VARIANT} already exists." echo "Have you already created this variant?" - popd || exit - exit 2 + exit 1 fi # Start a branch. Use YMD timestamp to avoid collisions. DATE=$(date +%Y%m%d) -git checkout -b "create_${variant}_${DATE}" +git checkout -b "create_${VARIANT}_${DATE}" || exit 1 -# Copy the template tree to the target -mkdir -p "variants/${variant}/" -cp -pr "${SRC}/template/." "variants/${variant}/" -git add "variants/${variant}/" +# Copy the template tree to the target. +mkdir -p "variants/${VARIANT}/" +cp -pr "${SRC}/template/." "variants/${VARIANT}/" +git add "variants/${VARIANT}/" # Now add the new variant to Kconfig and Kconfig.name # These files are in the current directory, e.g. src/mainboard/google/hatch -"${SRC}/kconfig.py" --name "${variant}" +"${SRC}/kconfig.py" --name "${VARIANT}" mv Kconfig.new Kconfig mv Kconfig.name.new Kconfig.name git add Kconfig Kconfig.name -# Now commit the files -git commit -sm "${base}: Create ${variant} variant +# Now commit the files. +git commit -sm "${BASE}: Create ${VARIANT} variant BUG=none -TEST=util/abuild/abuild -p none -t google/${base} -x -a -make sure the build includes GOOGLE_${variant^^}" - -popd || exit +TEST=util/abuild/abuild -p none -t google/${BASE} -x -a +make sure the build includes GOOGLE_${VARIANT_UPPER}" echo "Please check all the files (git show), make any changes you want," echo "and then push to coreboot HEAD:refs/for/master" From 39f3f52b3eb0fee0c9908e07d910270d05952c0d Mon Sep 17 00:00:00 2001 From: Paul Fagerburg Date: Wed, 25 Sep 2019 09:59:46 -0600 Subject: [PATCH 41/75] util/mb/google/hatch: script can take optional bug parameter When creating a new variant, adding a bug parameter after the name of the variant will populate the BUG= field in the commit message. If the parameter is not present, then BUG=None. Signed-off-by: Paul Fagerburg Change-Id: I3e08df5d80a5684c9f3675e3c0a8346240171cd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35606 Tested-by: build bot (Jenkins) Reviewed-by: Andrew McRae Reviewed-by: Edward O'Callaghan --- .../google/hatch/create_coreboot_variant.sh | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/util/mainboard/google/hatch/create_coreboot_variant.sh b/util/mainboard/google/hatch/create_coreboot_variant.sh index 739c2f1ac0..569143f795 100755 --- a/util/mainboard/google/hatch/create_coreboot_variant.sh +++ b/util/mainboard/google/hatch/create_coreboot_variant.sh @@ -15,9 +15,9 @@ export LC_ALL=C -if [[ "$#" -ne 1 ]]; then - echo "Usage: $0 variant_name" - echo "e.g. $0 kohaku" +if [[ "$#" -lt 1 ]]; then + echo "Usage: $0 variant_name [b:bug_number]" + echo "e.g. $0 kohaku b:140261109" echo "Adds a new variant of Hatch to Kconfig and Kconfig.name, creates the" echo "skeleton files for acpi, ec, and gpio, copies the makefile for" echo "SPD sources, and sets up a basic overridetree" @@ -34,6 +34,10 @@ BASE="hatch" VARIANT="${1,,}" VARIANT_UPPER="${VARIANT^^}" +# Assign text for the "BUG=" part of the commit, or use "None" if that +# parameter wasn't specified. +BUG=${2:-None} + # This script and the templates live in util/mainboard/google/hatch # We need to create files in src/mainboard/google/hatch pushd "${BASH_SOURCE%/*}" || exit 1 @@ -71,7 +75,7 @@ git add Kconfig Kconfig.name # Now commit the files. git commit -sm "${BASE}: Create ${VARIANT} variant -BUG=none +BUG=${BUG} TEST=util/abuild/abuild -p none -t google/${BASE} -x -a make sure the build includes GOOGLE_${VARIANT_UPPER}" From 4ab023329d9212342cf6f7cfa08fb388ac7f019b Mon Sep 17 00:00:00 2001 From: Paul Fagerburg Date: Wed, 25 Sep 2019 09:12:24 -0600 Subject: [PATCH 42/75] util/mb/google/hatch: update CRC calculation for correctness The CRC result is treated as a signed value, and so in certain situations, the calculated value for the last four digits will not be correct. Ensure that the CRC is treated as an unsigned 32-bit value prior to converting the last 4 decimal digits to a string. Signed-off-by: Paul Fagerburg Change-Id: I92f9ce1ceb7450f90b89c94e0ace6f79a9419b42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35604 Reviewed-by: Andrew McRae Reviewed-by: Edward O'Callaghan Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- util/mainboard/google/hatch/kconfig.py | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/util/mainboard/google/hatch/kconfig.py b/util/mainboard/google/hatch/kconfig.py index ecc24eeb49..891714b53e 100755 --- a/util/mainboard/google/hatch/kconfig.py +++ b/util/mainboard/google/hatch/kconfig.py @@ -64,8 +64,11 @@ def get_gbb_hwid(variant_name): converted to all uppercase as part of this function.""" hwid = variant_name + ' test' upperhwid = hwid.upper() - suffix = zlib.crc32(upperhwid.encode('UTF-8')) % 10000 - gbb_hwid = upperhwid + ' ' + str(suffix).zfill(4) + # Force conversion to unsigned by bitwise AND with (2^32)-1. + # See the docs for crc32 at https://docs.python.org/3/library/zlib.html + # for why '& 0xffffffff' is necessary. + crc = zlib.crc32(upperhwid.encode('UTF-8')) & 0xffffffff + gbb_hwid = upperhwid + ' ' + str(crc % 10000).zfill(4) return gbb_hwid From dde937cce30b92c1b507c7c294768e0691efd28f Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Mon, 9 Sep 2019 15:50:03 +0300 Subject: [PATCH 43/75] pci_ids: rename PCI_DEVICE_ID_INTEL_SKL_ID_H The new macro name contains the number of cores: PCI_DEVICE_ID_INTEL_SKL_ID_H_4 - 4 core PCI_DEVICE_ID_INTEL_SKL_ID_H_2 - 2 core Change-Id: I190181b213d55865aa577ae5baff179fef95afde Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/35302 Reviewed-by: Felix Singer Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/include/device/pci_ids.h | 2 +- src/soc/intel/common/block/systemagent/systemagent.c | 2 +- src/soc/intel/skylake/bootblock/report_platform.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 905618cb66..07589c8048 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3176,7 +3176,7 @@ #define PCI_DEVICE_ID_INTEL_SKL_ID_Y 0x190c #define PCI_DEVICE_ID_INTEL_SKL_ID_ULX 0x1924 #define PCI_DEVICE_ID_INTEL_SKL_ID_H_2 0x1900 -#define PCI_DEVICE_ID_INTEL_SKL_ID_H 0x1910 +#define PCI_DEVICE_ID_INTEL_SKL_ID_H_4 0x1910 #define PCI_DEVICE_ID_INTEL_SKL_ID_S_2 0x190f #define PCI_DEVICE_ID_INTEL_SKL_ID_S_4 0x191f #define PCI_DEVICE_ID_INTEL_KBL_ID_S 0x590f diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index b19b8ca64f..0312cac94e 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -340,7 +340,7 @@ static const unsigned short systemagent_ids[] = { PCI_DEVICE_ID_INTEL_SKL_ID_U, PCI_DEVICE_ID_INTEL_SKL_ID_Y, PCI_DEVICE_ID_INTEL_SKL_ID_ULX, - PCI_DEVICE_ID_INTEL_SKL_ID_H, + PCI_DEVICE_ID_INTEL_SKL_ID_H_4, PCI_DEVICE_ID_INTEL_SKL_ID_H_2, PCI_DEVICE_ID_INTEL_SKL_ID_S_2, PCI_DEVICE_ID_INTEL_SKL_ID_S_4, diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index fcfd874c8f..89dd1547c0 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -50,7 +50,7 @@ static struct { { PCI_DEVICE_ID_INTEL_SKL_ID_U, "Skylake-U" }, { PCI_DEVICE_ID_INTEL_SKL_ID_Y, "Skylake-Y" }, { PCI_DEVICE_ID_INTEL_SKL_ID_ULX, "Skylake-ULX" }, - { PCI_DEVICE_ID_INTEL_SKL_ID_H, "Skylake-H" }, + { PCI_DEVICE_ID_INTEL_SKL_ID_H_4, "Skylake-H (4 Core)" }, { PCI_DEVICE_ID_INTEL_SKL_ID_H_EM, "Skylake-H Embedded" }, { PCI_DEVICE_ID_INTEL_SKL_ID_H_2, "Skylake-H (2 Core)" }, { PCI_DEVICE_ID_INTEL_SKL_ID_S_2, "Skylake-S (2 Core)" }, From 9529530766ed6f1ed17c2af11d51deca9a2092d6 Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Mon, 23 Sep 2019 11:07:21 +0300 Subject: [PATCH 44/75] pci_ids: fix PCI ID for Intel Iris HALO GT4 iGPU According to the documentation [1], SKL-H Halo GT4E (Iris Pro Graphics P580) PCI ID should be 0x193B. [1] page 11-12, Intel(R) Open Source HD Graphics, Intel Iris(TM) Graphics, and Intel Iris(TM) Pro Graphics, Programmer's Reference Manual. Volume 4: Configurations. May 2016, Revision 1.0 Doc Ref # IHD-OS-SKL-Vol 4-05.16 Change-Id: Id62fe3ec26779d51b748efd271db565ade1e3ee0 Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/35536 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Rudolph --- src/include/device/pci_ids.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 07589c8048..e6b8b1879d 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3103,7 +3103,7 @@ #define PCI_DEVICE_ID_INTEL_SKL_GT2_SULTM 0x1916 #define PCI_DEVICE_ID_INTEL_SKL_GT2_SHALM 0x191B #define PCI_DEVICE_ID_INTEL_SKL_GT2_SWKSM 0x191D -#define PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM 0x193D +#define PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM 0x193B #define PCI_DEVICE_ID_INTEL_KBL_GT1_SULTM 0x5906 #define PCI_DEVICE_ID_INTEL_KBL_GT2_DT2P2 0x5912 #define PCI_DEVICE_ID_INTEL_KBL_GT2_SULXM 0x591E From 9734af669768203349485bd76a4ad3c79c8bdc73 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Wed, 1 Nov 2017 13:15:33 +0100 Subject: [PATCH 45/75] device/i2c_bus: Add i2c_dev_read_at16() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit i2c_dev_read_at16() sends a 16-bit offset to the I2C chip (for larger EEPROM parts), then reads bytes up to a given length into a buffer. Change-Id: I7516f3e5d9aca362c2b340aa5627d91510c09412 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/29478 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/device/i2c_bus.c | 37 ++++++++++++++++++++++++++++++++++++ src/include/device/i2c_bus.h | 8 ++++++++ 2 files changed, 45 insertions(+) diff --git a/src/device/i2c_bus.c b/src/device/i2c_bus.c index 30bb80ca98..93634d223b 100644 --- a/src/device/i2c_bus.c +++ b/src/device/i2c_bus.c @@ -16,6 +16,7 @@ #include #include #include +#include struct bus *i2c_link(struct device *const dev) { @@ -159,3 +160,39 @@ int i2c_dev_writeb_at(struct device *const dev, return -1; } } + +int i2c_dev_read_at16(struct device *const dev, + uint8_t *const buf, const size_t len, uint16_t off) +{ + struct device *const busdev = i2c_busdev(dev); + if (!busdev) + return -1; + + if (busdev->ops->ops_i2c_bus) { + const struct i2c_msg msg[] = { + { + .flags = 0, + .slave = dev->path.i2c.device, + .buf = (uint8_t *)&off, + .len = sizeof(off), + }, + { + .flags = I2C_M_RD, + .slave = dev->path.i2c.device, + .buf = buf, + .len = len, + }, + }; + + write_be16(&off, off); + const int ret = busdev->ops->ops_i2c_bus->transfer( + busdev, msg, ARRAY_SIZE(msg)); + if (ret) + return ret; + else + return len; + } else { + printk(BIOS_ERR, "%s Missing ops_i2c_bus->transfer", dev_path(busdev)); + return -1; + } +} diff --git a/src/include/device/i2c_bus.h b/src/include/device/i2c_bus.h index 6aa4f9ba9d..5302d20228 100644 --- a/src/include/device/i2c_bus.h +++ b/src/include/device/i2c_bus.h @@ -89,4 +89,12 @@ int i2c_dev_readb_at(struct device *, uint8_t off); */ int i2c_dev_writeb_at(struct device *, uint8_t off, uint8_t val); +/* + * Sends the 16-bit register offset `off` and reads `len` bytes into `buf`. + * + * Returns the number of bytes read on success, negative `enum cb_err` + * value on error. + */ +int i2c_dev_read_at16(struct device *, uint8_t *buf, size_t len, uint16_t off); + #endif /* _DEVICE_I2C_BUS_H_ */ From 5936ba43f3f41e5d67657cd0eab28b477e91ef39 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Thu, 19 Sep 2019 14:42:39 +0200 Subject: [PATCH 46/75] drivers/i2c/at24rf08c: Add proper Kconfig option MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The existing Kconfig code made SMBIOS_PROVIDED_BY_MOBO depend on VENDOR_LENOVO. Thus, it couldn't be selected by boards from other vendors. So we add another Kconfig that selects it here. NB. It's still unclear how the two drivers in this directory are related (at24rf08c and lenovo_serial). From the code, it doesn't look like the latter belongs here. Change-Id: Iaa5c5a584f2a5e2426352ec6aa681f99a55efa49 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/35472 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Kyösti Mälkki --- src/drivers/i2c/at24rf08c/Kconfig | 9 +++------ src/drivers/i2c/at24rf08c/Makefile.inc | 4 ++-- 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/src/drivers/i2c/at24rf08c/Kconfig b/src/drivers/i2c/at24rf08c/Kconfig index e8ee9863e9..8a5eb20bc5 100644 --- a/src/drivers/i2c/at24rf08c/Kconfig +++ b/src/drivers/i2c/at24rf08c/Kconfig @@ -1,7 +1,4 @@ -if VENDOR_LENOVO - -config SMBIOS_PROVIDED_BY_MOBO +config DRIVER_LENOVO_SERIALS bool - default y - -endif + default y if VENDOR_LENOVO + select SMBIOS_PROVIDED_BY_MOBO diff --git a/src/drivers/i2c/at24rf08c/Makefile.inc b/src/drivers/i2c/at24rf08c/Makefile.inc index 10c91d1764..985aa685a3 100644 --- a/src/drivers/i2c/at24rf08c/Makefile.inc +++ b/src/drivers/i2c/at24rf08c/Makefile.inc @@ -1,2 +1,2 @@ -ramstage-$(CONFIG_VENDOR_LENOVO) += at24rf08c.c -ramstage-$(CONFIG_VENDOR_LENOVO) += lenovo_serials.c +ramstage-$(CONFIG_DRIVER_LENOVO_SERIALS) += at24rf08c.c +ramstage-$(CONFIG_DRIVER_LENOVO_SERIALS) += lenovo_serials.c From 5fb34e87eb94294b37420493d6863983673fa4a0 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Thu, 19 Sep 2019 16:35:28 +0200 Subject: [PATCH 47/75] ec/kontron/kempld: Add fall-through comments where appropriate MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes related GCC warnings. Change-Id: I803fc0e005390ebd8a5e3ac6886ee968c56c3a34 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/35473 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/ec/kontron/kempld/kempld.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/ec/kontron/kempld/kempld.c b/src/ec/kontron/kempld/kempld.c index 19c18804c2..b87238b649 100644 --- a/src/ec/kontron/kempld/kempld.c +++ b/src/ec/kontron/kempld/kempld.c @@ -95,11 +95,13 @@ static void kempld_enable_dev(struct device *const dev) dev->ops = &kempld_uart_ops; break; } + /* Fall through. */ case 1: if (dev->path.generic.subid == 0) { kempld_i2c_device_init(dev); break; } + /* Fall through. */ default: printk(BIOS_WARNING, "KEMPLD: Spurious device %s.\n", From 9a940bf295337153728e69afdbfee8776170b7bb Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Mon, 20 May 2019 14:13:12 +0200 Subject: [PATCH 48/75] drivers/i2c/lm96000: Fix integer sign issue MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We accidentally converted an `int` return value to an `unsigned`, making it impossible to check for errors with `< 0`. Fix that by using an `int` variable. Change-Id: I5433c27e334bc177913e138df83118b128c674b7 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/35474 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/drivers/i2c/lm96000/lm96000.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/drivers/i2c/lm96000/lm96000.c b/src/drivers/i2c/lm96000/lm96000.c index 4bb2a4a8b4..4a3c2eba14 100644 --- a/src/drivers/i2c/lm96000/lm96000.c +++ b/src/drivers/i2c/lm96000/lm96000.c @@ -178,20 +178,21 @@ static void lm96000_configure_temp_zone(struct device *const dev, static void lm96000_init(struct device *const dev) { const struct drivers_i2c_lm96000_config *const config = dev->chip_info; - unsigned int i, lm_config; + unsigned int i; + int lm_config; struct stopwatch sw; printk(BIOS_DEBUG, "lm96000: Initialization hardware monitoring.\n"); stopwatch_init_msecs_expire(&sw, 1000); lm_config = lm96000_read(dev, LM96000_CONFIG); - while ((lm_config < 0 || !(lm_config & LM96000_READY))) { + while ((lm_config < 0 || !((unsigned int)lm_config & LM96000_READY))) { mdelay(1); lm_config = lm96000_read(dev, LM96000_CONFIG); if (stopwatch_expired(&sw)) break; } - if (lm_config < 0 || !(lm_config & LM96000_READY)) { + if (lm_config < 0 || !((unsigned int)lm_config & LM96000_READY)) { printk(BIOS_INFO, "lm96000: Not ready after 1s.\n"); return; } From b56fcfe9b5b49915c1ae00ac06421fca7a7e2308 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Tue, 6 Aug 2019 18:05:50 +0200 Subject: [PATCH 49/75] drivers/i2c/lm96000: Add more settings for fan control MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Allow to set a lower temperature limit, as the currently hard-coded 25C may be to low for a given temperature sensor. Also enable smoo- thing, currently hard-coded to the maximum interval of 35s, and set the hysteresis value. Change-Id: I5fde1cf909e8fbbaf8a345790b00c58a73c19ef8 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/35475 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/drivers/i2c/lm96000/chip.h | 8 ++++++-- src/drivers/i2c/lm96000/lm96000.c | 11 +++++++++-- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/src/drivers/i2c/lm96000/chip.h b/src/drivers/i2c/lm96000/chip.h index ab782dbbb5..cbf8601146 100644 --- a/src/drivers/i2c/lm96000/chip.h +++ b/src/drivers/i2c/lm96000/chip.h @@ -93,6 +93,7 @@ struct lm96000_fan_config { }; struct lm96000_temp_zone { + u8 low_temp; /* temperature for min. duty cycle (in °C) */ u8 target_temp; /* temperature for 100% duty cycle (in °C) */ u8 panic_temp; /* temperature for 100% duty cycle on all fans */ @@ -100,9 +101,12 @@ struct lm96000_temp_zone { with. (Datasheet clearly states the opposite, that this is tied to each PWM output so YMMV.) */ enum { - LM96000_LOW_TEMP_OFF = 0, /* turn fan off below low temp. */ - LM96000_LOW_TEMP_MIN = 1, /* keep PWM at mininum duty cycle */ + /* turn fan off below `low_temp - hysteresis` */ + LM96000_LOW_TEMP_OFF = 0, + /* keep PWM at mininum duty cycle */ + LM96000_LOW_TEMP_MIN = 1, } min_off; + u8 hysteresis; }; /* Implements only those parts currently used by coreboot mainboards. */ diff --git a/src/drivers/i2c/lm96000/lm96000.c b/src/drivers/i2c/lm96000/lm96000.c index 4a3c2eba14..7fbb31b4e5 100644 --- a/src/drivers/i2c/lm96000/lm96000.c +++ b/src/drivers/i2c/lm96000/lm96000.c @@ -156,9 +156,9 @@ static void lm96000_configure_temp_zone(struct device *const dev, { 2, 3, 3, 4, 5, 7, 8, 10, 13, 16, 20, 27, 32, 40, 53, 80 }; unsigned int i; - /* find longest range that starts from 25°C */ + /* find longest range that starts from `low_temp` */ for (i = ARRAY_SIZE(temp_range) - 1; i > 0; --i) { - if (temp_range[i] + 25 <= config->target_temp) + if (config->low_temp + temp_range[i] <= config->target_temp) break; } @@ -170,9 +170,16 @@ static void lm96000_configure_temp_zone(struct device *const dev, : 0); lm96000_write(dev, LM96000_ZONE_TEMP_PANIC(zone), config->panic_temp ? config->panic_temp : 100); + lm96000_update(dev, LM96000_ZONE_SMOOTH(zone), + LM96000_ZONE_SMOOTH_MASK(zone), + LM96000_ZONE_SMOOTH_EN(zone) | 0); /* 0: 35s */ lm96000_update(dev, LM96000_FAN_MIN_OFF, LM96000_FAN_MIN(zone), config->min_off ? LM96000_FAN_MIN(zone) : 0); + lm96000_update(dev, LM96000_ZONE_HYSTERESIS(zone), + LM96000_ZONE_HYST_MASK(zone), + config->hysteresis << LM96000_ZONE_HYST_SHIFT(zone) + & LM96000_ZONE_HYST_MASK(zone)); } static void lm96000_init(struct device *const dev) From d2186a3b3f5c092a97bd2b669a846f73441353d9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 26 Sep 2019 09:49:00 +0300 Subject: [PATCH 50/75] soc/intel/fsp_broadwell_de: Enable SSE and SSE2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Apparently romcc-bootblock just barely built without XMM registers. Change-Id: Ie7b1101f47c2dfb718bef99f8c05f9d575c821cd Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35617 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Werner Zeh --- src/soc/intel/fsp_broadwell_de/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index 94eff07bab..6c74a749a4 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -18,6 +18,7 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_MP select SMP select IOAPIC + select SSE2 select UDELAY_TSC select SUPPORT_CPU_UCODE_IN_CBFS select INTEL_DESCRIPTOR_MODE_CAPABLE From 7b2da05310c3cf65506946484134e8ed6400504d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 25 Sep 2019 13:41:04 +0300 Subject: [PATCH 51/75] arch/x86: Fix __ROMCC__ automatic prerequisities MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit While the list of prerequisities is not created with romcc, we need to simulate it since different set of header files will is used. Change-Id: Ib799c872b5280e2035126f9660e04e51acc4b1a8 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35601 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/arch/x86/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 554107f2fe..612424d5c8 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -161,7 +161,7 @@ $(objgenerated)/bootblock.ld: $$(filter-out $(call src-to-obj,bootblock,src/arch $(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(KCONFIG_AUTOHEADER) # The open quote in the subst messes with syntax highlighting. Fix it - ") @printf " ROMCC $(subst $(obj)/,,$(@))\n" - $(CC_bootblock) $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \ + $(CC_bootblock) -D__ROMCC__ -D__PRE_RAM__ -D__BOOTBLOCK__ $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \ $< > $(objgenerated)/bootblock.inc.d $(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@ From 0e1245e3d065287b3f731e92fa45811225462532 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Fri, 27 Sep 2019 12:05:59 +0530 Subject: [PATCH 52/75] mb/google/drallion: Configure LPSS controller parameters drallion uses below LPSS controllers: I2C: 0/1/4 GSPI: None UART: 0(Console) BUG=b:141575294 Change-Id: I9c57f8054f5da5add667168502ebc3e089c440f8 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/35638 Tested-by: build bot (Jenkins) Reviewed-by: Bora Guvendik --- .../drallion/variants/drallion/devicetree.cb | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 956e54edf9..2e8edd5b0e 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -13,6 +13,21 @@ chip soc/intel/cannonlake register "gen2_dec" = "0x00040941" # 0x940-0x947 register "gen3_dec" = "0x000c0951" # 0x950-0x95f + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + [PchSerialIoIndexSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + # FSP configuration register "SaGv" = "SaGv_Enabled" register "HeciEnabled" = "0" From ff5eb86aeb3e2129882120150132ba83dd1efea0 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Mon, 30 Sep 2019 08:26:00 +0530 Subject: [PATCH 53/75] mb/google/drallion: Clean up devicetree config * Disable SATA controller and related configs. * Disable PCIe root ports 10 and related configs. -> Board uses integrated CnVi for WLAN * Disable PCIe root ports 12 and related configs. -> Board uses WWAN intarfaced over USB Change-Id: If9d49cef290dcccb114afccc3ac34cd072802ea4 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/35723 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- .../drallion/variants/drallion/devicetree.cb | 21 +++---------------- 1 file changed, 3 insertions(+), 18 deletions(-) diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 2e8edd5b0e..db3f36bc8d 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -31,10 +31,6 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "SaGv_Enabled" register "HeciEnabled" = "0" - register "SataSalpSupport" = "1" - register "SataMode" = "Sata_AHCI" - register "SataPortsEnable[2]" = "1" - register "SataPortsDevSlp[2]" = "1" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "PchPmSlpS3MinAssert" = "3" # 50ms @@ -47,7 +43,6 @@ chip soc/intel/cannonlake register "psys_pmax" = "140" register "s0ix_enable" = "1" register "dptf_enable" = "1" - register "satapwroptimize" = "1" register "tdp_pl1_override" = "25" register "tdp_pl2_override" = "51" register "Device4Enable" = "1" @@ -202,16 +197,6 @@ chip soc/intel/cannonlake register "PcieClkSrcUsage[4]" = "8" register "PcieClkSrcClkReq[4]" = "4" - # PCIe port 10 for M.2 2230 WLAN - register "PcieRpEnable[9]" = "1" - register "PcieClkSrcUsage[1]" = "9" - register "PcieClkSrcClkReq[1]" = "1" - - # PCIe port 12 for M.2 3042 WWAN - register "PcieRpEnable[11]" = "1" - register "PcieClkSrcUsage[0]" = "11" - register "PcieClkSrcClkReq[0]" = "0" - # PCIe port 13 for M.2 2280 SSD register "PcieRpEnable[12]" = "1" register "PcieRpLtrEnable[12]" = "1" @@ -395,7 +380,7 @@ chip soc/intel/cannonlake device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on end # SATA + device pci 17.0 off end # SATA device pci 19.0 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" @@ -417,9 +402,9 @@ chip soc/intel/cannonlake device pci 1d.0 on smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" end # PCI Express Port 9 - device pci 1d.1 on end # PCI Express Port 10 + device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 on end # PCI Express Port 12 + device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" end # PCI Express Port 13 (x4) From ebf201b8f563ece11ceb60d81ba9cd676020da42 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 28 May 2019 13:51:36 +0200 Subject: [PATCH 54/75] sb/intel/bd82x6x: Use common final SPI OPs setup This also reworks the interface to override OPs from the devicetree to match the interface in sb/intel/common/spi. Change-Id: I534e989279d771ec4c0249af325bc3b30a661145 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/33040 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- .../sapphire/pureplatinumh61/devicetree.cb | 9 +++- src/southbridge/intel/bd82x6x/chip.h | 10 +--- src/southbridge/intel/bd82x6x/lpc.c | 46 ++++++++----------- src/southbridge/intel/bd82x6x/pch.h | 41 ----------------- 4 files changed, 29 insertions(+), 77 deletions(-) diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb index aff01302b2..b863c30851 100644 --- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -55,7 +55,14 @@ chip northbridge/intel/sandybridge register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" register "spi.opprefixes" = "{ 0x50, 0x06 }" - register "spi.ops" = "{ { 0, 1, 0x01 }, { 1, 1, 0x02 }, { 1, 0, 0x03 }, { 0, 0, 0x05 }, { 1, 1, 0x20 }, { 0, 0, 0x9f }, { 0, 1, 0xad }, { 0, 1, 0x04 } }" + register "spi.ops" = "{{0x01, WRITE_NO_ADDR}, + {0x02, WRITE_WITH_ADDR}, + {0x03, READ_WITH_ADDR}, + {0x05, READ_NO_ADDR}, + {0x20, WRITE_WITH_ADDR}, + {0x9f, READ_NO_ADDR}, + {0xad, WRITE_NO_ADDR}, + {0x04, WRITE_NO_ADDR}}" device pci 16.0 on # Management Engine Interface 1 subsystemid 0x174b 0x1007 end diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 4be91522d2..9f9c4455bb 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -16,6 +16,7 @@ #ifndef SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H #define SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H +#include #include struct southbridge_intel_bd82x6x_config { @@ -96,14 +97,7 @@ struct southbridge_intel_bd82x6x_config { uint32_t spi_uvscc; uint32_t spi_lvscc; - struct { - uint8_t opprefixes[2]; - struct { - uint8_t needs_address; - uint8_t is_write; - uint8_t op; - } ops[8]; - } spi; + struct intel_swseq_spi_config spi; }; #endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */ diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 592c70f8b4..b8df7aad10 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -39,6 +39,7 @@ #include #include #include +#include #define NMI_OFF 0 @@ -874,33 +875,7 @@ static void southbridge_fill_ssdt(struct device *device) static void lpc_final(struct device *dev) { - u16 spi_opprefix = SPI_OPPREFIX; - u16 spi_optype = SPI_OPTYPE; - u32 spi_opmenu[2] = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }; - - /* Configure SPI opcode menu; devicetree may override defaults. */ - const config_t *const config = dev->chip_info; - if (config && config->spi.ops[0].op) { - unsigned int i; - - spi_opprefix = 0; - spi_optype = 0; - spi_opmenu[0] = 0; - spi_opmenu[1] = 0; - for (i = 0; i < sizeof(spi_opprefix); ++i) - spi_opprefix |= config->spi.opprefixes[i] << i * 8; - for (i = 0; i < sizeof(spi_opmenu); ++i) { - spi_optype |= - config->spi.ops[i].is_write << 2 * i | - config->spi.ops[i].needs_address << (2 * i + 1); - spi_opmenu[i / 4] |= - config->spi.ops[i].op << (i % 4) * 8; - } - } - RCBA16(0x3894) = spi_opprefix; - RCBA16(0x3896) = spi_optype; - RCBA32(0x3898) = spi_opmenu[0]; - RCBA32(0x389c) = spi_opmenu[1]; + spi_finalize_ops(); /* Call SMM finalize() handlers before resume */ if (CONFIG(HAVE_SMI_HANDLER)) { @@ -911,6 +886,23 @@ static void lpc_final(struct device *dev) } } +void intel_southbridge_override_spi( + struct intel_swseq_spi_config *spi_config) +{ + struct device *dev = pcidev_on_root(0x1f, 0); + + if (!dev) + return; + /* Devicetree may override defaults. */ + const config_t *const config = dev->chip_info; + + if (!config) + return; + + if (config->spi.ops[0].op != 0) + memcpy(spi_config, &config->spi, sizeof(*spi_config)); +} + static struct pci_operations pci_ops = { .set_subsystem = pci_dev_set_subsystem, }; diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index fcb15ac99e..cb0691fea2 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -561,47 +561,6 @@ void early_usb_init(const struct southbridge_usb_port *portmap); #define TCO_LOCK (1 << 12) #define TCO2_CNT 0x6a -/* - * SPI Opcode Menu setup for SPIBAR lockdown - * should support most common flash chips. - */ - -#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ -#define SPI_OPTYPE_0 0x01 /* Write, no address */ - -#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ -#define SPI_OPTYPE_1 0x03 /* Write, address required */ - -#define SPI_OPMENU_2 0x03 /* READ: Read Data */ -#define SPI_OPTYPE_2 0x02 /* Read, address required */ - -#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ -#define SPI_OPTYPE_3 0x00 /* Read, no address */ - -#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ -#define SPI_OPTYPE_4 0x03 /* Write, address required */ - -#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ -#define SPI_OPTYPE_5 0x00 /* Read, no address */ - -#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ -#define SPI_OPTYPE_6 0x03 /* Write, address required */ - -#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ -#define SPI_OPTYPE_7 0x02 /* Read, address required */ - -#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ - (SPI_OPMENU_5 << 8) | SPI_OPMENU_4) -#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ - (SPI_OPMENU_1 << 8) | SPI_OPMENU_0) - -#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ - (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ - (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ - (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0)) - -#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ - #define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ #define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ #define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ From 50b4f78344e800bdfe9ef7d2b64331a24191e112 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 23 Sep 2019 11:49:17 +0200 Subject: [PATCH 55/75] sb/intel/spi: Use different SPIOPS for most SST flashes Many supported SST flashes use the AAI OP (0xad) to write. TESTED on Thinkpad X60 with SST25VF016B, flashrom can use AAI_WRITE op with locked down SPIOPS. Change-Id: Ica72eda04a8d9f4e563987871b1640565c6e7e12 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/35537 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/common/spi.c | 40 ++++++++++++++++++++++++------ 1 file changed, 32 insertions(+), 8 deletions(-) diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 268030b9c8..73181cfd54 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -1060,9 +1060,9 @@ void spi_finalize_ops(void) struct ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr); u16 spi_opprefix; u16 optype = 0; - struct intel_swseq_spi_config spi_config = { + struct intel_swseq_spi_config spi_config_default = { {0x06, 0x50}, /* OPPREFIXES: EWSR and WREN */ - { /* OPTYPE and OPCODE */ + { /* OPCODE and OPTYPE */ {0x01, WRITE_NO_ADDR}, /* WRSR: Write Status Register */ {0x02, WRITE_WITH_ADDR}, /* BYPR: Byte Program */ {0x03, READ_WITH_ADDR}, /* READ: Read Data */ @@ -1073,19 +1073,43 @@ void spi_finalize_ops(void) {0x0b, READ_WITH_ADDR}, /* FAST: Fast Read */ } }; + struct intel_swseq_spi_config spi_config_aai_write = { + {0x06, 0x50}, /* OPPREFIXES: EWSR and WREN */ + { /* OPCODE and OPTYPE */ + {0x01, WRITE_NO_ADDR}, /* WRSR: Write Status Register */ + {0x02, WRITE_WITH_ADDR}, /* BYPR: Byte Program */ + {0x03, READ_WITH_ADDR}, /* READ: Read Data */ + {0x05, READ_NO_ADDR}, /* RDSR: Read Status Register */ + {0x20, WRITE_WITH_ADDR}, /* SE20: Sector Erase 0x20 */ + {0x9f, READ_NO_ADDR}, /* RDID: Read ID */ + {0xad, WRITE_NO_ADDR}, /* Auto Address Increment Word Program */ + {0x04, WRITE_NO_ADDR} /* Write Disable */ + } + }; + const struct spi_flash *flash = boot_device_spi_flash(); + struct intel_swseq_spi_config *spi_config = &spi_config_default; int i; + /* + * Some older SST SPI flashes support AAI write but use 0xaf opcde for + * that. Flashrom uses the byte program opcode to write those flashes, + * so this configuration is fine too. SST25VF064C (id = 0x4b) is an + * exception. + */ + if (flash && flash->vendor == VENDOR_ID_SST && (flash->model & 0x00ff) != 0x4b) + spi_config = &spi_config_aai_write; + if (spi_locked()) return; - intel_southbridge_override_spi(&spi_config); + intel_southbridge_override_spi(spi_config); - spi_opprefix = spi_config.opprefixes[0] - | (spi_config.opprefixes[1] << 8); + spi_opprefix = spi_config->opprefixes[0] + | (spi_config->opprefixes[1] << 8); writew_(spi_opprefix, cntlr->preop); - for (i = 0; i < ARRAY_SIZE(spi_config.ops); i++) { - optype |= (spi_config.ops[i].type & 3) << (i * 2); - writeb_(spi_config.ops[i].op, &cntlr->opmenu[i]); + for (i = 0; i < ARRAY_SIZE(spi_config->ops); i++) { + optype |= (spi_config->ops[i].type & 3) << (i * 2); + writeb_(spi_config->ops[i].op, &cntlr->opmenu[i]); } writew_(optype, cntlr->optype); } From a0b366d550e720f2e086db20b5f7f7b07ccabc02 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 26 Sep 2019 22:33:51 +0300 Subject: [PATCH 56/75] device/pci_early: Drop some __SIMPLE_DEVICE__ use MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The simple PCI config accessors are always available under names pci_s_[read|write]_configX. We have some use for PCI bridge configurations and resets in romstages, so expose them. Change-Id: Ia97a4e1f1b4c80b3dae800d80615bdc118414ed3 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35672 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/device/pci_early.c | 73 ++++++++++++++++++++-------------------- src/include/device/pci.h | 6 ++-- 2 files changed, 40 insertions(+), 39 deletions(-) diff --git a/src/device/pci_early.c b/src/device/pci_early.c index 880480d280..b15f4a3370 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -11,64 +11,61 @@ * GNU General Public License for more details. */ -#define __SIMPLE_DEVICE__ - #include #include #include #include #include -static void pci_bridge_reset_secondary(pci_devfn_t p2p_bridge) +void pci_s_assert_secondary_reset(pci_devfn_t p2p_bridge) { u16 reg16; - - /* First we reset the secondary bus. */ - reg16 = pci_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL); - reg16 |= (1 << 6); /* SRESET */ - pci_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16); - - /* Assume we don't have to wait here forever */ - - /* Read back and clear reset bit. */ - reg16 = pci_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL); - reg16 &= ~(1 << 6); /* SRESET */ - pci_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16); + reg16 = pci_s_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL); + reg16 |= PCI_BRIDGE_CTL_BUS_RESET; + pci_s_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16); } -static void pci_bridge_set_secondary(pci_devfn_t p2p_bridge, u8 secondary) +void pci_s_deassert_secondary_reset(pci_devfn_t p2p_bridge) +{ + u16 reg16; + reg16 = pci_s_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL); + reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET; + pci_s_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16); +} + +void pci_s_bridge_set_secondary(pci_devfn_t p2p_bridge, u8 secondary) { /* Disable config transaction forwarding. */ - pci_write_config8(p2p_bridge, PCI_SECONDARY_BUS, 0x00); - pci_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, 0x00); + pci_s_write_config8(p2p_bridge, PCI_SECONDARY_BUS, 0x00); + pci_s_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, 0x00); /* Enable config transaction forwarding. */ - pci_write_config8(p2p_bridge, PCI_SECONDARY_BUS, secondary); - pci_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, secondary); + pci_s_write_config8(p2p_bridge, PCI_SECONDARY_BUS, secondary); + pci_s_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, secondary); } -static void pci_bridge_set_mmio(pci_devfn_t p2p_bridge, u32 base, u32 size) +static void pci_s_bridge_set_mmio(pci_devfn_t p2p_bridge, u32 base, u32 size) { u16 reg16; /* Disable MMIO window behind the bridge. */ - reg16 = pci_read_config16(p2p_bridge, PCI_COMMAND); + reg16 = pci_s_read_config16(p2p_bridge, PCI_COMMAND); reg16 &= ~PCI_COMMAND_MEMORY; - pci_write_config16(p2p_bridge, PCI_COMMAND, reg16); - pci_write_config32(p2p_bridge, PCI_MEMORY_BASE, 0x10); + pci_s_write_config16(p2p_bridge, PCI_COMMAND, reg16); + pci_s_write_config32(p2p_bridge, PCI_MEMORY_BASE, 0x10); if (!size) return; /* Enable MMIO window behind the bridge. */ - pci_write_config32(p2p_bridge, PCI_MEMORY_BASE, + pci_s_write_config32(p2p_bridge, PCI_MEMORY_BASE, ((base + size - 1) & 0xfff00000) | ((base >> 16) & 0xfff0)); - reg16 = pci_read_config16(p2p_bridge, PCI_COMMAND); + reg16 = pci_s_read_config16(p2p_bridge, PCI_COMMAND); reg16 |= PCI_COMMAND_MEMORY; - pci_write_config16(p2p_bridge, PCI_COMMAND, reg16); + pci_s_write_config16(p2p_bridge, PCI_COMMAND, reg16); } -void pci_early_mmio_window(pci_devfn_t p2p_bridge, u32 mmio_base, u32 mmio_size) +static void pci_s_early_mmio_window(pci_devfn_t p2p_bridge, u32 mmio_base, u32 mmio_size) { int timeout, ret = -1; @@ -79,12 +76,14 @@ void pci_early_mmio_window(pci_devfn_t p2p_bridge, u32 mmio_base, u32 mmio_size) u8 dev = 0; /* Enable configuration and MMIO over bridge. */ - pci_bridge_reset_secondary(p2p_bridge); - pci_bridge_set_secondary(p2p_bridge, secondary); - pci_bridge_set_mmio(p2p_bridge, mmio_base, mmio_size); + pci_s_assert_secondary_reset(p2p_bridge); + pci_s_deassert_secondary_reset(p2p_bridge); + pci_s_bridge_set_secondary(p2p_bridge, secondary); + pci_s_bridge_set_mmio(p2p_bridge, mmio_base, mmio_size); for (timeout = 20000; timeout; timeout--) { - u32 id = pci_read_config32(PCI_DEV(secondary, dev, 0), PCI_VENDOR_ID); + pci_devfn_t dbg_dev = PCI_DEV(secondary, dev, 0); + u32 id = pci_s_read_config32(dbg_dev, PCI_VENDOR_ID); if (id != 0 && id != 0xffffffff && id != 0xffff0001) break; udelay(10); @@ -95,13 +94,13 @@ void pci_early_mmio_window(pci_devfn_t p2p_bridge, u32 mmio_base, u32 mmio_size) /* Disable MMIO window if we found no suitable device. */ if (ret) - pci_bridge_set_mmio(p2p_bridge, 0, 0); + pci_s_bridge_set_mmio(p2p_bridge, 0, 0); /* Resource allocator will reconfigure bridges and secondary bus * number may change. Thus early device cannot reliably use config * transactions from here on, so we may as well disable them. */ - pci_bridge_set_secondary(p2p_bridge, 0); + pci_s_bridge_set_secondary(p2p_bridge, 0); } void pci_early_bridge_init(void) @@ -112,7 +111,7 @@ void pci_early_bridge_init(void) pci_devfn_t p2p_bridge = PCI_DEV(0, CONFIG_EARLY_PCI_BRIDGE_DEVICE, CONFIG_EARLY_PCI_BRIDGE_FUNCTION); - pci_early_mmio_window(p2p_bridge, CONFIG_EARLY_PCI_MMIO_BASE, 0x4000); + pci_s_early_mmio_window(p2p_bridge, CONFIG_EARLY_PCI_MMIO_BASE, 0x4000); } /* FIXME: A lot of issues using the following, please avoid. @@ -123,7 +122,7 @@ pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev) { for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) { unsigned int id; - id = pci_read_config32(dev, 0); + id = pci_s_read_config32(dev, 0); if (id == pci_id) return dev; } @@ -139,7 +138,7 @@ pci_devfn_t pci_locate_device_on_bus(unsigned int pci_id, unsigned int bus) for (; dev <= last; dev += PCI_DEV(0, 0, 1)) { unsigned int id; - id = pci_read_config32(dev, 0); + id = pci_s_read_config32(dev, 0); if (id == pci_id) return dev; } diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 8d6a9ae520..f091105438 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -116,8 +116,10 @@ struct msix_entry *pci_msix_get_table(struct device *dev); pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev); pci_devfn_t pci_locate_device_on_bus(unsigned int pci_id, unsigned int bus); -void pci_early_mmio_window(pci_devfn_t p2p_bridge, u32 mmio_base, - u32 mmio_size); +void pci_s_assert_secondary_reset(pci_devfn_t p2p_bridge); +void pci_s_deassert_secondary_reset(pci_devfn_t p2p_bridge); +void pci_s_bridge_set_secondary(pci_devfn_t p2p_bridge, u8 secondary); + int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base); static inline int pci_base_address_is_memory_space(unsigned int attr) From a84a7340b6291e209db2d5a3a28507816eec2223 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 23 Sep 2019 10:01:16 +0300 Subject: [PATCH 57/75] sb/intel/bd8x62x,i82801gx: Fix PCI bridge subsystem IDs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implementation of ich_pci_dev_enable_resources() used to have a custom implementation to program PCI subsystem IDs for the (legacy) PCI bus bridge. With the local implementation removed, we no longer need the custom .enable_resources callback. Change-Id: I6f73fd0e4d5a1829d1555455c9a143f1d18a6116 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35673 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Petr Cvek --- src/southbridge/intel/bd82x6x/pci.c | 30 +--------------------------- src/southbridge/intel/i82801gx/pci.c | 30 +--------------------------- 2 files changed, 2 insertions(+), 58 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c index 6391de409c..a222893d88 100644 --- a/src/southbridge/intel/bd82x6x/pci.c +++ b/src/southbridge/intel/bd82x6x/pci.c @@ -57,34 +57,6 @@ static void pci_init(struct device *dev) pci_write_config16(dev, SECSTS, reg16); } -static void ich_pci_dev_enable_resources(struct device *dev) -{ - uint16_t command; - - command = pci_read_config16(dev, PCI_COMMAND); - command |= dev->command; - printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command); - pci_write_config16(dev, PCI_COMMAND, command); -} - -static void ich_pci_bus_enable_resources(struct device *dev) -{ - uint16_t ctrl; - /* enable IO in command register if there is VGA card - * connected with (even it does not claim IO resource) - */ - if (dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA) - dev->command |= PCI_COMMAND_IO; - ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL); - ctrl |= dev->link_list->bridge_ctrl; - ctrl |= (PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR); /* error check */ - printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); - pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); - - /* This is the reason we need our own pci_bus_enable_resources */ - ich_pci_dev_enable_resources(dev); -} - static struct pci_operations pci_ops = { .set_subsystem = pci_dev_set_subsystem, }; @@ -92,7 +64,7 @@ static struct pci_operations pci_ops = { static struct device_operations device_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = ich_pci_bus_enable_resources, + .enable_resources = pci_bus_enable_resources, .init = pci_init, .scan_bus = pci_scan_bridge, .ops_pci = &pci_ops, diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c index 1d1f902727..4d98e8939a 100644 --- a/src/southbridge/intel/i82801gx/pci.c +++ b/src/southbridge/intel/i82801gx/pci.c @@ -56,34 +56,6 @@ static void pci_init(struct device *dev) pci_write_config16(dev, SECSTS, reg16); } -static void ich_pci_dev_enable_resources(struct device *dev) -{ - uint16_t command; - - command = pci_read_config16(dev, PCI_COMMAND); - command |= dev->command; - printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command); - pci_write_config16(dev, PCI_COMMAND, command); -} - -static void ich_pci_bus_enable_resources(struct device *dev) -{ - uint16_t ctrl; - /* enable IO in command register if there is VGA card - * connected with (even it does not claim IO resource) - */ - if (dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA) - dev->command |= PCI_COMMAND_IO; - ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL); - ctrl |= dev->link_list->bridge_ctrl; - ctrl |= (PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR); /* error check */ - printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); - pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); - - /* This is the reason we need our own pci_bus_enable_resources */ - ich_pci_dev_enable_resources(dev); -} - static struct pci_operations pci_ops = { .set_subsystem = pci_dev_set_subsystem, }; @@ -91,7 +63,7 @@ static struct pci_operations pci_ops = { static struct device_operations device_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, - .enable_resources = ich_pci_bus_enable_resources, + .enable_resources = pci_bus_enable_resources, .init = pci_init, .scan_bus = pci_scan_bridge, .ops_pci = &pci_ops, From df128a55b183d3d7a6d7ae986f33abffac50f371 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 21 Sep 2019 18:35:37 +0300 Subject: [PATCH 58/75] intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is a PCI standard register, no need to alias its definitions under different names. Change-Id: Iea6b198dd70fe1e49b5dc0824dba62628dedc69a Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35521 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/kontron/986lcd-m/romstage.c | 4 +- src/mainboard/roda/rk886ex/romstage.c | 4 +- src/northbridge/intel/haswell/haswell.h | 4 -- src/northbridge/intel/i945/early_init.c | 41 +++++++++---------- src/northbridge/intel/i945/i945.h | 1 - src/northbridge/intel/nehalem/nehalem.h | 4 -- src/northbridge/intel/pineview/pineview.h | 1 - .../intel/sandybridge/sandybridge.h | 4 -- src/soc/intel/broadwell/pcie.c | 8 ++-- src/soc/intel/common/block/pcie/pcie.c | 3 +- src/southbridge/intel/bd82x6x/pch.h | 4 -- src/southbridge/intel/bd82x6x/pci.c | 9 ++-- src/southbridge/intel/bd82x6x/pcie.c | 10 ++--- src/southbridge/intel/i82801gx/i82801gx.h | 4 -- src/southbridge/intel/i82801gx/pci.c | 9 ++-- src/southbridge/intel/i82801gx/pcie.c | 10 ++--- src/southbridge/intel/i82801ix/pcie.c | 9 ++-- src/southbridge/intel/i82801jx/pcie.c | 9 ++-- src/southbridge/intel/ibexpeak/pch.h | 4 -- src/southbridge/intel/lynxpoint/pch.h | 4 -- src/southbridge/intel/lynxpoint/pcie.c | 10 ++--- 21 files changed, 65 insertions(+), 91 deletions(-) diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index bbaad83089..cee7c2a603 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -247,9 +247,9 @@ void mainboard_romstage_entry(void) enable_lapic(); /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); + pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_BUS_RESET); udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); + pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, 0); ich7_enable_lpc(); early_superio_config_w83627thg(); diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 30ebf4431d..93b24a0a47 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -210,9 +210,9 @@ void mainboard_romstage_entry(void) enable_lapic(); /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); + pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_BUS_RESET); udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); + pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, 0); ich7_enable_lpc(); early_superio_config(); diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 9de0cfb2c3..bd89609601 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -108,10 +108,6 @@ #define GLBIOTLBINV (1 << 1) #define GLBCTXTINV (1 << 0) -/* Device 0:1.0 PCI configuration space (PCI Express) */ - -#define BCTRL1 0x3e /* 16bit */ - /* Device 0:2.0 PCI configuration space (Graphics Device) */ diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index f9167dfc97..ebff49c6ad 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -546,13 +546,13 @@ static void i945_setup_pci_express_x16(void) */ /* First we reset the secondary bus */ - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); - reg16 |= (1 << 6); /* SRESET */ - pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); + reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL); + reg16 |= PCI_BRIDGE_CTL_BUS_RESET; + pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16); /* Read back and clear reset bit. */ - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); - reg16 &= ~(1 << 6); /* SRESET */ - pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); + reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL); + reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET; /* SRESET */ + pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16); reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), SLOTSTS); printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16); @@ -610,12 +610,11 @@ static void i945_setup_pci_express_x16(void) reg32 |= 1; pci_write_config32(PCI_DEV(0, 0x01, 0), PEGSTS, reg32); - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); - - reg16 |= (1 << 6); - pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); - reg16 &= ~(1 << 6); - pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); + reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL); + reg16 |= PCI_BRIDGE_CTL_BUS_RESET; + pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16); + reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET; + pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16); printk(BIOS_DEBUG, "PCIe link training ..."); timeout = 0x7ffff; @@ -663,9 +662,9 @@ static void i945_setup_pci_express_x16(void) pci_write_config32(PCI_DEV(0, 0x0, 0), DEVEN, reg32); /* Set VGA enable bit in PCIe bridge */ - reg16 = pci_read_config16(PCI_DEV(0, 0x1, 0), BCTRL1); - reg16 |= (1 << 3); - pci_write_config16(PCI_DEV(0, 0x1, 0), BCTRL1, reg16); + reg16 = pci_read_config16(PCI_DEV(0, 0x1, 0), PCI_BRIDGE_CONTROL); + reg16 |= PCI_BRIDGE_CTL_VGA; + pci_write_config16(PCI_DEV(0, 0x1, 0), PCI_BRIDGE_CONTROL, reg16); } /* Enable GPEs */ @@ -776,17 +775,17 @@ disable_pciexpress_x16_link: MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0); - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); - reg16 |= (1 << 6); - pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); + reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL); + reg16 |= PCI_BRIDGE_CTL_BUS_RESET; + pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16); reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x224); reg32 |= (1 << 8); pci_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32); - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), BCTRL1); - reg16 &= ~(1 << 6); - pci_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16); + reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL); + reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET; + pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16); printk(BIOS_DEBUG, "Wait for link to enter detect state... "); timeout = 0x7fffff; diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index ebcc8bcb19..d19748eaf9 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -86,7 +86,6 @@ #define SBUSN1 0x19 /* 8bit */ #define SUBUSN1 0x1a /* 8bit */ #define SSTS1 0x1e /* 16bit */ -#define BCTRL1 0x3e /* 16bit */ #define PEG_CAP 0xa2 /* 16bit */ #define DSTS 0xaa /* 16bit */ #define SLOTCAP 0xb4 /* 32bit */ diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index 93024f69d8..21c2a395fe 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -153,10 +153,6 @@ typedef struct { #define SKPAD 0xdc /* Scratchpad Data */ -/* Device 0:1.0 PCI configuration space (PCI Express) */ - -#define BCTRL1 0x3e /* 16bit */ - /* Device 0:2.0 PCI configuration space (Graphics Device) */ diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index f53ff17aa3..882f886b21 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -84,7 +84,6 @@ /* Device 0:1.0 PCI configuration space (PCI Express) */ -#define BCTRL1 0x3e /* 16bit */ #define PEGSTS 0x214 /* 32bit */ /* Device 0:2.0 PCI configuration space (Graphics Device) */ diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index b598c9b6e9..d505728a3b 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -101,10 +101,6 @@ enum platform_type { #define SKPAD 0xdc /* Scratchpad Data */ -/* Device 0:1.0 PCI configuration space (PCI Express) */ - -#define BCTRL1 0x3e /* 16bit */ - /* Device 0:2.0 PCI configuration space (Graphics Device) */ diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index bdaced2edd..36523411c3 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -604,10 +604,10 @@ static void pch_pcie_init(struct device *dev) /* Set Cache Line Size to 0x10 */ pci_write_config8(dev, 0x0c, 0x10); - reg16 = pci_read_config16(dev, 0x3e); - reg16 &= ~(1 << 0); /* disable parity error response */ - reg16 |= (1 << 2); /* ISA enable */ - pci_write_config16(dev, 0x3e, reg16); + reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); + reg16 &= ~PCI_BRIDGE_CTL_PARITY; + reg16 |= PCI_BRIDGE_CTL_NO_ISA; + pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); #ifdef EVEN_MORE_DEBUG reg32 = pci_read_config32(dev, 0x20); diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index 94fa63122e..c8ca4f4d87 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -38,7 +38,8 @@ static void pch_pcie_init(struct device *dev) pci_write_config8(dev, PCI_CACHE_LINE_SIZE, CACHE_LINE_SIZE); /* disable parity error response, enable ISA */ - pci_update_config16(dev, PCI_BRIDGE_CONTROL, ~1, 1<<2); + pci_update_config16(dev, PCI_BRIDGE_CONTROL, + ~PCI_BRIDGE_CTL_PARITY, PCI_BRIDGE_CTL_NO_ISA); if (CONFIG(PCIE_DEBUG_INFO)) { printk(BIOS_SPEW, " MBL = 0x%08x\n", diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index cb0691fea2..22b91073ce 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -101,10 +101,6 @@ void early_usb_init(const struct southbridge_usb_port *portmap); #define SMLT 0x1b #define SECSTS 0x1e #define INTR 0x3c -#define BCTRL 0x3e -#define SBR (1 << 6) -#define SEE (1 << 1) -#define PERE (1 << 0) #define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0) #define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0) diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c index a222893d88..833512a5b7 100644 --- a/src/southbridge/intel/bd82x6x/pci.c +++ b/src/southbridge/intel/bd82x6x/pci.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include "pch.h" @@ -36,10 +37,10 @@ static void pci_init(struct device *dev) pci_write_config8(dev, INTR, 0xff); /* disable parity error response and SERR */ - reg16 = pci_read_config16(dev, BCTRL); - reg16 &= ~(1 << 0); - reg16 &= ~(1 << 1); - pci_write_config16(dev, BCTRL, reg16); + reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); + reg16 &= ~PCI_BRIDGE_CTL_PARITY; + reg16 &= ~PCI_BRIDGE_CTL_SERR; + pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); /* Master Latency Count must be set to 0x04! */ reg8 = pci_read_config8(dev, SMLT); diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 686930d80a..739f6ce8a8 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -232,11 +233,10 @@ static void pci_init(struct device *dev) // This has no effect but the OS might expect it pci_write_config8(dev, 0x0c, 0x10); - reg16 = pci_read_config16(dev, 0x3e); - reg16 &= ~(1 << 0); /* disable parity error response */ - // reg16 &= ~(1 << 1); /* disable SERR */ - reg16 |= (1 << 2); /* ISA enable */ - pci_write_config16(dev, 0x3e, reg16); + reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); + reg16 &= ~PCI_BRIDGE_CTL_PARITY; + reg16 |= PCI_BRIDGE_CTL_NO_ISA; + pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); #ifdef EVEN_MORE_DEBUG reg32 = pci_read_config32(dev, 0x20); diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 7fc0114aac..d615b403ac 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -59,10 +59,6 @@ int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, #define SMLT 0x1b #define SECSTS 0x1e #define INTR 0x3c -#define BCTRL 0x3e -#define SBR (1 << 6) -#define SEE (1 << 1) -#define PERE (1 << 0) #define ICH_PCIE_DEV_SLOT 28 diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c index 4d98e8939a..d493b790a7 100644 --- a/src/southbridge/intel/i82801gx/pci.c +++ b/src/southbridge/intel/i82801gx/pci.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include "i82801gx.h" @@ -35,10 +36,10 @@ static void pci_init(struct device *dev) pci_write_config8(dev, INTR, 0xff); /* disable parity error response and SERR */ - reg16 = pci_read_config16(dev, BCTRL); - reg16 &= ~(1 << 0); - reg16 &= ~(1 << 1); - pci_write_config16(dev, BCTRL, reg16); + reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); + reg16 &= ~PCI_BRIDGE_CTL_PARITY; + reg16 &= ~PCI_BRIDGE_CTL_SERR; + pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); /* Master Latency Count must be set to 0x04! */ reg8 = pci_read_config8(dev, SMLT); diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index 0946a9aadf..0d8b474d9b 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include "chip.h" @@ -67,11 +68,10 @@ static void pci_init(struct device *dev) // This has no effect but the OS might expect it pci_write_config8(dev, 0x0c, 0x10); - reg16 = pci_read_config16(dev, 0x3e); - reg16 &= ~(1 << 0); /* disable parity error response */ - // reg16 &= ~(1 << 1); /* disable SERR */ - reg16 |= (1 << 2); /* ISA enable */ - pci_write_config16(dev, 0x3e, reg16); + reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); + reg16 &= ~PCI_BRIDGE_CTL_PARITY; + reg16 |= PCI_BRIDGE_CTL_NO_ISA; + pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); /* Enable IO xAPIC on this PCIe port */ reg32 = pci_read_config32(dev, 0xd8); diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c index 3b90ce6471..b1d0ecc214 100644 --- a/src/southbridge/intel/i82801ix/pcie.c +++ b/src/southbridge/intel/i82801ix/pcie.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -41,10 +42,10 @@ static void pci_init(struct device *dev) // This has no effect but the OS might expect it pci_write_config8(dev, 0x0c, 0x10); - reg16 = pci_read_config16(dev, 0x3e); - reg16 &= ~(1 << 0); /* disable parity error response */ - reg16 |= (1 << 2); /* ISA enable */ - pci_write_config16(dev, 0x3e, reg16); + reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); + reg16 &= ~PCI_BRIDGE_CTL_PARITY; + reg16 |= PCI_BRIDGE_CTL_NO_ISA; + pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); /* Enable IO xAPIC on this PCIe port */ reg32 = pci_read_config32(dev, 0xd8); diff --git a/src/southbridge/intel/i82801jx/pcie.c b/src/southbridge/intel/i82801jx/pcie.c index 84b2b6a3fa..64da5a734b 100644 --- a/src/southbridge/intel/i82801jx/pcie.c +++ b/src/southbridge/intel/i82801jx/pcie.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -41,10 +42,10 @@ static void pci_init(struct device *dev) // This has no effect but the OS might expect it pci_write_config8(dev, 0x0c, 0x10); - reg16 = pci_read_config16(dev, 0x3e); - reg16 &= ~(1 << 0); /* disable parity error response */ - reg16 |= (1 << 2); /* ISA enable */ - pci_write_config16(dev, 0x3e, reg16); + reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); + reg16 &= ~PCI_BRIDGE_CTL_PARITY; + reg16 |= PCI_BRIDGE_CTL_NO_ISA; + pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); /* Enable IO xAPIC on this PCIe port */ reg32 = pci_read_config32(dev, 0xd8); diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index e7cc9d2c7c..f7b29291db 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -82,10 +82,6 @@ void pch_enable(struct device *dev); #define SMLT 0x1b #define SECSTS 0x1e #define INTR 0x3c -#define BCTRL 0x3e -#define SBR (1 << 6) -#define SEE (1 << 1) -#define PERE (1 << 0) #define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0) #define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0) diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 3f37887567..be4285b1da 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -195,10 +195,6 @@ void mainboard_config_superio(void); #define SMLT 0x1b #define SECSTS 0x1e #define INTR 0x3c -#define BCTRL 0x3e -#define SBR (1 << 6) -#define SEE (1 << 1) -#define PERE (1 << 0) /* Power Management Control and Status */ #define PCH_PCS 0x84 diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index a3b2e096d8..1eb8e4bcc4 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -684,11 +685,10 @@ static void pci_init(struct device *dev) // This has no effect but the OS might expect it pci_write_config8(dev, 0x0c, 0x10); - reg16 = pci_read_config16(dev, 0x3e); - reg16 &= ~(1 << 0); /* disable parity error response */ - // reg16 &= ~(1 << 1); /* disable SERR */ - reg16 |= (1 << 2); /* ISA enable */ - pci_write_config16(dev, 0x3e, reg16); + reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); + reg16 &= ~PCI_BRIDGE_CTL_PARITY; + reg16 |= PCI_BRIDGE_CTL_NO_ISA; + pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); #ifdef EVEN_MORE_DEBUG reg32 = pci_read_config32(dev, 0x20); From 444d2af9a9b99244967dba978325f2d3bc4dfeb1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 29 Sep 2019 07:03:31 +0300 Subject: [PATCH 59/75] intel/i945: Define p2peg for PCIe x16 slot MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I0e9dd06376c1076be4a4c41ff87dfd3cf820d7bc Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35675 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/i945/early_init.c | 162 ++++++++++++------------ 1 file changed, 82 insertions(+), 80 deletions(-) diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index ebff49c6ad..791baecc6a 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -529,6 +529,7 @@ static void i945_setup_pci_express_x16(void) u32 timeout; u32 reg32; u16 reg16; + pci_devfn_t p2peg = PCI_DEV(0, 0x01, 0); printk(BIOS_DEBUG, "Enabling PCI Express x16 Link\n"); @@ -536,9 +537,9 @@ static void i945_setup_pci_express_x16(void) reg16 |= DEVEN_D1F0; pci_write_config16(PCI_DEV(0, 0x00, 0), DEVEN, reg16); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEGCC); + reg32 = pci_read_config32(p2peg, PEGCC); reg32 &= ~(1 << 8); - pci_write_config32(PCI_DEV(0, 0x01, 0), PEGCC, reg32); + pci_write_config32(p2peg, PEGCC, reg32); /* We have no success with querying the usual PCIe registers * for link setup success on the i945. Hence we assign a temporary @@ -546,53 +547,53 @@ static void i945_setup_pci_express_x16(void) */ /* First we reset the secondary bus */ - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL); + reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); reg16 |= PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16); + pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); /* Read back and clear reset bit. */ - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL); + reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET; /* SRESET */ - pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16); + pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), SLOTSTS); + reg16 = pci_read_config16(p2peg, SLOTSTS); printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16); if (!(reg16 & 0x48)) goto disable_pciexpress_x16_link; reg16 |= (1 << 4) | (1 << 0); - pci_write_config16(PCI_DEV(0, 0x01, 0), SLOTSTS, reg16); + pci_write_config16(p2peg, SLOTSTS, reg16); - pci_write_config8(PCI_DEV(0, 0x01, 0), SBUSN1, 0x00); - pci_write_config8(PCI_DEV(0, 0x01, 0), SUBUSN1, 0x00); - pci_write_config8(PCI_DEV(0, 0x01, 0), SBUSN1, 0x0a); - pci_write_config8(PCI_DEV(0, 0x01, 0), SUBUSN1, 0x0a); + pci_write_config8(p2peg, SBUSN1, 0x00); + pci_write_config8(p2peg, SUBUSN1, 0x00); + pci_write_config8(p2peg, SBUSN1, 0x0a); + pci_write_config8(p2peg, SUBUSN1, 0x0a); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x224); + reg32 = pci_read_config32(p2peg, 0x224); reg32 &= ~(1 << 8); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32); + pci_write_config32(p2peg, 0x224, reg32); MCHBAR16(UPMC1) &= ~((1 << 5) | (1 << 0)); /* Initialize PEG_CAP */ - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PEG_CAP); + reg16 = pci_read_config16(p2peg, PEG_CAP); reg16 |= (1 << 8); - pci_write_config16(PCI_DEV(0, 0x01, 0), PEG_CAP, reg16); + pci_write_config16(p2peg, PEG_CAP, reg16); /* Setup SLOTCAP */ /* TODO: These values are mainboard dependent and should * be set from devicetree.cb. */ /* NOTE: SLOTCAP becomes RO after the first write! */ - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), SLOTCAP); + reg32 = pci_read_config32(p2peg, SLOTCAP); reg32 &= 0x0007ffff; reg32 &= 0xfffe007f; - pci_write_config32(PCI_DEV(0, 0x01, 0), SLOTCAP, reg32); + pci_write_config32(p2peg, SLOTCAP, reg32); /* Wait for training to succeed */ printk(BIOS_DEBUG, "PCIe link training ..."); timeout = 0x7ffff; - while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3) + while ((((pci_read_config32(p2peg, PEGSTS) >> 16) & 3) != 3) && --timeout) ; @@ -605,20 +606,20 @@ static void i945_setup_pci_express_x16(void) printk(BIOS_DEBUG, "Restrain PCIe port to x1\n"); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS); + reg32 = pci_read_config32(p2peg, PEGSTS); reg32 &= ~(0xf << 1); reg32 |= 1; - pci_write_config32(PCI_DEV(0, 0x01, 0), PEGSTS, reg32); + pci_write_config32(p2peg, PEGSTS, reg32); - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL); + reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); reg16 |= PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16); + pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16); + pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); printk(BIOS_DEBUG, "PCIe link training ..."); timeout = 0x7ffff; - while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3) + while ((((pci_read_config32(p2peg, PEGSTS) >> 16) & 3) != 3) && --timeout) ; @@ -633,22 +634,22 @@ static void i945_setup_pci_express_x16(void) } } - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xb2); + reg16 = pci_read_config16(p2peg, 0xb2); reg16 >>= 4; reg16 &= 0x3f; /* reg16 == 1 -> x1; reg16 == 16 -> x16 */ printk(BIOS_DEBUG, "PCIe x%d link training succeeded.\n", reg16); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEGTC); + reg32 = pci_read_config32(p2peg, PEGTC); reg32 &= 0xfffffc00; /* clear [9:0] */ if (reg16 == 1) reg32 |= 0x32b; // TODO - /* pci_write_config32(PCI_DEV(0, 0x01, 0), PEGTC, reg32); */ + /* pci_write_config32(p2peg, PEGTC, reg32); */ else if (reg16 == 16) reg32 |= 0x0f4; // TODO - /* pci_write_config32(PCI_DEV(0, 0x01, 0), PEGTC, reg32); */ + /* pci_write_config32(p2peg, PEGTC, reg32); */ reg32 = (pci_read_config32(PCI_DEV(0xa, 0, 0), 0x8) >> 8); printk(BIOS_DEBUG, "PCIe device class: %06x\n", reg32); @@ -662,84 +663,84 @@ static void i945_setup_pci_express_x16(void) pci_write_config32(PCI_DEV(0, 0x0, 0), DEVEN, reg32); /* Set VGA enable bit in PCIe bridge */ - reg16 = pci_read_config16(PCI_DEV(0, 0x1, 0), PCI_BRIDGE_CONTROL); + reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); reg16 |= PCI_BRIDGE_CTL_VGA; - pci_write_config16(PCI_DEV(0, 0x1, 0), PCI_BRIDGE_CONTROL, reg16); + pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); } /* Enable GPEs */ - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEG_LC); + reg32 = pci_read_config32(p2peg, PEG_LC); reg32 |= (1 << 2) | (1 << 1) | (1 << 0); /* PMEGPE, HPGPE, GENGPE */ - pci_write_config32(PCI_DEV(0, 0x01, 0), PEG_LC, reg32); + pci_write_config32(p2peg, PEG_LC, reg32); /* Virtual Channel Configuration: Only VC0 on PCIe x16 */ - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), VC0RCTL); + reg32 = pci_read_config32(p2peg, VC0RCTL); reg32 &= 0xffffff01; - pci_write_config32(PCI_DEV(0, 0x01, 0), VC0RCTL, reg32); + pci_write_config32(p2peg, VC0RCTL, reg32); /* Extended VC count */ - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PVCCAP1); + reg32 = pci_read_config32(p2peg, PVCCAP1); reg32 &= ~(7 << 0); - pci_write_config32(PCI_DEV(0, 0x01, 0), PVCCAP1, reg32); + pci_write_config32(p2peg, PVCCAP1, reg32); /* Active State Power Management ASPM */ /* TODO */ /* Clear error bits */ - pci_write_config16(PCI_DEV(0, 0x01, 0), PCISTS1, 0xffff); - pci_write_config16(PCI_DEV(0, 0x01, 0), SSTS1, 0xffff); - pci_write_config16(PCI_DEV(0, 0x01, 0), DSTS, 0xffff); - pci_write_config32(PCI_DEV(0, 0x01, 0), UESTS, 0xffffffff); - pci_write_config32(PCI_DEV(0, 0x01, 0), CESTS, 0xffffffff); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0x1f0, 0xffffffff); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0x228, 0xffffffff); + pci_write_config16(p2peg, PCISTS1, 0xffff); + pci_write_config16(p2peg, SSTS1, 0xffff); + pci_write_config16(p2peg, DSTS, 0xffff); + pci_write_config32(p2peg, UESTS, 0xffffffff); + pci_write_config32(p2peg, CESTS, 0xffffffff); + pci_write_config32(p2peg, 0x1f0, 0xffffffff); + pci_write_config32(p2peg, 0x228, 0xffffffff); /* Program R/WO registers */ - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x308); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0x308, reg32); + reg32 = pci_read_config32(p2peg, 0x308); + pci_write_config32(p2peg, 0x308, reg32); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x314); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0x314, reg32); + reg32 = pci_read_config32(p2peg, 0x314); + pci_write_config32(p2peg, 0x314, reg32); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x324); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0x324, reg32); + reg32 = pci_read_config32(p2peg, 0x324); + pci_write_config32(p2peg, 0x324, reg32); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x328); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0x328, reg32); + reg32 = pci_read_config32(p2peg, 0x328); + pci_write_config32(p2peg, 0x328, reg32); /* Additional PCIe graphics setup */ - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); + reg32 = pci_read_config32(p2peg, 0xf0); reg32 |= (3 << 26); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32); + pci_write_config32(p2peg, 0xf0, reg32); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); + reg32 = pci_read_config32(p2peg, 0xf0); reg32 |= (3 << 24); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32); + pci_write_config32(p2peg, 0xf0, reg32); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xf0); + reg32 = pci_read_config32(p2peg, 0xf0); reg32 |= (1 << 5); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0xf0, reg32); + pci_write_config32(p2peg, 0xf0, reg32); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x200); + reg32 = pci_read_config32(p2peg, 0x200); reg32 &= ~(3 << 26); reg32 |= (2 << 26); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0x200, reg32); + pci_write_config32(p2peg, 0x200, reg32); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xe80); + reg32 = pci_read_config32(p2peg, 0xe80); if (i945_silicon_revision() >= 2) reg32 |= (1 << 12); else reg32 &= ~(1 << 12); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32); + pci_write_config32(p2peg, 0xe80, reg32); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xeb4); + reg32 = pci_read_config32(p2peg, 0xeb4); reg32 &= ~(1 << 31); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0xeb4, reg32); + pci_write_config32(p2peg, 0xeb4, reg32); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xfc); + reg32 = pci_read_config32(p2peg, 0xfc); reg32 |= (1 << 31); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0xfc, reg32); + pci_write_config32(p2peg, 0xfc, reg32); if (i945_silicon_revision() >= 3) { static const u32 reglist[] = { @@ -750,21 +751,21 @@ static void i945_setup_pci_express_x16(void) int i; for (i = 0; i < ARRAY_SIZE(reglist); i++) { - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), reglist[i]); + reg32 = pci_read_config32(p2peg, reglist[i]); reg32 &= 0x0fffffff; reg32 |= (2 << 28); - pci_write_config32(PCI_DEV(0, 0x01, 0), reglist[i], reg32); + pci_write_config32(p2peg, reglist[i], reg32); } } if (i945_silicon_revision() <= 2) { /* Set voltage specific parameters */ - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xe80); + reg32 = pci_read_config32(p2peg, 0xe80); reg32 &= (0xf << 4); /* Default case 1.05V */ if ((MCHBAR32(DFT_STRAP1) & (1 << 20)) == 0) { /* 1.50V */ reg32 |= (7 << 4); } - pci_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32); + pci_write_config32(p2peg, 0xe80, reg32); } return; @@ -775,21 +776,21 @@ disable_pciexpress_x16_link: MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0); - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL); + reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); reg16 |= PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16); + pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x224); + reg32 = pci_read_config32(p2peg, 0x224); reg32 |= (1 << 8); - pci_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32); + pci_write_config32(p2peg, 0x224, reg32); - reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL); + reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(PCI_DEV(0, 0x01, 0), PCI_BRIDGE_CONTROL, reg16); + pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); printk(BIOS_DEBUG, "Wait for link to enter detect state... "); timeout = 0x7fffff; - for (reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS); + for (reg32 = pci_read_config32(p2peg, PEGSTS); (reg32 & 0x000f0000) && --timeout;) ; if (!timeout) @@ -806,6 +807,7 @@ disable_pciexpress_x16_link: static void i945_setup_root_complex_topology(void) { u32 reg32; + pci_devfn_t p2peg = PCI_DEV(0, 0x01, 0); printk(BIOS_DEBUG, "Setting up Root Complex Topology\n"); /* Egress Port Root Topology */ @@ -840,10 +842,10 @@ static void i945_setup_root_complex_topology(void) /* PCI Express x16 Port Root Topology */ if (pci_read_config8(PCI_DEV(0, 0x00, 0), DEVEN) & DEVEN_D1F0) { - pci_write_config32(PCI_DEV(0, 0x01, 0), LE1A, DEFAULT_EPBAR); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), LE1D); + pci_write_config32(p2peg, LE1A, DEFAULT_EPBAR); + reg32 = pci_read_config32(p2peg, LE1D); reg32 |= (1 << 0); - pci_write_config32(PCI_DEV(0, 0x01, 0), LE1D, reg32); + pci_write_config32(p2peg, LE1D, reg32); } } From 9137cbd5e4bc7040282ce9eb6fb75e8f251bcffa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 29 Sep 2019 07:03:37 +0300 Subject: [PATCH 60/75] intel/i945: Delay bridge VGA IO enable to ramstage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ifc54ecc96b6d9d79d5a16b2d7baeae70b59275c9 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35676 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/i945/early_init.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 791baecc6a..c53577b40d 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -661,11 +661,6 @@ static void i945_setup_pci_express_x16(void) reg32 = pci_read_config32(PCI_DEV(0, 0x0, 0), DEVEN); reg32 &= ~(DEVEN_D2F0 | DEVEN_D2F1); pci_write_config32(PCI_DEV(0, 0x0, 0), DEVEN, reg32); - - /* Set VGA enable bit in PCIe bridge */ - reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); - reg16 |= PCI_BRIDGE_CTL_VGA; - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); } /* Enable GPEs */ From 2647b6f9baffcad8bf52b591b2dc3f40a2ba7243 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 29 Sep 2019 07:03:55 +0300 Subject: [PATCH 61/75] intel/i945: Define peg_plugin for potential add-on PCIe card MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I06f6a7ed7a1ce935d154b8c7b11dcb81608329b9 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35677 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/i945/early_init.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index c53577b40d..d6d37d9083 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -531,6 +531,9 @@ static void i945_setup_pci_express_x16(void) u16 reg16; pci_devfn_t p2peg = PCI_DEV(0, 0x01, 0); + u8 tmp_secondary = 0x0a; + pci_devfn_t peg_plugin = PCI_DEV(tmp_secondary, 0, 0); + printk(BIOS_DEBUG, "Enabling PCI Express x16 Link\n"); reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN); @@ -562,10 +565,10 @@ static void i945_setup_pci_express_x16(void) reg16 |= (1 << 4) | (1 << 0); pci_write_config16(p2peg, SLOTSTS, reg16); - pci_write_config8(p2peg, SBUSN1, 0x00); - pci_write_config8(p2peg, SUBUSN1, 0x00); - pci_write_config8(p2peg, SBUSN1, 0x0a); - pci_write_config8(p2peg, SUBUSN1, 0x0a); + pci_write_config8(p2peg, PCI_SECONDARY_BUS, 0x00); + pci_write_config8(p2peg, PCI_SUBORDINATE_BUS, 0x00); + pci_write_config8(p2peg, PCI_SECONDARY_BUS, tmp_secondary); + pci_write_config8(p2peg, PCI_SUBORDINATE_BUS, tmp_secondary); reg32 = pci_read_config32(p2peg, 0x224); reg32 &= ~(1 << 8); @@ -597,7 +600,7 @@ static void i945_setup_pci_express_x16(void) && --timeout) ; - reg32 = pci_read_config32(PCI_DEV(0x0a, 0x0, 0), 0); + reg32 = pci_read_config32(peg_plugin, PCI_VENDOR_ID); if (reg32 != 0x00000000 && reg32 != 0xffffffff) { printk(BIOS_DEBUG, " Detected PCIe device %04x:%04x\n", reg32 & 0xffff, reg32 >> 16); @@ -623,7 +626,7 @@ static void i945_setup_pci_express_x16(void) && --timeout) ; - reg32 = pci_read_config32(PCI_DEV(0xa, 0x00, 0), 0); + reg32 = pci_read_config32(peg_plugin, PCI_VENDOR_ID); if (reg32 != 0x00000000 && reg32 != 0xffffffff) { printk(BIOS_DEBUG, " Detected PCIe x1 device %04x:%04x\n", reg32 & 0xffff, reg32 >> 16); @@ -651,7 +654,7 @@ static void i945_setup_pci_express_x16(void) // TODO /* pci_write_config32(p2peg, PEGTC, reg32); */ - reg32 = (pci_read_config32(PCI_DEV(0xa, 0, 0), 0x8) >> 8); + reg32 = (pci_read_config32(peg_plugin, 0x8) >> 8); printk(BIOS_DEBUG, "PCIe device class: %06x\n", reg32); if (reg32 == 0x030000) { printk(BIOS_DEBUG, "PCIe device is VGA. Disabling IGD.\n"); From 5adbc767f66224e617b6c8204a868542b8010999 Mon Sep 17 00:00:00 2001 From: Petr Cvek Date: Sun, 29 Sep 2019 01:26:12 +0200 Subject: [PATCH 62/75] mb/kontron/986lcd-m: Add gameport base allocation workaround A missing definition of gameport base (PNP io 0x60) will cause an automatic address assignment during PCI/PNP enumeration, which won't obey limit 0x7ff. This will cause the enumeration to fail as other devices already have the values enabled. The symptoms are: not working USB, PS/2, garbled UART console, not working PCIe GPUs and crashes. Probably because of wrongly assigned IO ports. Example of log (shortened): Done reading resources. Setting resources... !! Resource didn't fit !! aligned base 1000 size 1000 limit 2e7 1fff needs to be <= 2e7 (limit) PCI: 00:1c.0 1c * [0x0 - 0xfff] io !! Resource didn't fit !! aligned base 1000 size 1000 limit 2e7 1fff needs to be <= 2e7 (limit) PCI: 00:1c.1 1c * [0x1000 - 0x1fff] io !! Resource didn't fit !! aligned base 1000 size 1000 limit 2e7 1fff needs to be <= 2e7 (limit) PCI: 00:1c.2 1c * [0x2000 - 0x2fff] io !! Resource didn't fit !! aligned base 400 size 10 limit 2e7 40f needs to be <= 2e7 (limit) PCI: 00:1f.2 20 * [0x3080 - 0x308f] io !! Resource didn't fit !! ... ERROR: PCI: 00:02.0 14 io size: 0x0000000008 not assigned ... ERROR: PCI: 00:1f.2 10 io size: 0x0000000008 not assigned ERROR: PCI: 00:1f.2 14 io size: 0x0000000004 not assigned ERROR: PCI: 00:1f.2 18 io size: 0x0000000008 not assigned ERROR: PCI: 00:1f.2 1c io size: 0x0000000004 not assigned ERROR: PCI: 00:1f.2 20 io size: 0x0000000010 not assigned ... PCI: 00:1b.0 subsystem <- 8086/27d8 PCI: 00:1b.0 cmd <- 102 PCI: 00:1c.0 bridge ctrl <- 0003 PCI: 00:1c.0 subsystem <- 8086/27d0 PCI: 00:1c.0 cmd <- 107 PCI: 00:1c.1 brids70c01mcu0PeC: 0 dV0i8s0immicrocode: upd10a00000y0025 x666600CPU physiaB 0 0 e k MTRR cheaeu60zeAttemfWaiting for 1st Sot AP: slot 1 apic_L0ecl0zsax a aInitiNntt kac:oIG0 Ua dUrSGSGL Ct0C07fintel_vga_int15_h VGA Option ROM wa7..Azalia0Azalia: codkAbCiPCI: 00:1c.0 init finished We can see the ports probably started to collide after the activation of 00:1c.0 device. A debug run with compiled SPEW shows the problem with enumeration: PCI: 00:1f.1 18 * [0x50b8 - 0x50bf] io PCI: 00:1f.2 10 * [0x50c0 - 0x50c7] io PCI: 00:1f.2 18 * [0x50c8 - 0x50cf] io PCI: 00:1f.1 14 * [0x50d0 - 0x50d3] io PCI: 00:1f.1 1c * [0x50d4 - 0x50d7] io PCI: 00:1f.2 14 * [0x50d8 - 0x50db] io PCI: 00:1f.2 1c * [0x50dc - 0x50df] io PNP: 002e.7 60 * [0x50e0 - 0x50e0] io <-- gameport base DOMAIN: 0000 io: base: 50e1 size: 40e1 align: 12 gran: 0 limit: 7ff done Notice a weird base for DOMAIN, along with the limit. Adding a definition of gameport (0x220) as a workaround fixes the problems. The gameport should be still disabled thanks to disable bits (W83627THF datasheet is little bit chaotic). I didn't find any info if the gameport is available on some pads of the motherboard. Signed-off-by: Petr Cvek Change-Id: Ie8e42552ac5e638e91e5c290655edcce1f64e408 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35671 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Paul Menzel --- src/mainboard/kontron/986lcd-m/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb index 5db7551d12..e2c0d88a0a 100644 --- a/src/mainboard/kontron/986lcd-m/devicetree.cb +++ b/src/mainboard/kontron/986lcd-m/devicetree.cb @@ -79,6 +79,7 @@ chip northbridge/intel/i945 irq 0xf0 = 0x82 # HW accel A20. end device pnp 2e.7 on # GPIO1, GAME, MIDI + io 0x60 = 0x220 # allocator workaround io 0x62 = 0x330 irq 0x70 = 9 end From 6e079dc120a4aa95a25cfe536d4b1acd178918fd Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 26 Sep 2019 10:26:49 +0200 Subject: [PATCH 63/75] cpu/intel/common: Move intel_ht_sibling() to common folder Make intel_ht_sibling() available on all platforms. Will be used in MP init to only write "Core" MSRs from one thread on HyperThreading enabled platforms, to prevent race conditions and resulting #GP if MSRs are written twice or are already locked. Change-Id: I5d000b34ba4c6536dc866fbaf106b78e905e3e35 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/35619 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/arch/x86/include/arch/cpu.h | 1 + src/cpu/intel/Makefile.inc | 2 + src/cpu/intel/common/Kconfig | 3 ++ src/cpu/intel/common/Makefile.inc | 3 +- src/cpu/intel/common/common.h | 7 +++ src/cpu/intel/common/hyperthreading.c | 45 ++++++++++++++++++++ src/cpu/intel/fsp_model_406dx/Makefile.inc | 1 - src/cpu/intel/haswell/Makefile.inc | 1 - src/cpu/intel/hyperthreading/intel_sibling.c | 24 ----------- src/cpu/intel/model_1067x/Makefile.inc | 1 - src/cpu/intel/model_106cx/Makefile.inc | 1 - src/cpu/intel/model_2065x/Makefile.inc | 1 - src/cpu/intel/model_206ax/Makefile.inc | 1 - src/cpu/intel/model_f2x/Kconfig | 2 + src/cpu/intel/model_f2x/model_f2x_init.c | 1 + src/cpu/intel/model_f3x/Kconfig | 2 + src/cpu/intel/model_f3x/model_f3x_init.c | 1 + src/include/cpu/intel/hyperthreading.h | 1 - 18 files changed, 66 insertions(+), 32 deletions(-) create mode 100644 src/cpu/intel/common/hyperthreading.c diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index ffa532b47e..b82473621d 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -158,6 +158,7 @@ static inline unsigned int cpuid_edx(unsigned int op) #define CPUID_FEATURE_PAE (1 << 6) #define CPUID_FEATURE_PSE36 (1 << 17) +#define CPUID_FEAURE_HTT (1 << 28) // Intel leaf 0x4, AMD leaf 0x8000001d EAX diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 3f897407cf..484e241312 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -16,3 +16,5 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_RANGELEY) += fsp_model_406dx subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775 + +subdirs-y += common diff --git a/src/cpu/intel/common/Kconfig b/src/cpu/intel/common/Kconfig index 4074d8cc66..4fa3affb55 100644 --- a/src/cpu/intel/common/Kconfig +++ b/src/cpu/intel/common/Kconfig @@ -22,4 +22,7 @@ config SET_IA32_FC_LOCK_BIT config CPU_INTEL_COMMON_TIMEBASE bool +config CPU_INTEL_COMMON_HYPERTHREADING + bool + endif diff --git a/src/cpu/intel/common/Makefile.inc b/src/cpu/intel/common/Makefile.inc index c38e81c380..161201244c 100644 --- a/src/cpu/intel/common/Makefile.inc +++ b/src/cpu/intel/common/Makefile.inc @@ -1,4 +1,5 @@ -ramstage-y += common_init.c +ramstage-$(CONFIG_CPU_INTEL_COMMON) += common_init.c +ramstage-$(CONFIG_CPU_INTEL_COMMON_HYPERTHREADING) += hyperthreading.c ifeq ($(CONFIG_CPU_INTEL_COMMON_TIMEBASE),y) bootblock-y += fsb.c diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h index b9ac0566c6..f6b8e57ffd 100644 --- a/src/cpu/intel/common/common.h +++ b/src/cpu/intel/common/common.h @@ -15,6 +15,8 @@ #ifndef _CPU_INTEL_COMMON_H #define _CPU_INTEL_COMMON_H +#include + void set_vmx_and_lock(void); void set_feature_ctrl_vmx(void); void set_feature_ctrl_lock(void); @@ -27,4 +29,9 @@ void set_feature_ctrl_lock(void); struct cppc_config; void cpu_init_cppc_config(struct cppc_config *config, u32 version); +/* + * Returns true if it's not thread 0 on a hyperthreading enabled core. + */ +bool intel_ht_sibling(void); + #endif diff --git a/src/cpu/intel/common/hyperthreading.c b/src/cpu/intel/common/hyperthreading.c new file mode 100644 index 0000000000..4caf49e5b6 --- /dev/null +++ b/src/cpu/intel/common/hyperthreading.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +/* + * Return true if running thread does not have the smallest lapic ID + * within a CPU core. + */ +bool intel_ht_sibling(void) +{ + struct cpuid_result result; + unsigned int core_ids, apic_ids, threads; + + /* Is Hyper-Threading supported */ + if (!(cpuid_edx(1) & CPUID_FEAURE_HTT)) + return false; + + apic_ids = 1; + if (cpuid_eax(0) >= 1) + apic_ids = (cpuid_ebx(1) >> 16) & 0xff; + if (apic_ids == 0) + apic_ids = 1; + + core_ids = 1; + if (cpuid_eax(0) >= 4) { + result = cpuid_ext(4, 0); + core_ids += (result.eax >> 26) & 0x3f; + } + + threads = (apic_ids / core_ids); + return !!(lapicid() & (threads - 1)); +} diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc index d7fb4a886c..a3ebe3da06 100644 --- a/src/cpu/intel/fsp_model_406dx/Makefile.inc +++ b/src/cpu/intel/fsp_model_406dx/Makefile.inc @@ -13,7 +13,6 @@ ramstage-y += model_406dx_init.c subdirs-y += ../../x86/name -subdirs-y += ../common subdirs-y += ../../x86/tsc subdirs-y += ../../x86/mtrr diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 7661a4e2d8..aebeed497a 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -21,7 +21,6 @@ subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../turbo -subdirs-y += ../common cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3c-*) cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-45-*) diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index 3c3e53a839..f5bcc87a10 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -25,30 +25,6 @@ static int first_time = 1; static int disable_siblings = !CONFIG(LOGICAL_CPUS); -/* Return true if running thread does not have the smallest lapic ID - * within a CPU core. - */ -int intel_ht_sibling(void) -{ - unsigned int core_ids, apic_ids, threads; - - apic_ids = 1; - if (cpuid_eax(0) >= 1) - apic_ids = (cpuid_ebx(1) >> 16) & 0xff; - if (apic_ids < 1) - apic_ids = 1; - - core_ids = 1; - if (cpuid_eax(0) >= 4) { - struct cpuid_result result; - result = cpuid_ext(4, 0); - core_ids += (result.eax >> 26) & 0x3f; - } - - threads = (apic_ids / core_ids); - return !!(lapicid() & (threads-1)); -} - void intel_sibling_init(struct device *cpu) { unsigned int i, siblings; diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc index 743e780a36..545f04de72 100644 --- a/src/cpu/intel/model_1067x/Makefile.inc +++ b/src/cpu/intel/model_1067x/Makefile.inc @@ -1,7 +1,6 @@ ramstage-y += model_1067x_init.c ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c subdirs-y += ../../x86/name -subdirs-y += ../common subdirs-y += ../smm/gen1 cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-17-*) diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc index 6701e6fc18..6d8414ec16 100644 --- a/src/cpu/intel/model_106cx/Makefile.inc +++ b/src/cpu/intel/model_106cx/Makefile.inc @@ -1,6 +1,5 @@ ramstage-y += model_106cx_init.c subdirs-y += ../../x86/name -subdirs-y += ../common subdirs-y += ../smm/gen1 ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index 4f6d3c2fd8..dde4234521 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -8,7 +8,6 @@ subdirs-y += ../../intel/turbo subdirs-y += ../../intel/microcode subdirs-y += ../../x86/smm subdirs-y += ../smm/gen1 -subdirs-y += ../common ramstage-y += acpi.c diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index d19d860304..391d126e77 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -1,7 +1,6 @@ ramstage-y += model_206ax_init.c subdirs-y += ../../x86/name subdirs-y += ../smm/gen1 -subdirs-y += ../common subdirs-y += ../../x86/tsc subdirs-y += ../../x86/mtrr diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig index 9e70775650..dcf94415d0 100644 --- a/src/cpu/intel/model_f2x/Kconfig +++ b/src/cpu/intel/model_f2x/Kconfig @@ -7,3 +7,5 @@ config CPU_INTEL_MODEL_F2X select SMP select SUPPORT_CPU_UCODE_IN_CBFS select SMM_ASEG + select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_HYPERTHREADING diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index e759a43dc0..04710a9e68 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -17,6 +17,7 @@ #include #include #include +#include #include static void model_f2x_init(struct device *cpu) diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig index 7eaa820772..9a5e2a1caf 100644 --- a/src/cpu/intel/model_f3x/Kconfig +++ b/src/cpu/intel/model_f3x/Kconfig @@ -6,3 +6,5 @@ config CPU_INTEL_MODEL_F3X select ARCH_RAMSTAGE_X86_32 select SMP select SUPPORT_CPU_UCODE_IN_CBFS + select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_HYPERTHREADING diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index d348df6c82..48e3872225 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -17,6 +17,7 @@ #include #include #include +#include #include static void model_f3x_init(struct device *cpu) diff --git a/src/include/cpu/intel/hyperthreading.h b/src/include/cpu/intel/hyperthreading.h index c84a6a7a4a..0a1461ceb5 100644 --- a/src/include/cpu/intel/hyperthreading.h +++ b/src/include/cpu/intel/hyperthreading.h @@ -3,6 +3,5 @@ struct device; void intel_sibling_init(struct device *cpu); -int intel_ht_sibling(void); #endif /* CPU_INTEL_HYPERTHREADING_H */ From 9168ab0077a15d09c5a313359fa5391b29558dd4 Mon Sep 17 00:00:00 2001 From: Hsin-Hsiung Wang Date: Thu, 29 Aug 2019 14:56:25 +0800 Subject: [PATCH 64/75] mediatek/mt8183: Allow modifying vcore voltage Because vcore is the power of ddrphy in the soc, DRAM DVFS needs to be calibrated with different vcore voltages to get correct parameters. A new API is added to allow changing vcore voltage. BUG=b:80501386 BRANCH=none TEST=measure vcore voltage with multimeter Change-Id: Ic43d5efe7e597121775dc853a3e2a08ebc59657d Signed-off-by: Hsin-Hsiung Wang Reviewed-on: https://review.coreboot.org/c/coreboot/+/33391 Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8183/include/soc/mt6358.h | 5 +++++ src/soc/mediatek/mt8183/mt6358.c | 21 ++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/src/soc/mediatek/mt8183/include/soc/mt6358.h b/src/soc/mediatek/mt8183/include/soc/mt6358.h index 19ab5e106e..bb5f019433 100644 --- a/src/soc/mediatek/mt8183/include/soc/mt6358.h +++ b/src/soc/mediatek/mt8183/include/soc/mt6358.h @@ -25,6 +25,9 @@ enum { PMIC_TOP_TMA_KEY = 0x03a8, PMIC_PWRHOLD = 0x0a08, PMIC_CPSDSA4 = 0x0a2e, + PMIC_VCORE_OP_EN = 0x1490, + PMIC_VCORE_DBG0 = 0x149e, + PMIC_VCORE_VOSEL = 0x14aa, PMIC_VDRAM1_VOSEL_SLEEP = 0x160a, PMIC_SMPS_ANA_CON0 = 0x1808, PMIC_VSIM2_ANA_CON0 = 0x1e30, @@ -41,5 +44,7 @@ void mt6358_init(void); void pmic_set_power_hold(bool enable); void pmic_set_vsim2_cali(unsigned int vsim2_mv); void pmic_init_scp_voltage(void); +unsigned int pmic_get_vcore_vol(void); +void pmic_set_vcore_vol(unsigned int vcore_uv); #endif /* __SOC_MEDIATEK_MT6358_H__ */ diff --git a/src/soc/mediatek/mt8183/mt6358.c b/src/soc/mediatek/mt8183/mt6358.c index fa928cbcf6..3600b6a3de 100644 --- a/src/soc/mediatek/mt8183/mt6358.c +++ b/src/soc/mediatek/mt8183/mt6358.c @@ -805,6 +805,27 @@ void pmic_set_vsim2_cali(unsigned int vsim2_mv) pwrap_write_field(PMIC_VSIM2_ANA_CON0, cali_mv / 10, 0xF, 0); } +unsigned int pmic_get_vcore_vol(void) +{ + unsigned int vol_reg; + + vol_reg = pwrap_read_field(PMIC_VCORE_DBG0, 0x7F, 0); + return 500000 + vol_reg * 6250; +} + +void pmic_set_vcore_vol(unsigned int vcore_uv) +{ + unsigned int vol_reg; + + assert(vcore_uv >= 500000); + assert(vcore_uv <= 1100000); + + vol_reg = (vcore_uv - 500000) / 6250; + + pwrap_write_field(PMIC_VCORE_OP_EN, 1, 0x7F, 0); + pwrap_write_field(PMIC_VCORE_VOSEL, vol_reg, 0x7F, 0); +} + static void pmic_wdt_set(void) { /* [5]=1, RG_WDTRSTB_DEB */ From 6453c9062bea3e72d4f0f547cdf869567c2c9a70 Mon Sep 17 00:00:00 2001 From: Richard Spiegel Date: Wed, 24 Jul 2019 13:05:56 -0700 Subject: [PATCH 65/75] Documentation/soc/amd: Add Family 15h Create documentation for AMD Family 15h. BUG=none. TEST=none. Change-Id: Iaab4edc431329a691283121494595f3797c566c6 Signed-off-by: Richard Spiegel Reviewed-on: https://review.coreboot.org/c/coreboot/+/34561 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- Documentation/soc/amd/family15h.md | 49 ++++++++++++++++++++++++++++++ Documentation/soc/amd/index.md | 1 + 2 files changed, 50 insertions(+) create mode 100644 Documentation/soc/amd/family15h.md diff --git a/Documentation/soc/amd/family15h.md b/Documentation/soc/amd/family15h.md new file mode 100644 index 0000000000..fc41e91de2 --- /dev/null +++ b/Documentation/soc/amd/family15h.md @@ -0,0 +1,49 @@ +# AMD Family 15h [SOC|Processors] + +## Abstract + +Family 15h is a line of AMD x86 products first introduced in 2011. The initial +microarchitecture, codenamed "Bulldozer", introduced the concept of a "Compute +Unit" (CU) where some parts of the processor are shared between two cores and +some parts are unique for each core. Family 15h offerings matured into various +models with increased performance and features targeting Enterprise, Client, +and Embedded designs. Notice that a particular model can address more than one +market(see models references below). + +## Introduction + +The first CU designs were 2 x86 cores with separate integer processors but +sharing cache, code branch prediction engine and floating point processor. A die +can have up to 8 CU. The floating point processor is composed of two symmetrical +128-bit FMAC. Provided each x86 core is doing 128-bit floating point arithmetic, +they both do floating point simultaneously. If one is doing 256-bit floating +point, the other x86 core can't do floating point simultaneously. Later models +changed how resources were shared, and introduced other performance improvements. + +Family 15h products range from SOCs to 3-chip solutions. Devices designed to +contain on-die graphics (including headless) are commonly referred to as APUs, +not CPUs. + +Later SOCs include a Platform Security Processor (PSP), a small ARM processor +responsible for security related measures: For example, if secure boot is +enabled, the cores will not exit reset until the BIOS image within the SPI +flash is authenticated through its OEM signature, thus ensuring that only OEM +produced BIOS can run the platform. + +Support in coreboot for modern AMD products is based on AMD’s reference code: +AMD Generic Encapsulated Software Architecture (AGESA™). AGESA contains the +code for enabling DRAM, configuring proprietary core logic, assistance with +generating ACPI tables, and other features. + +While coreboot contains support for most models, some implementations use a +separate cpu/north/south bridge directory structure. Newer products for models +60h-6Fh (Merlin Falcon) and 70h-7Fh (Stoney Ridge) rely on modern SOC directory +structure. + +## References + +1. [Models 00h-0Fh BKDG](https://www.amd.com/system/files/TechDocs/42301_15h_Mod_00h-0Fh_BKDG.pdf) +2. [Models 10h-1Fh BKDG](https://www.amd.com/system/files/TechDocs/42300_15h_Mod_10h-1Fh_BKDG.pdf) +3. [Models 30h-3Fh BKDG](https://www.amd.com/system/files/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf) +4. [Models 60h-6Fh BKDG](https://www.amd.com/system/files/TechDocs/50742_15h_Models_60h-6Fh_BKDG.pdf) +5. [Models 70h-7Fh BKDG](https://www.amd.com/system/files/TechDocs/55072_AMD_Family_15h_Models_70h-7Fh_BKDG.pdf) diff --git a/Documentation/soc/amd/index.md b/Documentation/soc/amd/index.md index 7945b488f5..d6f31c88ca 100644 --- a/Documentation/soc/amd/index.md +++ b/Documentation/soc/amd/index.md @@ -4,5 +4,6 @@ This section contains documentation about coreboot on specific AMD SOCs. ## Technology +- [Family 15h](family15h.md) - [Family 17h](family17h.md) From 5387144a939b4ad3d334f2b4abebb987611b0274 Mon Sep 17 00:00:00 2001 From: Richard Spiegel Date: Mon, 22 Jul 2019 14:01:48 -0700 Subject: [PATCH 66/75] Documentation/mainboard/amd: Add padmelon documentation and images Create documentation on padmelon, including how to program the SPI. Also include an index.md pointing to the documentation, as currently there's no maiboard documentation folder for AMD. BUG=none. TEST=none. Change-Id: I1a684c1acd3fb9441df71e2bc0fffa6131148b98 Signed-off-by: Richard Spiegel Reviewed-on: https://review.coreboot.org/c/coreboot/+/34493 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- Documentation/mainboard/amd/index.md | 7 ++ .../mainboard/amd/padmelon/padmelon.jpg | Bin 0 -> 80772 bytes .../mainboard/amd/padmelon/padmelon.md | 80 ++++++++++++++++++ .../mainboard/amd/padmelon/padmelon_io.jpg | Bin 0 -> 32380 bytes 4 files changed, 87 insertions(+) create mode 100644 Documentation/mainboard/amd/index.md create mode 100644 Documentation/mainboard/amd/padmelon/padmelon.jpg create mode 100644 Documentation/mainboard/amd/padmelon/padmelon.md create mode 100644 Documentation/mainboard/amd/padmelon/padmelon_io.jpg diff --git a/Documentation/mainboard/amd/index.md b/Documentation/mainboard/amd/index.md new file mode 100644 index 0000000000..7a33de8f78 --- /dev/null +++ b/Documentation/mainboard/amd/index.md @@ -0,0 +1,7 @@ +# AMD platforms documentation + +This section contains documentation about specific AMD mainboards. + +## Mainboard + +- [padmelon](padmelon/padmelon.md) diff --git a/Documentation/mainboard/amd/padmelon/padmelon.jpg b/Documentation/mainboard/amd/padmelon/padmelon.jpg new file mode 100644 index 0000000000000000000000000000000000000000..76ee5786153902356d03a25b248a09642b19a8f1 GIT binary patch literal 80772 zcmeFXWmH_xyXU*1arY2BKyV1|)(P(J5Zq~8(j>tG!8H&hKm);Pf;Npqa0?Cz9xMUU zxCgoX&zU)A*4%k<&$_ejT6fK_dR6zctE%g%{i)h}e|J^gf4^S?NYs>6l>js}06=^A z0QWyht`&n^905R66W{^>00+Q8lLF8mERu%w%f-RT!5siF zlR^KcC@3D3Ls>G$f7orQDgS1JM8p9gHT6I3|5O(^pZ-PgA9eA6;yC)}oc|&44}pIO z{6pX$0{=-skY7MTl3z?xP?$+T_+N&QDDb~Z0{}h11+W900UN*vuz#4g&~gY%c+x?VK^|Tn4t_RF zK_2c9U&$aD=6|bQ^1=RB@-t>xX&-w>Nj(Ln|5oDRNanw{B``3MFHnfj)5qzVfP{p^ zGk(Emf`YscC3t;bLHuljcp<(l|E&TA2VXlM7cV~-PYBb$Dzvfn^!Jlt_V;(Omvppo z6tT6p7vZ(F5whnM5U{u5wXqix;I$VLvKJE(5Epb5ux0*l?(OaV!@HNikNdy*wzqrc z;O^kz0P*vEpds*#`PsiW`hS(Hc!;w9>SkVkF=8c=>Oi9|39K7D{XHlY4@+Td;0vldwmD*|98FZ?jrj? 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Some specs will change if not + using Merlin Falcon. +* One half mini PCI-Express slot on back side of mainboard +* One PCI Express® 3.0 x8 slot +* Two SATA3 ports with 6Gb/s data transfer rate +* Two USB 2.0 ports at rear panel +* Two USB 3.0 ports at rear panel +* Dual Gigabit Ethernet from Realtek RTL8111F Gigabit controller +* 6-channel High-Definition audio from Realtek ALC662 codec +* One soldered down SPI flash with dediprog header + +## Mainboard + +![mainboard][padmelon] + +Three items are marked in this picture +1. dediprog header +2. memory dimms, address 0xA0 and 0xA4 +3. SATA cables connected to motherboard + +## Back panel + +![back panel][padmelon_io] + +* The lower serial port is UART A (debug serial) + +## Flashing coreboot + +```eval_rst ++---------------------+--------------------+ +| Type | Value | ++=====================+====================+ +| Socketed flash | no | ++---------------------+--------------------+ +| Model | Macronix MX256435E | ++---------------------+--------------------+ +| Size | 8 MiB | ++---------------------+--------------------+ +| Flash programing | dediprog header | ++---------------------+--------------------+ +| Package | SOIC-8 | ++---------------------+--------------------+ +| Write protection | No | ++---------------------+--------------------+ +``` + +## Technology + +```eval_rst ++---------------+------------------------------+ +| Fan control | Using fintek F81803A | ++---------------+------------------------------+ +| CPU | Merlin Falcon (see reference)| ++---------------+------------------------------+ +``` + +## Description of pictures within this document + +```eval_rst ++----------------------------+----------------------------------------+ +|padmelon.jpg | Motherboard with components identified | ++----------------------------+----------------------------------------+ +|padmelon_io.jpg | Back panel picture | ++----------------------------+----------------------------------------+ +``` + +## Reference + +[Merlin Falcon BKDG][merlinfalcon] + +[merlinfalcon]: ../../soc/amd/family15h.md +[padmelon]: padmelon.jpg +[padmelon_io]: padmelon_io.jpg diff --git a/Documentation/mainboard/amd/padmelon/padmelon_io.jpg b/Documentation/mainboard/amd/padmelon/padmelon_io.jpg new file mode 100644 index 0000000000000000000000000000000000000000..ed715d4577ad84df6bc7b69ac8424b51099d4a4c GIT binary patch literal 32380 zcmeFXcT`i|yYCx9fDkF6i3ZTnd+z}x3B3mhy(pc~tAL0vBy__Gc@*9ynE0{})w01*HH00w|4Q~br`tQX3Gln(k2`*~)@zidibMF1c(^FQtXR2Sf)zX|@MF8)uPNB{Ks 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zqqOCM5n~d}>fM3Eu^5##Ug{Bn!aH;Y`UwcL zYd#hIr4?+mj^x9xr@Io?u$}TY@?Ju`x4+8q^BnuE`dGPpwPB^k#S0hZHTEa)p1P$j zwOk`ZPgiZXAAKc?zijuXK7;rZMYD4RYNE0mpUucn7NNp7UnvXO?}r2{fed0UKshSQ-o+tEOHo~^Z33BuJI?$wDM`TmT?NG;Y$BF-nVAIOt`v) z6AwM})=3rx{?D9dM;wXf)jC_GUSzb@bo}lUYR${Au%}eAU6#f+| z72nD&&_&2dlgF2xBS;%H<8HD(>|op7$`l{WGTI-fn5);h_#Q0kNzuWbC|zckGhaKp zjliXltZWBCD0RP&MRDrV`(umQ&aQ@ssMwXSav6Ad;hBk&h|{2LT|PC4@Oa61?9`lL&c=;93+kP5*)Vor$?JGirsjTV@4!P1>sx>x z?PBzotUOkj1&=g&Sf#TObV1ZDNg&Jw*_Mg--n6XgUGrdBi-#b~Q`&OrtvzflRP9%bM z|5d!Ylw!#}s?%wf%pW>pyrX=vwd*!VD^jLY-hxIAej{!q&*))(?o=|`(%>EnXA-}TwxxoSUoMfc3`n24Z=vwwT(7ElC3iTC-2 zhi+$0$dLK|4}T+vzR}9HM^iOs3o$T&D2oagL9vzJMvb4z!G$YKHH6-zs}c$ubqkf? zeK!kn>|Q9s?XCl=+eX9HeC%!9`)jBX@_cfSLVJA=NXjp@J(+|p76-(~4ZrKm)w$FU zE*7gew|S*L6!=b{-ZkpkSamhPmE^4*I*=S z*4N!dY&DcK{#a~R$BEo}74-4Vb+IT#*jE=hKUS#;lOX*q=YoAslJ;fIM zSg^W;f$v-A%1W2J;{9_O9)VOmcFC_TJ~=z8Jc?v*|0l)t^Q(Y{S~`jJ2_Gj+CVeEF zP(TlTb`oXWXJ;7`1lBX7BY3M-g0)6*d2XRlaGBRU%rN_kcTgcOlDP7DpSx0pl7MVwq@#f-CbCn(Qe=QA8D5Trjm~RI3^IK(5B_|_9IUQSCReKH49VueIWfC;! zuJ}%bQ(NFq-is`3NUYwF7PB_zjBFrO=z~WG1%Dhsrum}~-Gg2feBziqweK>7J#uif zG)uDvZPQ)yW$bVB?rsaGp9{a9#5|DQa+ZX_xKVtx8g6Jk@8r=?)MA&VHelFW>_L+Q537=Qc-rJw0# z?$U$1C>uV+DX87tTzamqrj8eRx zAw%f}-{XgxH2_^<4csZAeT$Ww+@aClHXLKVI^jg Date: Mon, 23 Sep 2019 14:38:41 +0200 Subject: [PATCH 67/75] soc/intel/skylake: devicetree: introduce PchHdaVcType fsp parameter MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make the the FSP Parameter PchHdaVcType a devicetree setting and make use of it in the devicetrees of all boards that currently set it. Signed-off-by: Michael Niewöhner Change-Id: Ibafc3b6bd2495658f2bd634218042ec413a89f5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/35542 Tested-by: build bot (Jenkins) Reviewed-by: Maxim Polyakov --- src/mainboard/asrock/h110m/devicetree.cb | 1 + src/mainboard/asrock/h110m/ramstage.c | 2 -- src/mainboard/intel/kblrvp/ramstage.c | 3 --- src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb | 1 + src/mainboard/supermicro/x11-lga1151-series/ramstage.c | 3 --- .../x11-lga1151-series/variants/x11ssh-tf/overridetree.cb | 3 +++ src/soc/intel/skylake/chip.h | 6 ++++++ src/soc/intel/skylake/chip_fsp20.c | 1 + 8 files changed, 12 insertions(+), 8 deletions(-) diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 572cd6ab52..acb2a9e629 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -55,6 +55,7 @@ chip soc/intel/skylake register "PmTimerDisabled" = "0" register "EnableAzalia" = "1" register "DspEnable" = "0" + register "PchHdaVcType" = "Vc1" register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/mainboard/asrock/h110m/ramstage.c b/src/mainboard/asrock/h110m/ramstage.c index c93e84c3d4..a247b72587 100644 --- a/src/mainboard/asrock/h110m/ramstage.c +++ b/src/mainboard/asrock/h110m/ramstage.c @@ -24,6 +24,4 @@ void mainboard_silicon_init_params(FSP_SIL_UPD *params) gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); params->CdClock = 3; - /* Enable Virtual Channel 1 */ - params->PchHdaVcType = 0x1; } diff --git a/src/mainboard/intel/kblrvp/ramstage.c b/src/mainboard/intel/kblrvp/ramstage.c index ad55c2675a..a19e96ec70 100644 --- a/src/mainboard/intel/kblrvp/ramstage.c +++ b/src/mainboard/intel/kblrvp/ramstage.c @@ -25,9 +25,6 @@ void mainboard_silicon_init_params(FSP_SIL_UPD *params) * dependencies during hardware initialization. */ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); params->CdClock = 3; - - /* Enable Virtual Channel 1 */ - params->PchHdaVcType = 0x1; } static void ioexpander_init(void *unused) diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index 2a1cb8a021..212721a90f 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -30,6 +30,7 @@ chip soc/intel/skylake register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "SaGv" = "SaGv_Enabled" + register "PchHdaVcType" = "Vc1" register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/mainboard/supermicro/x11-lga1151-series/ramstage.c b/src/mainboard/supermicro/x11-lga1151-series/ramstage.c index 694165aefc..a16678eb33 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/ramstage.c +++ b/src/mainboard/supermicro/x11-lga1151-series/ramstage.c @@ -20,7 +20,4 @@ void mainboard_silicon_init_params(FSP_SIL_UPD *params) /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); - - /* This must be one, otherwise FSP crashes ... */ - params->PchHdaVcType = 0x1; } diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index 1039f7a0ca..09aa8b558c 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -30,6 +30,9 @@ chip soc/intel/skylake register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "0" + # FIXME: find out why FSP crashes without this + register "PchHdaVcType" = "Vc1" + device domain 0 on device pci 01.0 on end # unused device pci 01.1 on # PCIE Slot (JPCIE1) diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 70fb045baf..944315b47e 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -208,6 +208,12 @@ struct soc_intel_skylake_config { u8 EnableAzalia; u8 DspEnable; + /* HDA Virtual Channel Type Select */ + enum { + Vc0, + Vc1, + } PchHdaVcType; + /* * I/O Buffer Ownership: * 0: HD-A Link diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index e46e52ccd2..462285c2a0 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -361,6 +361,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchIshEnable = dev ? dev->enabled : 0; params->PchHdaEnable = config->EnableAzalia; + params->PchHdaVcType = config->PchHdaVcType; params->PchHdaIoBufferOwnership = config->IoBufferOwnership; params->PchHdaDspEnable = config->DspEnable; params->Device4Enable = config->Device4Enable; From 4c80425f3037d43cc45d56801e0717471cea0489 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 3 Dec 2018 01:28:18 +0100 Subject: [PATCH 68/75] sb/intel/common/smihandler: Hook up smmstore TESTED on Asus P5QC. Change-Id: I20b87f3dcb898656ad31478820dd5153e4053cb2 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/30012 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/southbridge/intel/common/Kconfig | 1 + src/southbridge/intel/common/smihandler.c | 25 +++++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index c3bd90dca8..dfd89755ec 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -20,6 +20,7 @@ config SOUTHBRIDGE_INTEL_COMMON_SMBUS config SOUTHBRIDGE_INTEL_COMMON_SPI def_bool n select SPI_FLASH + select BOOT_DEVICE_SUPPORTS_WRITES config SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN def_bool n diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index daa0959e3b..d61238c865 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "pmutil.h" @@ -268,6 +269,26 @@ static void southbridge_smi_gsmi(void) } #endif +static void southbridge_smi_store(void) +{ + u8 sub_command, ret; + em64t101_smm_state_save_area_t *io_smi = + smi_apmc_find_state_save(APM_CNT_SMMSTORE); + uint32_t reg_ebx; + + if (!io_smi) + return; + /* Command and return value in EAX */ + sub_command = (io_smi->rax >> 8) & 0xff; + + /* Parameter buffer in EBX */ + reg_ebx = io_smi->rbx; + + /* drivers/smmstore/smi.c */ + ret = smmstore_exec(sub_command, (uintptr_t *)reg_ebx); + io_smi->rax = ret; +} + static int mainboard_finalized = 0; static void southbridge_smi_apmc(void) @@ -322,6 +343,10 @@ static void southbridge_smi_apmc(void) southbridge_smi_gsmi(); break; #endif + case APM_CNT_SMMSTORE: + if (CONFIG(SMMSTORE)) + southbridge_smi_store(); + break; } mainboard_smi_apmc(reg8); From cf9588040d91148c2c83b5f6200687448f4f2193 Mon Sep 17 00:00:00 2001 From: Yu-Ping Wu Date: Tue, 1 Oct 2019 14:16:51 +0800 Subject: [PATCH 69/75] mediatek/mt8183: Rename fields of struct sdram_params Two fields of struct sdram_params are renamed for future CL of DRAM full calibration. Field 'impedance' is also removed. BUG=none BRANCH=none TEST=emerge-kukui coreboot Change-Id: I2f9673fd5ea2e62ee971f0d81bdd12aaf565e31c Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/35738 Reviewed-by: Hung-Te Lin Tested-by: build bot (Jenkins) --- .../kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c | 8 ++------ .../sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c | 8 ++------ .../sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c | 8 ++------ .../sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c | 8 ++------ .../sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c | 8 ++------ .../sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c | 8 ++------ .../kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c | 8 ++------ .../kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c | 8 ++------ src/soc/mediatek/mt8183/dramc_pi_calibration_api.c | 4 ++-- src/soc/mediatek/mt8183/include/soc/emi.h | 5 ++--- 10 files changed, 20 insertions(+), 53 deletions(-) diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c index da6c7d255e..fab124038f 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-H9HCNNNCPMALHR-4GB.c @@ -16,19 +16,15 @@ #include struct sdram_params params = { - .impedance = { - [ODT_OFF] = {0x7, 0x6, 0x0, 0xF}, - [ODT_ON] = {0x9, 0x9, 0x0, 0xF} - }, .wr_level = { [CHANNEL_A] = { {0x22, 0x1b}, {0x22, 0x19} }, [CHANNEL_B] = { {0x24, 0x20}, {0x25, 0x20} } }, - .cbt_cs = { + .cbt_cs_dly = { [CHANNEL_A] = {0x0, 0x0}, [CHANNEL_B] = {0x0, 0x0} }, - .cbt_mr12 = { + .cbt_final_vref = { [CHANNEL_A] = {0x52, 0x52}, [CHANNEL_B] = {0x52, 0x52} }, diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c index 8d855ff1ba..d3c1496a6c 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB.c @@ -16,19 +16,15 @@ #include struct sdram_params params = { - .impedance = { - [ODT_OFF] = {0x9, 0x7, 0x0, 0xF}, - [ODT_ON] = {0xB, 0x9, 0x0, 0xE} - }, .wr_level = { [CHANNEL_A] = { {0x22, 0x1C}, {0x23, 0x1D} }, [CHANNEL_B] = { {0x26, 0x23}, {0x26, 0x23} } }, - .cbt_cs = { + .cbt_cs_dly = { [CHANNEL_A] = {0x6, 0x5}, [CHANNEL_B] = {0x6, 0x6} }, - .cbt_mr12 = { + .cbt_final_vref = { [CHANNEL_A] = {0x56, 0x58}, [CHANNEL_B] = {0x58, 0x56} }, diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c index 1e0c3628fd..c21cd12315 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDH6001DA-B422-4GB.c @@ -16,19 +16,15 @@ #include struct sdram_params params = { - .impedance = { - [ODT_OFF] = {0x9, 0x7, 0x0, 0xF}, - [ODT_ON] = {0xA, 0x9, 0x0, 0xE} - }, .wr_level = { [CHANNEL_A] = { {0x21, 0x21}, {0x20, 0x20} }, [CHANNEL_B] = { {0x1E, 0x1F}, {0x1D, 0x1E} } }, - .cbt_cs = { + .cbt_cs_dly = { [CHANNEL_A] = {0x1, 0x1}, [CHANNEL_B] = {0x2, 0x2} }, - .cbt_mr12 = { + .cbt_final_vref = { [CHANNEL_A] = {0x56, 0x56}, [CHANNEL_B] = {0x58, 0x5C} }, diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c index 12acc61b3e..434984541c 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDP6001DA-B425-4GB.c @@ -16,19 +16,15 @@ #include struct sdram_params params = { - .impedance = { - [ODT_OFF] = {0x7, 0x6, 0x0, 0xF}, - [ODT_ON] = {0x8, 0x9, 0x0, 0xD} - }, .wr_level = { [CHANNEL_A] = { {0x22, 0x21}, {0x20, 0x21} }, [CHANNEL_B] = { {0x23, 0x27}, {0x23, 0x27} } }, - .cbt_cs = { + .cbt_cs_dly = { [CHANNEL_A] = {0x0, 0x0}, [CHANNEL_B] = {0x6, 0x6} }, - .cbt_mr12 = { + .cbt_final_vref = { [CHANNEL_A] = {0x56, 0x5A}, [CHANNEL_B] = {0x58, 0x58} }, diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c index 8cc0d3d693..cab57ce853 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-KMDV6001DA-B620-4GB.c @@ -16,19 +16,15 @@ #include struct sdram_params params = { - .impedance = { - [ODT_OFF] = {0x8, 0x7, 0x0, 0xF}, - [ODT_ON] = {0x9, 0x9, 0x0, 0xD} - }, .wr_level = { [CHANNEL_A] = { {0x21, 0x24}, {0x22, 0x24} }, [CHANNEL_B] = { {0x24, 0x28}, {0x22, 0x27} } }, - .cbt_cs = { + .cbt_cs_dly = { [CHANNEL_A] = {0xC, 0xC}, [CHANNEL_B] = {0xB, 0xB} }, - .cbt_mr12 = { + .cbt_final_vref = { [CHANNEL_A] = {0x58, 0x58}, [CHANNEL_B] = {0x56, 0x56} }, diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c index 512023b35e..2810ef50f7 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT29VZZZAD8DQKSL-4GB.c @@ -16,19 +16,15 @@ #include struct sdram_params params = { - .impedance = { - [ODT_OFF] = {0x9, 0x7, 0x0, 0xF}, - [ODT_ON] = {0xA, 0x9, 0x0, 0xE} - }, .wr_level = { [CHANNEL_A] = { {0x21, 0x21}, {0x20, 0x20} }, [CHANNEL_B] = { {0x21, 0x28}, {0x21, 0x29} } }, - .cbt_cs = { + .cbt_cs_dly = { [CHANNEL_A] = {0x2, 0x2}, [CHANNEL_B] = {0x2, 0x2} }, - .cbt_mr12 = { + .cbt_final_vref = { [CHANNEL_A] = {0x5E, 0x5E}, [CHANNEL_B] = {0x5E, 0x5C} }, diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c index 0fb5abacba..329cc76afe 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-MT53E1G32D4NQ-4GB.c @@ -16,19 +16,15 @@ #include struct sdram_params params = { - .impedance = { - [ODT_OFF] = {0x5, 0x7, 0x0, 0xF}, - [ODT_ON] = {0x6, 0x9, 0x0, 0xF} - }, .wr_level = { [CHANNEL_A] = { {0x1F, 0x19}, {0x20, 0x1A} }, [CHANNEL_B] = { {0x22, 0x1E}, {0x22, 0x1E} } }, - .cbt_cs = { + .cbt_cs_dly = { [CHANNEL_A] = {0x5, 0x4}, [CHANNEL_B] = {0x8, 0x8} }, - .cbt_mr12 = { + .cbt_final_vref = { [CHANNEL_A] = {0x56, 0x56}, [CHANNEL_B] = {0x56, 0x56} }, diff --git a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c index 61060d6fdc..ccb591e06a 100644 --- a/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c +++ b/src/mainboard/google/kukui/sdram_params/sdram-lpddr4x-SDADA4CR-128G-4GB.c @@ -16,19 +16,15 @@ #include struct sdram_params params = { - .impedance = { - [ODT_OFF] = {0x8, 0x7, 0x0, 0xF}, - [ODT_ON] = {0x9, 0x9, 0x0, 0xE} - }, .wr_level = { [CHANNEL_A] = { {0x1F, 0x1C}, {0x1C, 0x1B} }, [CHANNEL_B] = { {0x27, 0x28}, {0x23, 0x28} } }, - .cbt_cs = { + .cbt_cs_dly = { [CHANNEL_A] = {0x3, 0x3}, [CHANNEL_B] = {0x4, 0x6} }, - .cbt_mr12 = { + .cbt_final_vref = { [CHANNEL_A] = {0x5C, 0x5A}, [CHANNEL_B] = {0x5C, 0x5A} }, diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index fcc3b14a1e..f8b1f091ed 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -252,8 +252,8 @@ static void dramc_cmd_bus_training(u8 chn, u8 rank, u8 freq_group, { u32 cbt_cs, mr12_value; - cbt_cs = params->cbt_cs[chn][rank]; - mr12_value = params->cbt_mr12[chn][rank]; + cbt_cs = params->cbt_cs_dly[chn][rank]; + mr12_value = params->cbt_final_vref[chn][rank]; /* CBT adjust cs */ clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h index 264d91869a..15889eeca4 100644 --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -21,10 +21,9 @@ #include struct sdram_params { - u32 impedance[2][4]; u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; - u8 cbt_cs[CHANNEL_MAX][RANK_MAX]; - u8 cbt_mr12[CHANNEL_MAX][RANK_MAX]; + u8 cbt_cs_dly[CHANNEL_MAX][RANK_MAX]; + u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX]; u32 emi_cona_val; u32 emi_conh_val; u32 emi_conf_val; From 0f47ff1be5a16c8de1995617830ec8fedbbb4197 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Wed, 4 Sep 2019 13:49:07 +0800 Subject: [PATCH 70/75] mb/google/drallion: Dynamicly disable memory channel Disable memory channel by HW strap pin. Using for factory debug. BUG=b:139773082 BRANCH=N/A TEST=Rework HW strap pin and check /proc/mem_info Signed-off-by: Eric Lai Change-Id: Ic5f53f0ba3bd432fbcb7513d2a8aa49d42f7a23e Reviewed-on: https://review.coreboot.org/c/coreboot/+/35241 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/google/drallion/variants/drallion/gpio.c | 7 +++++++ .../drallion/variants/drallion/include/variant/gpio.h | 4 ++++ 2 files changed, 11 insertions(+) diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index 154fc5a7f2..f0fc55e8d4 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -286,4 +286,11 @@ void variant_mainboard_post_init_params(FSPM_UPD *mupd) FSP_M_CONFIG *fsp_m_cfg = &mupd->FspmConfig; if (fsp_m_cfg->PchIshEnable) fsp_m_cfg->PchIshEnable = is_ish_device_enabled(); + + /* + * Disable memory channel by HW strap pin, HW default is enable + * 0: Enable both DIMMs, 3: Disable both DIMMs + */ + mupd->FspmConfig.DisableDimmChannel0 = gpio_get(DDR_CH0_EN) ? 0 : 3; + mupd->FspmConfig.DisableDimmChannel1 = gpio_get(DDR_CH1_EN) ? 0 : 3; } diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h index 251b40e0d0..219e0c4b37 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h @@ -28,6 +28,10 @@ /* Sensor detection pin */ #define SENSOR_DET_360 GPP_H5 +/* DDR channel enable pin */ +#define DDR_CH0_EN GPP_F1 +#define DDR_CH1_EN GPP_F2 + /* Memory configuration board straps */ #define GPIO_MEM_CONFIG_0 GPP_F12 #define GPIO_MEM_CONFIG_1 GPP_F13 From d3d38c95b7c23c5bd455d35e1b5bef0bce7b2cc5 Mon Sep 17 00:00:00 2001 From: Himanshu Sahdev Date: Mon, 23 Sep 2019 15:08:18 +0530 Subject: [PATCH 71/75] coreinfo/coreinfo.c: Support both lower and upper case alphabets Modify handle_category_key to handle both upper and lower case alphabets in the coreinfo payload. Change-Id: I3ccbf69e90ba7824ad6ec85d2ca59aa8f40b3006 Signed-off-by: Himanshu Sahdev Reviewed-on: https://review.coreboot.org/c/coreboot/+/35538 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- payloads/coreinfo/coreinfo.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/payloads/coreinfo/coreinfo.c b/payloads/coreinfo/coreinfo.c index b731abfbf5..53985b293a 100644 --- a/payloads/coreinfo/coreinfo.c +++ b/payloads/coreinfo/coreinfo.c @@ -198,8 +198,13 @@ static void redraw_module(struct coreinfo_cat *cat) static void handle_category_key(struct coreinfo_cat *cat, int key) { - if (key >= 'a' && key <= 'z') { - int index = key - 'a'; + if ((key >= 'a' && key <= 'z') || (key >= 'A' && key <= 'Z')) { + int index; + if (key >= 'A' && key <= 'Z') { + index = key - 'A'; + } else { + index = key - 'a'; + } if (index < cat->count) { cat->cur = index; redraw_module(cat); From d5f645c6cde230004ee5af6c62d451d1329928e9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 28 Sep 2019 00:20:27 +0300 Subject: [PATCH 72/75] soc/intel: Replace config_of_path() with config_of_soc() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The previously provided device path made no difference, all integrated PCI devices point back to the same chip_info structure. Change reduces the exposure of various SA_DEVFN_xx and PCH_DEVFN_xx from (ugly) soc/pci_devs.h. Change-Id: Ibf13645fdd3ef7fd3d5c8217bb24d7ede045c790 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35656 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/include/device/device.h | 11 ++--------- src/mainboard/google/fizz/mainboard.c | 2 +- src/mainboard/google/hatch/variants/akemi/variant.c | 2 +- src/mainboard/google/hatch/variants/kindred/variant.c | 2 +- src/mainboard/google/poppy/variants/atlas/mainboard.c | 2 +- src/mainboard/google/poppy/variants/nami/mainboard.c | 2 +- .../google/poppy/variants/nautilus/mainboard.c | 2 +- .../google/poppy/variants/nocturne/mainboard.c | 2 +- src/soc/intel/apollolake/acpi.c | 4 ++-- src/soc/intel/apollolake/chip.c | 4 ++-- src/soc/intel/apollolake/cpu.c | 2 +- src/soc/intel/apollolake/memmap.c | 2 +- src/soc/intel/apollolake/pmutil.c | 2 +- src/soc/intel/apollolake/pnpconfig.c | 2 +- src/soc/intel/apollolake/romstage.c | 4 ++-- src/soc/intel/broadwell/acpi.c | 2 +- src/soc/intel/broadwell/cpu.c | 4 ++-- src/soc/intel/broadwell/romstage/pch.c | 2 +- src/soc/intel/cannonlake/acpi.c | 8 ++++---- src/soc/intel/cannonlake/chip.c | 2 +- src/soc/intel/cannonlake/cpu.c | 10 +++++----- src/soc/intel/cannonlake/finalize.c | 2 +- src/soc/intel/cannonlake/fsp_params.c | 4 ++-- src/soc/intel/cannonlake/pmc.c | 2 +- src/soc/intel/cannonlake/pmutil.c | 2 +- src/soc/intel/cannonlake/smihandler.c | 2 +- src/soc/intel/common/block/chip/chip.c | 2 +- src/soc/intel/fsp_broadwell_de/iou_complto.c | 2 +- src/soc/intel/icelake/acpi.c | 8 ++++---- src/soc/intel/icelake/chip.c | 2 +- src/soc/intel/icelake/cpu.c | 4 ++-- src/soc/intel/icelake/finalize.c | 2 +- src/soc/intel/icelake/fsp_params.c | 4 ++-- src/soc/intel/icelake/pmc.c | 2 +- src/soc/intel/icelake/pmutil.c | 2 +- src/soc/intel/icelake/romstage/fsp_params.c | 2 +- src/soc/intel/icelake/smihandler.c | 2 +- src/soc/intel/quark/romstage/fsp2_0.c | 2 +- src/soc/intel/skylake/acpi.c | 8 ++++---- src/soc/intel/skylake/chip_fsp20.c | 2 +- src/soc/intel/skylake/cpu.c | 10 +++++----- src/soc/intel/skylake/pmc.c | 2 +- src/soc/intel/skylake/pmutil.c | 2 +- src/soc/intel/skylake/romstage/romstage.c | 4 ++-- src/soc/intel/skylake/romstage/romstage_fsp20.c | 2 +- src/soc/intel/skylake/romstage/systemagent.c | 2 +- 46 files changed, 72 insertions(+), 79 deletions(-) diff --git a/src/include/device/device.h b/src/include/device/device.h index f24e4b2157..cb37c096e4 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -321,16 +321,9 @@ static inline DEVTREE_CONST void *config_of(const struct device *dev) devtree_die(); } -static inline DEVTREE_CONST void *config_of_path(pci_devfn_t devfn) +static inline DEVTREE_CONST void *config_of_soc(void) { - const struct device *dev = pcidev_path_on_root(devfn); - if (dev) - return config_of(dev); - - devtree_bug(__func__, devfn); - - dev = dev_find_slot(0, devfn); - return config_of(dev); + return config_of(pcidev_on_root(0, 0)); } void scan_smbus(struct device *bus); diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 6b3423b886..89e692741e 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -221,7 +221,7 @@ static unsigned long mainboard_write_acpi_tables( static void mainboard_enable(struct device *dev) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); mainboard_set_power_limits(conf); diff --git a/src/mainboard/google/hatch/variants/akemi/variant.c b/src/mainboard/google/hatch/variants/akemi/variant.c index 0717e810ce..c648a527f5 100644 --- a/src/mainboard/google/hatch/variants/akemi/variant.c +++ b/src/mainboard/google/hatch/variants/akemi/variant.c @@ -23,7 +23,7 @@ void variant_devtree_update(void) uint32_t sku_id; struct device *emmc_host; struct device *ssd_host; - config_t *cfg = config_of_path(SA_DEVFN_ROOT); + config_t *cfg = config_of_soc(); emmc_host = pcidev_path_on_root(PCH_DEVFN_EMMC); ssd_host = pcidev_path_on_root(PCH_DEVFN_SATA); diff --git a/src/mainboard/google/hatch/variants/kindred/variant.c b/src/mainboard/google/hatch/variants/kindred/variant.c index 6cd017bf60..1e1d083c25 100644 --- a/src/mainboard/google/hatch/variants/kindred/variant.c +++ b/src/mainboard/google/hatch/variants/kindred/variant.c @@ -23,7 +23,7 @@ void variant_devtree_update(void) uint32_t sku_id; struct device *emmc_host; struct device *ssd_host; - config_t *cfg = config_of_path(SA_DEVFN_ROOT); + config_t *cfg = config_of_soc(); emmc_host = pcidev_path_on_root(PCH_DEVFN_EMMC); ssd_host = pcidev_path_on_root(PCH_DEVFN_SATA); diff --git a/src/mainboard/google/poppy/variants/atlas/mainboard.c b/src/mainboard/google/poppy/variants/atlas/mainboard.c index 9c4b2bc75d..e1538c67b6 100644 --- a/src/mainboard/google/poppy/variants/atlas/mainboard.c +++ b/src/mainboard/google/poppy/variants/atlas/mainboard.c @@ -39,7 +39,7 @@ static uint32_t get_pl2(void) /* Override dev tree settings per board */ void variant_devtree_update(void) { - config_t *cfg = config_of_path(SA_DEVFN_ROOT); + config_t *cfg = config_of_soc(); /* Update PL2 based on CPU */ cfg->tdp_pl2_override = get_pl2(); diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index e48a952022..e3855bd794 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -241,7 +241,7 @@ void variant_devtree_update(void) uint8_t pl2_id = PL2_ID_DEFAULT; struct device *spi_fpmcu = PCH_DEV_GSPI1; - config_t *cfg = config_of_path(SA_DEVFN_ROOT); + config_t *cfg = config_of_soc(); switch (sku_id) { case SKU_0_SONA: diff --git a/src/mainboard/google/poppy/variants/nautilus/mainboard.c b/src/mainboard/google/poppy/variants/nautilus/mainboard.c index 9aa6b724dd..b78ec82aeb 100644 --- a/src/mainboard/google/poppy/variants/nautilus/mainboard.c +++ b/src/mainboard/google/poppy/variants/nautilus/mainboard.c @@ -44,7 +44,7 @@ void variant_devtree_update(void) uint16_t abase; uint32_t val32; - config_t *cfg = config_of_path(SA_DEVFN_ROOT); + config_t *cfg = config_of_soc(); switch (sku_id) { case SKU_0_NAUTILUS: diff --git a/src/mainboard/google/poppy/variants/nocturne/mainboard.c b/src/mainboard/google/poppy/variants/nocturne/mainboard.c index 7b6b28b0ba..3743cf70b1 100644 --- a/src/mainboard/google/poppy/variants/nocturne/mainboard.c +++ b/src/mainboard/google/poppy/variants/nocturne/mainboard.c @@ -40,7 +40,7 @@ static uint32_t get_pl2(void) /* Override dev tree settings per board */ void variant_devtree_update(void) { - config_t *cfg = config_of_path(SA_DEVFN_ROOT); + config_t *cfg = config_of_soc(); /* Update PL2 based on CPU */ cfg->tdp_pl2_override = get_pl2(); diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index f729f3139e..7163884365 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -90,7 +90,7 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries) void acpi_create_gnvs(struct global_nvs_t *gnvs) { struct soc_intel_apollolake_config *cfg; - cfg = config_of_path(SA_DEVFN_ROOT); + cfg = config_of_soc(); /* Clear out GNVS. */ memset(gnvs, 0, sizeof(*gnvs)); @@ -152,7 +152,7 @@ int soc_madt_sci_irq_polarity(int sci) void soc_fill_fadt(acpi_fadt_t *fadt) { const struct soc_intel_apollolake_config *cfg; - cfg = config_of_path(SA_DEVFN_ROOT); + cfg = config_of_soc(); fadt->pm_tmr_blk = ACPI_BASE_ADDRESS + PM1_TMR; diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index b7159efaec..8e516f8a84 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -300,7 +300,7 @@ static void set_power_limits(void) uint32_t tdp, min_power, max_power; uint32_t pl2_val; - cfg = config_of_path(SA_DEVFN_ROOT); + cfg = config_of_soc(); if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) { printk(BIOS_INFO, "Skip the RAPL settings.\n"); @@ -364,7 +364,7 @@ static void set_sci_irq(void) struct soc_intel_apollolake_config *cfg; uint32_t scis; - cfg = config_of_path(SA_DEVFN_ROOT); + cfg = config_of_soc(); /* Change only if a device tree entry exists. */ if (cfg->sci_irq) { diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 3f06026336..33496273d2 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -296,7 +296,7 @@ void cpu_lock_sgx_memory(void) int soc_fill_sgx_param(struct sgx_param *sgx_param) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); sgx_param->enable = conf->sgx_enable; return 0; diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index 905fa64571..77711ebf26 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -35,7 +35,7 @@ void *cbmem_top(void) if (!CONFIG(SOC_INTEL_GLK)) return tolum; - config = config_of_path(PCH_DEVFN_LPC); + config = config_of_soc(); /* FSP allocates 2x PRMRR Size Memory for alignment */ if (config->sgx_enable) diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 84b61da6b1..23e9732e91 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -148,7 +148,7 @@ void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_apollolake_config *config; - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); /* Assign to out variable */ *dw0 = config->gpe0_dw1; diff --git a/src/soc/intel/apollolake/pnpconfig.c b/src/soc/intel/apollolake/pnpconfig.c index 0e9e93118a..274f630a71 100644 --- a/src/soc/intel/apollolake/pnpconfig.c +++ b/src/soc/intel/apollolake/pnpconfig.c @@ -39,7 +39,7 @@ static void pnp_settings(void *unused) const struct pnpconfig *pnpconfigarr; struct soc_intel_apollolake_config *config; - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); switch (config->pnp_settings) { case PNP_PERF: diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 29498656dc..8418919bd2 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -95,7 +95,7 @@ static void soc_early_romstage_init(void) static void configure_thermal_target(void) { msr_t msr; - const config_t *conf = config_of_path(SA_DEVFN_ROOT); + const config_t *conf = config_of_soc(); if (!conf->tcc_offset) return; @@ -269,7 +269,7 @@ static void soc_memory_init_params(FSPM_UPD *mupd) /* Only for GLK */ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - const config_t *config = config_of_path(PCH_DEVFN_LPC); + const config_t *config = config_of_soc(); m_cfg->PrmrrSize = config->PrmrrSize; diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 705bc0089e..7acde68db1 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -390,7 +390,7 @@ static void generate_C_state_entries(void) int *set; int i; - config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc(); if (config->s0ix_enable) set = cstate_set_s0ix; diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 54a695eec1..8fe66dce5b 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -196,7 +196,7 @@ static int pcode_mailbox_write(u32 command, u32 data) static void initialize_vr_config(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr; printk(BIOS_DEBUG, "Initializing VR config.\n"); @@ -450,7 +450,7 @@ static void configure_c_states(void) static void configure_thermal_target(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr; diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c index 0bd4ccd471..af8ea53dea 100644 --- a/src/soc/intel/broadwell/romstage/pch.c +++ b/src/soc/intel/broadwell/romstage/pch.c @@ -78,7 +78,7 @@ static void pch_enable_lpc(void) /* Lookup device tree in romstage */ const config_t *config; - config = config_of_path(PCH_DEVFN_LPC); + config = config_of_soc(); pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec); pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec); diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 89770c0586..6846594ebf 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -145,7 +145,7 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries) int *set; int i; - config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc(); int is_s0ix_enable = config->s0ix_enable; @@ -166,7 +166,7 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries) void soc_power_states_generation(int core_id, int cores_per_package) { - config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc(); /* Generate P-state tables */ if (config->eist_enable) @@ -177,7 +177,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { const uint16_t pmbase = ACPI_BASE_ADDRESS; const struct soc_intel_cannonlake_config *config; - config = config_of_path(PCH_DEVFN_LPC); + config = config_of_soc(); if (!config->PmTimerDisabled) { fadt->pm_tmr_blk = pmbase + PM1_TMR; @@ -202,7 +202,7 @@ uint32_t soc_read_sci_irq_select(void) void acpi_create_gnvs(struct global_nvs_t *gnvs) { const struct soc_intel_cannonlake_config *config; - config = config_of_path(PCH_DEVFN_LPC); + config = config_of_soc(); /* Set unknown wake source */ gnvs->pm1i = -1; diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index c0810fb2ea..0ce2f1aca7 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -170,7 +170,7 @@ void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads) static void soc_fill_gpio_pm_configuration(void) { uint8_t value[TOTAL_GPIO_COMM]; - const config_t *config = config_of_path(SA_DEVFN_ROOT); + const config_t *config = config_of_soc(); if (config->gpio_override_pm) memcpy(value, config->gpio_pm, sizeof(uint8_t) * diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 0f4d52e790..c58b9ad693 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -106,7 +106,7 @@ void set_power_limits(u8 power_limit_1_time) unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1; u8 power_limit_1_val; - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; @@ -234,7 +234,7 @@ static void soc_fsp_load(void) static void configure_isst(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr; if (conf->speed_shift_enable) { @@ -259,7 +259,7 @@ static void configure_isst(void) static void configure_misc(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr; msr = rdmsr(IA32_MISC_ENABLE); @@ -361,7 +361,7 @@ static void configure_c_states(void) static void configure_thermal_target(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr; /* Set TCC activation offset if supported */ @@ -387,7 +387,7 @@ static void enable_pm_timer_emulation(void) const struct soc_intel_cannonlake_config *config; msr_t msr; - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); /* Enable PM timer emulation only if ACPI PM timer is disabled */ if (!config->PmTimerDisabled) diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index c99653b75a..115b73254e 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -84,7 +84,7 @@ static void pch_finalize(void) * point and hence removed from the root bus. pcidev_path_on_root thus * returns NULL for PCH_DEV_PMC device. */ - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); pmcbase = pmc_mmio_regs(); if (config->PmTimerDisabled) { reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 76d40aa624..b580620d70 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -99,7 +99,7 @@ static void parse_devicetree_param(const config_t *config, FSP_S_CONFIG *params) static void parse_devicetree(FSP_S_CONFIG *params) { - const config_t *config = config_of_path(SA_DEVFN_ROOT); + const config_t *config = config_of_soc(); parse_devicetree_param(config, params); } @@ -145,7 +145,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig; struct device *dev; - config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc(); /* Parse device tree and enable/disable devices */ parse_devicetree(params); diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c index b9f455ff68..c0bb9ae296 100644 --- a/src/soc/intel/cannonlake/pmc.c +++ b/src/soc/intel/cannonlake/pmc.c @@ -102,7 +102,7 @@ static void config_deep_sx(uint32_t deepsx_config) static void pmc_init(void *unused) { - const config_t *config = config_of_path(SA_DEVFN_ROOT); + const config_t *config = config_of_soc(); rtc_init(); diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index 1626e300d8..a543861406 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -175,7 +175,7 @@ uintptr_t soc_read_pmc_base(void) void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_cannonlake_config *config; - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); /* Assign to out variable */ *dw0 = config->gpe0_dw0; diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index b8ceec0f1d..4d0b241517 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -79,7 +79,7 @@ void smihandler_soc_at_finalize(void) { const struct soc_intel_cannonlake_config *config; - config = config_of_path(PCH_DEVFN_CSE); + config = config_of_soc(); if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) pch_disable_heci(); diff --git a/src/soc/intel/common/block/chip/chip.c b/src/soc/intel/common/block/chip/chip.c index 9e74803e1a..5ab8f6b07d 100644 --- a/src/soc/intel/common/block/chip/chip.c +++ b/src/soc/intel/common/block/chip/chip.c @@ -22,7 +22,7 @@ const struct soc_intel_common_config *chip_get_common_soc_structure(void) const struct soc_intel_common_config *soc_config; const config_t *config; - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); soc_config = &config->common_soc_config; return soc_config; diff --git a/src/soc/intel/fsp_broadwell_de/iou_complto.c b/src/soc/intel/fsp_broadwell_de/iou_complto.c index f998d97547..b092f53875 100644 --- a/src/soc/intel/fsp_broadwell_de/iou_complto.c +++ b/src/soc/intel/fsp_broadwell_de/iou_complto.c @@ -24,7 +24,7 @@ static void iou_init(struct device *dev) { /* Use config from device always present in static devicetree. */ - const config_t *config = config_of_path(SOC_DEV_FUNC); + const config_t *config = config_of_soc(); u16 devctl2; /* pcie completion timeout diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index c61d877d1c..4089679d1c 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -138,7 +138,7 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries) int *set; int i; - config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc(); int is_s0ix_enable = config->s0ix_enable; @@ -159,7 +159,7 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries) void soc_power_states_generation(int core_id, int cores_per_package) { - config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc(); if (config->eist_enable) /* Generate P-state tables */ @@ -170,7 +170,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt) { const uint16_t pmbase = ACPI_BASE_ADDRESS; - config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc(); if (!config->PmTimerDisabled) { fadt->pm_tmr_blk = pmbase + PM1_TMR; @@ -194,7 +194,7 @@ uint32_t soc_read_sci_irq_select(void) void acpi_create_gnvs(struct global_nvs_t *gnvs) { - config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc(); /* Set unknown wake source */ gnvs->pm1i = -1; diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index e71c573f98..2bb908c064 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -107,7 +107,7 @@ const char *soc_acpi_name(const struct device *dev) static void soc_fill_gpio_pm_configuration(void) { uint8_t value[TOTAL_GPIO_COMM]; - const config_t *config = config_of_path(SA_DEVFN_ROOT); + const config_t *config = config_of_soc(); if (config->gpio_override_pm) memcpy(value, config->gpio_pm, sizeof(uint8_t) * diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index 8a65ccf5d3..0ecccb94e5 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -40,7 +40,7 @@ static void soc_fsp_load(void) static void configure_isst(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr; if (conf->speed_shift_enable) { @@ -67,7 +67,7 @@ static void configure_misc(void) { msr_t msr; - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c index 086787d9df..a70b5a1ed4 100644 --- a/src/soc/intel/icelake/finalize.c +++ b/src/soc/intel/icelake/finalize.c @@ -83,7 +83,7 @@ static void pch_finalize(void) * point and hence removed from the root bus. pcidev_path_on_root thus * returns NULL for PCH_DEV_PMC device. */ - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); pmcbase = pmc_mmio_regs(); if (config->PmTimerDisabled) { reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL); diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index e31e47bf57..8819e7d033 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -31,7 +31,7 @@ static void parse_devicetree(FSP_S_CONFIG *params) { const struct soc_intel_icelake_config *config; - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i]; @@ -69,7 +69,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) struct device *dev; struct soc_intel_icelake_config *config; - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); /* Parse device tree and enable/disable devices */ parse_devicetree(params); diff --git a/src/soc/intel/icelake/pmc.c b/src/soc/intel/icelake/pmc.c index 28fc01d029..6348d28b25 100644 --- a/src/soc/intel/icelake/pmc.c +++ b/src/soc/intel/icelake/pmc.c @@ -84,7 +84,7 @@ static void config_deep_sx(uint32_t deepsx_config) static void pmc_init(void *unused) { - const config_t *config = config_of_path(SA_DEVFN_ROOT); + const config_t *config = config_of_soc(); rtc_init(); diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index a70840b527..c20da5018a 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -174,7 +174,7 @@ void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_icelake_config *config; - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); /* Assign to out variable */ *dw0 = config->gpe0_dw0; diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index a78c8a49cf..5bf34213f0 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -79,7 +79,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) const struct soc_intel_icelake_config *config; FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); soc_memory_init_params(m_cfg, config); diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index 8db2c3bbb4..b7c37d4aa7 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -76,7 +76,7 @@ void smihandler_soc_at_finalize(void) { const struct soc_intel_icelake_config *config; - config = config_of_path(PCH_DEVFN_CSE); + config = config_of_soc(); if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) pch_disable_heci(); diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index a64fed4868..cd654d74de 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -93,7 +93,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version) "Microcode file (rmu.bin) not found."); /* Locate the configuration data from devicetree.cb */ - config = config_of_path(LPC_DEV_FUNC); + config = config_of_soc(); /* Update the architectural UPD values. */ aupd = &fspm_upd->FspmArchUpd; diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index d67b502ac8..de37341a08 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -172,7 +172,7 @@ static int get_cores_per_package(void) static void acpi_create_gnvs(global_nvs_t *gnvs) { - const struct soc_intel_skylake_config *config = config_of_path(PCH_DEVFN_LPC); + const struct soc_intel_skylake_config *config = config_of_soc(); /* Set unknown wake source */ gnvs->pm1i = -1; @@ -232,7 +232,7 @@ unsigned long acpi_fill_madt(unsigned long current) void acpi_fill_fadt(acpi_fadt_t *fadt) { const uint16_t pmbase = ACPI_BASE_ADDRESS; - config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc(); /* Use ACPI 3.0 revision */ fadt->header.revision = get_acpi_table_revision(FADT); @@ -503,7 +503,7 @@ void generate_cpu_entries(struct device *device) int totalcores = dev_count_cpu(); int cores_per_package = get_cores_per_package(); int numcpus = totalcores/cores_per_package; - config_t *config = config_of_path(SA_DEVFN_ROOT); + config_t *config = config_of_soc(); int is_s0ix_enable = config->s0ix_enable; printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", @@ -674,7 +674,7 @@ void southbridge_inject_dsdt(struct device *device) /* Save wake source information for calculating ACPI _SWS values */ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) { - const struct soc_intel_skylake_config *config = config_of_path(PCH_DEVFN_LPC); + const struct soc_intel_skylake_config *config = config_of_soc(); struct chipset_power_state *ps; static uint32_t gpe0_sts[GPE0_REG_MAX]; uint32_t pm1_en; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 462285c2a0..55fedd3cf5 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -237,7 +237,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) uintptr_t vbt_data = (uintptr_t)vbt_get(); int i; - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); mainboard_silicon_init_params(params); /* Set PsysPmax if it is available from DT */ diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 0d49d28d3d..5424c91c58 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -117,7 +117,7 @@ void set_power_limits(u8 power_limit_1_time) unsigned int tdp, min_power, max_power, max_time, tdp_pl2, tdp_pl1; u8 power_limit_1_val; - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr)) power_limit_1_time = ARRAY_SIZE(power_limit_time_sec_to_msr) - 1; @@ -240,7 +240,7 @@ void set_power_limits(u8 power_limit_1_time) static void configure_thermal_target(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr; @@ -260,7 +260,7 @@ static void configure_thermal_target(void) static void configure_isst(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr; @@ -286,7 +286,7 @@ static void configure_isst(void) static void configure_misc(void) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); msr_t msr; @@ -562,7 +562,7 @@ void cpu_lock_sgx_memory(void) int soc_fill_sgx_param(struct sgx_param *sgx_param) { - config_t *conf = config_of_path(SA_DEVFN_ROOT); + config_t *conf = config_of_soc(); sgx_param->enable = conf->sgx_enable; return 0; diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index ffe060518e..ab9297fe92 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -188,7 +188,7 @@ BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL); */ static void pm1_handle_wake_pin(void *unused) { - const config_t *conf = config_of_path(SA_DEVFN_ROOT); + const config_t *conf = config_of_soc(); /* If WAKE# pin is enabled, bail out early. */ if (conf->deep_sx_config & DSX_EN_WAKE_PIN) diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 90f1b038e0..329cea9621 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -177,7 +177,7 @@ void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2) { DEVTREE_CONST struct soc_intel_skylake_config *config; - config = config_of_path(PCH_DEVFN_PMC); + config = config_of_soc(); /* Assign to out variable */ *dw0 = config->gpe0_dw0; diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index a8bbfb633d..f354af3442 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -43,7 +43,7 @@ void soc_pre_ram_init(struct romstage_params *params) /* Program MCHBAR and DMIBAR */ systemagent_early_init(); - config = config_of_path(PCH_DEVFN_LPC); + config = config_of_soc(); /* Force a full memory train if RMT is enabled */ params->disable_saved_data = config->Rmt; @@ -57,7 +57,7 @@ void soc_memory_init_params(struct romstage_params *params, /* Set the parameters for MemoryInit */ - config = config_of_path(PCH_DEVFN_LPC); + config = config_of_soc(); /* * Set IGD stolen size to 64MB. The FBC hardware for skylake does not diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index deda53312c..af89441194 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -289,7 +289,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig; - config = config_of_path(PCH_DEVFN_LPC); + config = config_of_soc(); soc_memory_init_params(m_cfg, config); soc_peg_init_params(m_cfg, m_t_cfg, config); diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c index 9b7ea2470e..bf0d5064e4 100644 --- a/src/soc/intel/skylake/romstage/systemagent.c +++ b/src/soc/intel/skylake/romstage/systemagent.c @@ -29,7 +29,7 @@ static void systemagent_vtd_init(void) const struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); const struct soc_intel_skylake_config *config = NULL; - config = config_of_path(SA_DEVFN_ROOT); + config = config_of_soc(); if (config->ignore_vtd) return; From 459f4934867a74e71868d3ea55f637782fd2f8cd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 28 Sep 2019 13:47:58 +0300 Subject: [PATCH 73/75] intel/baytrail: Replace config_of(dev) with config_of_soc() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The function does not otherwise need dev. Change-Id: I75d3283b537151258ed48f7e4e0991dff53a803c Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/35670 Reviewed-by: Furquan Shaikh Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/soc/intel/baytrail/romstage/pmc.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/soc/intel/baytrail/romstage/pmc.c b/src/soc/intel/baytrail/romstage/pmc.c index 882edf0a60..2eb3846c4f 100644 --- a/src/soc/intel/baytrail/romstage/pmc.c +++ b/src/soc/intel/baytrail/romstage/pmc.c @@ -41,13 +41,11 @@ void punit_init(void) { uint32_t reg; uint8_t rid; - const struct device *dev; const struct soc_intel_baytrail_config *cfg = NULL; rid = pci_read_config8(IOSF_PCI_DEV, REVID); - dev = pcidev_on_root(SOC_DEV, SOC_FUNC); - cfg = config_of(dev); + cfg = config_of_soc(); reg = iosf_punit_read(SB_BIOS_CONFIG); /* Write bits 17:16 of SB_BIOS_CONFIG in the PUNIT. */ From 86cb421df68f8c22b3cc27fb9ef45a6633724bb6 Mon Sep 17 00:00:00 2001 From: Thejaswani Putta Date: Fri, 20 Sep 2019 15:13:22 -0700 Subject: [PATCH 74/75] mb/google/drallion: Disable GBE in firmware for drallion variants BUG: None TEST: Build successful, checked the CBMEM log if 1f.6 is disabled with this patch Signed-off-by: Thejaswani Putta Change-Id: I4e74b259ce8f5f70833dce94692dcbe33e8504db Reviewed-on: https://review.coreboot.org/c/coreboot/+/35509 Reviewed-by: Mathew King Reviewed-by: Bora Guvendik Tested-by: build bot (Jenkins) --- src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb index f2367ffa1d..8cb1aa3001 100644 --- a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb +++ b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb @@ -417,6 +417,6 @@ chip soc/intel/cannonlake device pci 1f.3 on end # Intel HDA device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI - device pci 1f.6 on end # GbE + device pci 1f.6 off end # GbE end end From 3d4923d85ab07f8ea2b30018763c6bef269e5796 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 27 Sep 2019 00:02:25 -0700 Subject: [PATCH 75/75] libpayload: Add fmap_cache to sysinfo_t Now that FMAP is cached in CBMEM and its pointer is added to coreboot table for quick lookup, this change adds a new member "fmap_cache" to sysinfo_t that can be used by payloads to get to FMAP cache. BUG=b:141723751 Change-Id: If894c20c2de89a9d8564561bc7780c86f3f4135a Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/35640 Tested-by: build bot (Jenkins) Reviewed-by: Shelley Chen Reviewed-by: Patrick Rudolph Reviewed-by: Arthur Heymans Reviewed-by: Paul Menzel Reviewed-by: Aaron Durbin --- payloads/libpayload/include/coreboot_tables.h | 1 + payloads/libpayload/include/sysinfo.h | 3 +++ payloads/libpayload/libc/coreboot.c | 9 +++++++++ 3 files changed, 13 insertions(+) diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index bf2cf022d1..c24d6acfd6 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -78,6 +78,7 @@ enum { CB_TAG_VBOOT_WORKBUF = 0x0034, CB_TAG_MMC_INFO = 0x0035, CB_TAG_TCPA_LOG = 0x0036, + CB_TAG_FMAP = 0x0037, CB_TAG_CMOS_OPTION_TABLE = 0x00c8, CB_TAG_OPTION = 0x00c9, CB_TAG_OPTION_ENUM = 0x00ca, diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h index 50f0e3962c..c05be7c159 100644 --- a/payloads/libpayload/include/sysinfo.h +++ b/payloads/libpayload/include/sysinfo.h @@ -128,6 +128,9 @@ struct sysinfo_t { uint32_t mtc_size; void *chromeos_vpd; int mmc_early_wake_status; + + /* Pointer to FMAP cache in CBMEM */ + void *fmap_cache; }; extern struct sysinfo_t lib_sysinfo; diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index 03778b6d2a..e14b144ee4 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -239,6 +239,12 @@ static void cb_parse_vpd(void *ptr, struct sysinfo_t *info) info->chromeos_vpd = phys_to_virt(cbmem->cbmem_tab); } +static void cb_parse_fmap_cache(void *ptr, struct sysinfo_t *info) +{ + struct cb_cbmem_tab *const cbmem = (struct cb_cbmem_tab *)ptr; + info->fmap_cache = phys_to_virt(cbmem->cbmem_tab); +} + #if CONFIG(LP_TIMER_RDTSC) static void cb_parse_tsc_info(void *ptr, struct sysinfo_t *info) { @@ -412,6 +418,9 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info) case CB_TAG_VPD: cb_parse_vpd(ptr, info); break; + case CB_TAG_FMAP: + cb_parse_fmap_cache(ptr, info); + break; default: cb_parse_arch_specific(rec, info); break;