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nb/intel/gm45: Add more DMIBAR/EPBAR registers

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Add definitions for more DMIBAR/EPBAR registers, and specify their sizes
as well. Also, expand a comment as the registers' purpose is now known.

Tested with BUILD_TIMELESS=1, Roda RK9 does not change.

Change-Id: I9687d34e0663e70bdd2a1aa682246c2448690e18
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45448
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
2020-09-16 12:50:59 +02:00
parent 6642b44b29
commit 3e33be2e69
3 changed files with 77 additions and 42 deletions
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8
src/northbridge/intel/gm45/raminit.c
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@@ -1128,7 +1128,7 @@ static void clock_crossing_setup(const fsb_clock_t fsb,
}
}
/* Program egress VC1 timings. */
/* Program egress VC1 isoch timings. */
static void vc1_program_timings(const fsb_clock_t fsb)
{
const u32 timings_by_fsb[][2] = {
@@ -1136,9 +1136,9 @@ static void vc1_program_timings(const fsb_clock_t fsb)
/* FSB 800MHz */ { 0x14, 0x00f000f0 },
/* FSB 667MHz */ { 0x10, 0x00c000c0 },
};
EPBAR8(0x2c) = timings_by_fsb[fsb][0];
EPBAR32(0x38) = timings_by_fsb[fsb][1];
EPBAR32(0x3c) = timings_by_fsb[fsb][1];
EPBAR8(EPVC1ITC) = timings_by_fsb[fsb][0];
EPBAR32(EPVC1IST + 0) = timings_by_fsb[fsb][1];
EPBAR32(EPVC1IST + 4) = timings_by_fsb[fsb][1];
}
#define DEFAULT_PCI_MMIO_SIZE 2048