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soc/intel/common: Restrict common romstage/ramstage code to FSP

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Restrict the use of the common romstage/ramstage code to FSP 1.1

BRANCH=none
BUG=None
TEST=Build and run on cyan/sklrvp

Change-Id: Ifbdb6b4c201560a97617e83d69bf9974f9411994
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10653
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Lee Leahy
2015-06-24 11:17:54 -07:00
committed by Leroy P Leahy
parent fbe276b96f
commit 3e5bc1feab
3 changed files with 12 additions and 28 deletions
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4
src/soc/intel/common/Kconfig
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@@ -73,18 +73,22 @@ config SOC_INTEL_COMMON_FSP_RAM_INIT
config SOC_INTEL_COMMON_FSP_ROMSTAGE
bool
default n
depends on PLATFORM_USES_FSP1_1
config SOC_INTEL_COMMON_RESET
bool
default n
depends on PLATFORM_USES_FSP1_1
config SOC_INTEL_COMMON_STACK
bool
default n
depends on PLATFORM_USES_FSP1_1
config SOC_INTEL_COMMON_STAGE_CACHE
bool
default n
depends on PLATFORM_USES_FSP1_1
config ROMSTAGE_RAM_STACK_SIZE
hex "Size of the romstage RAM stack in bytes"