sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/{amd, intel}: Make use of common postcar_enable_tseg_cache() API

Browse Source 
This patch removes dedicated function call to make TSEG region cache
from soc and refers to postcar_enable_tseg_cache().

BUG=b:140008206

Change-Id: I18a032b43a2093c8ae86735c119d8dfee40570b1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Subrata Banik
2019-09-10 15:51:17 +05:30
parent b3426c03b4
commit 3eff037f8c
5 changed files with 10 additions and 55 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
src/soc/intel/skylake/memmap.c
View File

@@ -296,8 +296,6 @@ void *cbmem_top(void)
void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
uintptr_t smm_base;
size_t smm_size;
/*
* We need to make sure ramstage will be run cached. At this
@@ -310,14 +308,7 @@ void fill_postcar_frame(struct postcar_frame *pcf)
top_of_ram -= 16*MiB;
postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
/*
* Cache the TSEG region at the top of ram. This region is
* not restricted to SMM mode until SMM has been relocated.
* By setting the region to cacheable it provides faster access
* when relocating the SMM handler as well as using the TSEG
* region for other purposes.
*/
smm_region(&smm_base, &smm_size);
postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK);
/* Cache the TSEG region */
postcar_enable_tseg_cache(pcf);
}
#endif