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soc/amd/*/include/msr: add version number to SERIAL_VID_* define names

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Picasso and Cezanne use the serial voltage ID 2 standard to communicate
the CPU voltage to the voltage regulator module on the mainboard, while
Mendocino, Phoenix and Glinda use the serial voltage ID 3 standard for
this. Both standards encode the voltage in a different way, so add the
serial VID version number to the defines to clarify for which version
the define is.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8ddab8df27c86dc2c70a6dfb47908d9405d86240
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73994
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
This commit is contained in:
Felix Held
2023-03-23 23:05:50 +01:00
parent 6a6d524b0a
commit 3f2844fb1e
10 changed files with 20 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/soc/amd/cezanne/acpi.c
View File

@@ -150,8 +150,8 @@ uint32_t get_pstate_core_power(union pstate_msr pstate_reg)
/* Voltage off for VID codes 0xF8 to 0xFF */
voltage_in_uvolts = 0;
} else {
voltage_in_uvolts =
SERIAL_VID_MAX_MICROVOLTS - (SERIAL_VID_DECODE_MICROVOLTS * core_vid);
voltage_in_uvolts = SERIAL_VID_2_MAX_MICROVOLTS -
(SERIAL_VID_2_DECODE_MICROVOLTS * core_vid);
}
/* Power in mW */

4
src/soc/amd/cezanne/include/soc/msr.h
View File

@@ -23,8 +23,8 @@ union pstate_msr {
#define PSTATE_DEF_CORE_FREQ_BASE 25
/* Value defined in Serial VID Interface 2.0 spec (#48022, NDA only) */
#define SERIAL_VID_DECODE_MICROVOLTS 6250
#define SERIAL_VID_MAX_MICROVOLTS 1550000L
#define SERIAL_VID_2_DECODE_MICROVOLTS 6250
#define SERIAL_VID_2_MAX_MICROVOLTS 1550000L
#define MSR_CPPC_CAPABILITY_1 0xc00102b0
#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24

4
src/soc/amd/glinda/acpi.c
View File

@@ -127,8 +127,8 @@ uint32_t get_pstate_core_power(union pstate_msr pstate_reg)
/* Voltage off for VID code 0x00 */
voltage_in_uvolts = 0;
} else {
voltage_in_uvolts =
SERIAL_VID_BASE_MICROVOLTS + (SERIAL_VID_DECODE_MICROVOLTS * core_vid);
voltage_in_uvolts = SERIAL_VID_3_BASE_MICROVOLTS +
(SERIAL_VID_3_DECODE_MICROVOLTS * core_vid);
}
/* Power in mW */

4
src/soc/amd/glinda/include/soc/msr.h
View File

@@ -23,8 +23,8 @@ union pstate_msr {
#define PSTATE_DEF_CORE_FREQ_BASE 5
/* Value defined in Serial VID Interface 3.0 spec (#56413, NDA only) */
#define SERIAL_VID_DECODE_MICROVOLTS 5000
#define SERIAL_VID_BASE_MICROVOLTS 245000L
#define SERIAL_VID_3_DECODE_MICROVOLTS 5000
#define SERIAL_VID_3_BASE_MICROVOLTS 245000L
#define MSR_CPPC_CAPABILITY_1 0xc00102b0
#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24

4
src/soc/amd/mendocino/acpi.c
View File

@@ -152,8 +152,8 @@ uint32_t get_pstate_core_power(union pstate_msr pstate_reg)
/* Voltage off for VID code 0x00 */
voltage_in_uvolts = 0;
} else {
voltage_in_uvolts =
SERIAL_VID_BASE_MICROVOLTS + (SERIAL_VID_DECODE_MICROVOLTS * core_vid);
voltage_in_uvolts = SERIAL_VID_3_BASE_MICROVOLTS +
(SERIAL_VID_3_DECODE_MICROVOLTS * core_vid);
}
/* Power in mW */

4
src/soc/amd/mendocino/include/soc/msr.h
View File

@@ -24,8 +24,8 @@ union pstate_msr {
#define PSTATE_DEF_CORE_FREQ_BASE 25
/* Value defined in Serial VID Interface 3.0 spec (#56413, NDA only) */
#define SERIAL_VID_DECODE_MICROVOLTS 5000
#define SERIAL_VID_BASE_MICROVOLTS 245000L
#define SERIAL_VID_3_DECODE_MICROVOLTS 5000
#define SERIAL_VID_3_BASE_MICROVOLTS 245000L
#define MSR_CPPC_CAPABILITY_1 0xc00102b0
#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24

4
src/soc/amd/phoenix/acpi.c
View File

@@ -153,8 +153,8 @@ uint32_t get_pstate_core_power(union pstate_msr pstate_reg)
/* Voltage off for VID code 0x00 */
voltage_in_uvolts = 0;
} else {
voltage_in_uvolts =
SERIAL_VID_BASE_MICROVOLTS + (SERIAL_VID_DECODE_MICROVOLTS * core_vid);
voltage_in_uvolts = SERIAL_VID_3_BASE_MICROVOLTS +
(SERIAL_VID_3_DECODE_MICROVOLTS * core_vid);
}
/* Power in mW */

4
src/soc/amd/phoenix/include/soc/msr.h
View File

@@ -26,8 +26,8 @@ union pstate_msr {
#define PSTATE_DEF_CORE_FREQ_BASE 25
/* Value defined in Serial VID Interface 3.0 spec (#56413, NDA only) */
#define SERIAL_VID_DECODE_MICROVOLTS 5000
#define SERIAL_VID_BASE_MICROVOLTS 245000L
#define SERIAL_VID_3_DECODE_MICROVOLTS 5000
#define SERIAL_VID_3_BASE_MICROVOLTS 245000L
#define MSR_CPPC_CAPABILITY_1 0xc00102b0
#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24

4
src/soc/amd/picasso/acpi.c
View File

@@ -154,8 +154,8 @@ uint32_t get_pstate_core_power(union pstate_msr pstate_reg)
/* Voltage off for VID codes 0xF8 to 0xFF */
voltage_in_uvolts = 0;
} else {
voltage_in_uvolts =
SERIAL_VID_MAX_MICROVOLTS - (SERIAL_VID_DECODE_MICROVOLTS * core_vid);
voltage_in_uvolts = SERIAL_VID_2_MAX_MICROVOLTS -
(SERIAL_VID_2_DECODE_MICROVOLTS * core_vid);
}
/* Power in mW */

4
src/soc/amd/picasso/include/soc/msr.h
View File

@@ -27,7 +27,7 @@ union pstate_msr {
#define PSTATE_DEF_CORE_FREQ_BASE 25
/* Value defined in Serial VID Interface 2.0 spec (#48022, NDA only) */
#define SERIAL_VID_DECODE_MICROVOLTS 6250
#define SERIAL_VID_MAX_MICROVOLTS 1550000L
#define SERIAL_VID_2_DECODE_MICROVOLTS 6250
#define SERIAL_VID_2_MAX_MICROVOLTS 1550000L
#endif /* AMD_PICASSO_MSR_H */