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purism/librem_skl: Add AC/DC LoadLine to VR Config

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The FSP 2.0 needs to set the ac_loadline and dc_loadline for
each VR config. Without it, the Loadline is considered to be
0 mOhm and this causes CPU temp to jump all over the place
whenever the CPU is used.

This is necessary since there are no VR_CONFIG icc mappings for
Skylake SKUs, only KabyLake.

These values were copied from the Google Poppy devicetree.

Change-Id: I6aeb6ee521988b94f2ae94a60d1a28b87ba984d4
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/25324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Youness Alaoui
2018-03-20 18:32:23 -04:00
committed by Patrick Georgi
parent cb8f04dc83
commit 3f42a26b42
2 changed files with 50 additions and 30 deletions
Download Patch File Download Diff File Expand all files Collapse all files

40
src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
View File

@@ -31,8 +31,8 @@ chip soc/intel/skylake
# Enable "Intel Speed Shift Technology" # Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1" register "speed_shift_enable" = "1"
# Enable DPTF # Disable DPTF
register "dptf_enable" = "1" register "dptf_enable" = "0"
# FSP Configuration # FSP Configuration
register "ProbelessTrace" = "0" register "ProbelessTrace" = "0"
@@ -81,19 +81,21 @@ chip soc/intel/skylake
register "pirqh_routing" = "PCH_IRQ11" register "pirqh_routing" = "PCH_IRQ11"
# VR Settings Configuration for 4 Domains # VR Settings Configuration for 4 Domains
#+----------------+-------+-------+-------------+-------+ #+----------------+-----------+-----------+-------------+----------+
#| Domain/Setting | SA | IA | GT Unsliced | GT | #| Domain/Setting | SA | IA | GT Unsliced | GT |
#+----------------+-------+-------+-------------+-------+ #+----------------+-----------+-----------+-------------+----------+
#| Psi1Threshold | 20A | 20A | 20A | 20A | #| Psi1Threshold | 20A | 20A | 20A | 20A |
#| Psi2Threshold | 4A | 5A | 5A | 5A | #| Psi2Threshold | 4A | 5A | 5A | 5A |
#| Psi3Threshold | 1A | 1A | 1A | 1A | #| Psi3Threshold | 1A | 1A | 1A | 1A |
#| Psi3Enable | 1 | 1 | 1 | 1 | #| Psi3Enable | 1 | 1 | 1 | 1 |
#| Psi4Enable | 1 | 1 | 1 | 1 | #| Psi4Enable | 1 | 1 | 1 | 1 |
#| ImonSlope | 0 | 0 | 0 | 0 | #| ImonSlope | 0 | 0 | 0 | 0 |
#| ImonOffset | 0 | 0 | 0 | 0 | #| ImonOffset | 0 | 0 | 0 | 0 |
#| IccMax | 7A | 34A | 35A | 35A | #| IccMax | 7A | 34A | 35A | 35A |
#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
#+----------------+-------+-------+-------------+-------+ #| AC LoadLine | 15 mOhm | 5.7 mOhm | 5.2 mOhm | 5.2 mOhm |
#| DC LoadLine | 14.3 mOhm | 4.83 mOhm | 4.2 mOhm | 4.2 mOhm |
#+----------------+-----------+-----------+-------------+----------+
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
.vr_config_enable = 1, .vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20), .psi1threshold = VR_CFG_AMP(20),
@@ -105,6 +107,8 @@ chip soc/intel/skylake
.imon_offset = 0x0, .imon_offset = 0x0,
.icc_max = VR_CFG_AMP(7), .icc_max = VR_CFG_AMP(7),
.voltage_limit = 1520, .voltage_limit = 1520,
.ac_loadline = 1500,
.dc_loadline = 1430,
}" }"
register "domain_vr_config[VR_IA_CORE]" = "{ register "domain_vr_config[VR_IA_CORE]" = "{
@@ -118,6 +122,8 @@ chip soc/intel/skylake
.imon_offset = 0x0, .imon_offset = 0x0,
.icc_max = VR_CFG_AMP(34), .icc_max = VR_CFG_AMP(34),
.voltage_limit = 1520, .voltage_limit = 1520,
.ac_loadline = 570,
.dc_loadline = 483,
}" }"
register "domain_vr_config[VR_GT_UNSLICED]" = "{ register "domain_vr_config[VR_GT_UNSLICED]" = "{
@@ -131,6 +137,8 @@ chip soc/intel/skylake
.imon_offset = 0x0, .imon_offset = 0x0,
.icc_max = VR_CFG_AMP(35), .icc_max = VR_CFG_AMP(35),
.voltage_limit = 1520, .voltage_limit = 1520,
.ac_loadline = 520,
.dc_loadline = 420,
}" }"
register "domain_vr_config[VR_GT_SLICED]" = "{ register "domain_vr_config[VR_GT_SLICED]" = "{
@@ -144,6 +152,8 @@ chip soc/intel/skylake
.imon_offset = 0x0, .imon_offset = 0x0,
.icc_max = VR_CFG_AMP(35), .icc_max = VR_CFG_AMP(35),
.voltage_limit = 1520, .voltage_limit = 1520,
.ac_loadline = 520,
.dc_loadline = 420,
}" }"
# Enable Root Ports 5 and 9 # Enable Root Ports 5 and 9

40
src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
View File

@@ -31,8 +31,8 @@ chip soc/intel/skylake
# Enable "Intel Speed Shift Technology" # Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1" register "speed_shift_enable" = "1"
# Enable DPTF # Disable DPTF
register "dptf_enable" = "1" register "dptf_enable" = "0"
# FSP Configuration # FSP Configuration
register "ProbelessTrace" = "0" register "ProbelessTrace" = "0"
@@ -81,19 +81,21 @@ chip soc/intel/skylake
register "pirqh_routing" = "PCH_IRQ11" register "pirqh_routing" = "PCH_IRQ11"
# VR Settings Configuration for 4 Domains # VR Settings Configuration for 4 Domains
#+----------------+-------+-------+-------------+-------+ #+----------------+-----------+-----------+-------------+----------+
#| Domain/Setting | SA | IA | GT Unsliced | GT | #| Domain/Setting | SA | IA | GT Unsliced | GT |
#+----------------+-------+-------+-------------+-------+ #+----------------+-----------+-----------+-------------+----------+
#| Psi1Threshold | 20A | 20A | 20A | 20A | #| Psi1Threshold | 20A | 20A | 20A | 20A |
#| Psi2Threshold | 4A | 5A | 5A | 5A | #| Psi2Threshold | 4A | 5A | 5A | 5A |
#| Psi3Threshold | 1A | 1A | 1A | 1A | #| Psi3Threshold | 1A | 1A | 1A | 1A |
#| Psi3Enable | 1 | 1 | 1 | 1 | #| Psi3Enable | 1 | 1 | 1 | 1 |
#| Psi4Enable | 1 | 1 | 1 | 1 | #| Psi4Enable | 1 | 1 | 1 | 1 |
#| ImonSlope | 0 | 0 | 0 | 0 | #| ImonSlope | 0 | 0 | 0 | 0 |
#| ImonOffset | 0 | 0 | 0 | 0 | #| ImonOffset | 0 | 0 | 0 | 0 |
#| IccMax | 7A | 34A | 35A | 35A | #| IccMax | 7A | 34A | 35A | 35A |
#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
#+----------------+-------+-------+-------------+-------+ #| AC LoadLine | 15 mOhm | 5.7 mOhm | 5.2 mOhm | 5.2 mOhm |
#| DC LoadLine | 14.3 mOhm | 4.83 mOhm | 4.2 mOhm | 4.2 mOhm |
#+----------------+-----------+-----------+-------------+----------+
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
.vr_config_enable = 1, .vr_config_enable = 1,
.psi1threshold = VR_CFG_AMP(20), .psi1threshold = VR_CFG_AMP(20),
@@ -105,6 +107,8 @@ chip soc/intel/skylake
.imon_offset = 0x0, .imon_offset = 0x0,
.icc_max = VR_CFG_AMP(7), .icc_max = VR_CFG_AMP(7),
.voltage_limit = 1520, .voltage_limit = 1520,
.ac_loadline = 1500,
.dc_loadline = 1430,
}" }"
register "domain_vr_config[VR_IA_CORE]" = "{ register "domain_vr_config[VR_IA_CORE]" = "{
@@ -118,6 +122,8 @@ chip soc/intel/skylake
.imon_offset = 0x0, .imon_offset = 0x0,
.icc_max = VR_CFG_AMP(34), .icc_max = VR_CFG_AMP(34),
.voltage_limit = 1520, .voltage_limit = 1520,
.ac_loadline = 570,
.dc_loadline = 483,
}" }"
register "domain_vr_config[VR_GT_UNSLICED]" = "{ register "domain_vr_config[VR_GT_UNSLICED]" = "{
@@ -131,6 +137,8 @@ chip soc/intel/skylake
.imon_offset = 0x0, .imon_offset = 0x0,
.icc_max = VR_CFG_AMP(35), .icc_max = VR_CFG_AMP(35),
.voltage_limit = 1520, .voltage_limit = 1520,
.ac_loadline = 520,
.dc_loadline = 420,
}" }"
register "domain_vr_config[VR_GT_SLICED]" = "{ register "domain_vr_config[VR_GT_SLICED]" = "{
@@ -144,6 +152,8 @@ chip soc/intel/skylake
.imon_offset = 0x0, .imon_offset = 0x0,
.icc_max = VR_CFG_AMP(35), .icc_max = VR_CFG_AMP(35),
.voltage_limit = 1520, .voltage_limit = 1520,
.ac_loadline = 520,
.dc_loadline = 420,
}" }"
# Enable Root Ports 5 and 9 # Enable Root Ports 5 and 9