Drop prototype guarding for romcc
Commit "romcc: Don't fail on function prototypes" (11a7db3b) [1]
made romcc not choke on function prototypes anymore. This
allows us to get rid of a lot of ifdefs guarding __ROMCC__ .
[1] http://review.coreboot.org/2424
Change-Id: Ib1be3b294e5b49f5101f2e02ee1473809109c8ac
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3216
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
committed by
Ronald G. Minnich
parent
d654f42e27
commit
3f5f6d8368
@@ -1,5 +1,3 @@
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#ifndef _NE2K_H__
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#define _NE2K_H__
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/*
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* This file is part of the coreboot project.
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*
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@@ -19,9 +17,9 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __ROMCC__
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#ifndef _NE2K_H__
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#define _NE2K_H__
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void ne2k_append_data(unsigned char *d, int len, unsigned int base);
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int ne2k_init(unsigned int eth_nic_base);
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void ne2k_transmit(unsigned int eth_nic_base);
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#endif
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#endif /* _NE2K_H */
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@@ -511,7 +511,7 @@
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#define PMLogic_BASE (0x9D00)
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#if !defined(__ROMCC__) && !defined(__ASSEMBLER__)
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#if !defined(__ASSEMBLER__)
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#if defined(__PRE_RAM__)
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void cpuRegInit(void);
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void SystemPreInit(void);
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@@ -630,7 +630,7 @@
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#define DELAY_UPPER_DISABLE_CLK135 (1 << 23)
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#define DELAY_LOWER_STATUS_MASK 0x7C0
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#if !defined(__ROMCC__) && !defined(__ASSEMBLER__)
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#if !defined(__ASSEMBLER__)
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#if defined(__PRE_RAM__)
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void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated);
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void SystemPreInit(void);
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@@ -105,9 +105,7 @@ typedef struct {
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int num_states;
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} sst_table_t;
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#ifndef __ROMCC__
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void speedstep_gen_pstates(sst_table_t *);
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#endif
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#define SPEEDSTEP_MAX_POWER_YONAH 31000
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#define SPEEDSTEP_MIN_POWER_YONAH 13100
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@@ -51,7 +51,6 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void)
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return lapic_read(LAPIC_ID) >> 24;
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}
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#ifndef __ROMCC__
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#if !CONFIG_AP_IN_SIPI_WAIT
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/* If we need to go back to sipi wait, we use the long non-inlined version of
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* this function in lapic_cpu_init.c
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@@ -155,6 +154,5 @@ int start_cpu(struct device *cpu);
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#endif /* !__PRE_RAM__ */
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int boot_cpu(void);
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#endif
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#endif /* CPU_X86_LAPIC_H */
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@@ -1,8 +1,6 @@
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#ifndef DELAY_H
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#define DELAY_H
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#if !defined( __ROMCC__)
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#if CONFIG_HAVE_INIT_TIMER
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void init_timer(void);
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#else
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@@ -12,6 +10,4 @@ void init_timer(void);
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void udelay(unsigned usecs);
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void mdelay(unsigned msecs);
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void delay(unsigned secs);
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#endif
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#endif /* DELAY_H */
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@@ -25,7 +25,6 @@
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#define EHCI_BAR_INDEX 0x10
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#ifndef __ROMCC__
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/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
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/* Section 2.2 Host Controller Capability Registers */
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@@ -201,4 +200,3 @@ struct ehci_dbg_port {
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#define DBGP_EPADDR(dev, ep) (((dev)<<8)|(ep))
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} __attribute__ ((packed));
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#endif
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#endif
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@@ -1,8 +1,5 @@
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#ifndef IP_CHECKSUM_H
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#define IP_CHECKSUM_H
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#ifndef __ROMCC__
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unsigned long compute_ip_checksum(void *addr, unsigned long length);
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unsigned long add_ip_checksums(unsigned long offset, unsigned long sum, unsigned long new);
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#endif
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#endif /* IP_CHECKSUM_H */
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@@ -22,7 +22,6 @@
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#ifndef __LIB_H__
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#define __LIB_H__
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#include <stdint.h>
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#ifndef __ROMCC__ /* romcc doesn't support prototypes. */
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#ifndef __PRE_RAM__ /* Conflicts with inline function in arch/io.h */
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/* Defined in src/lib/clog2.c */
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@@ -43,8 +42,10 @@ void quick_ram_check(void);
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/* Defined in src/lib/stack.c */
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int checkstack(void *top_of_stack, int core);
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#ifndef __PRE_RAM__ // fails in bootblock compiled with romcc
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/* currently defined by a ldscript */
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extern unsigned char _estack[];
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#endif
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/* Defined in romstage.c */
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#if CONFIG_CPU_AMD_GEODE_LX
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@@ -53,5 +54,4 @@ void cache_as_ram_main(void);
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
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#endif
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#endif /* __ROMCC__ */
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#endif /* __LIB_H__ */
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@@ -58,7 +58,5 @@
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#define PPCB_SPKR 0x02 /* Bit 1 */
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#define PPCB_T2GATE 0x01 /* Bit 0 */
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#ifndef __ROMCC__
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void setup_i8254(void);
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#endif
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#endif
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@@ -203,9 +203,7 @@ static inline int get_option(void *dest __attribute__((unused)),
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#define CMOS_POST_BANK_1_MAGIC 0x81
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#define CMOS_POST_BANK_1_OFFSET (CMOS_POST_OFFSET + 2)
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#if !defined(__ROMCC__)
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void cmos_post_log(void);
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#endif
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#endif /* CONFIG_CMOS_POST */
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#endif /* PC80_MC146818RTC_H */
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@@ -1,9 +1,6 @@
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#ifndef RESET_H
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#define RESET_H
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#if !defined( __ROMCC__ )
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/* ROMCC can't do function prototypes... */
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#if CONFIG_HAVE_HARD_RESET
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void hard_reset(void);
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#else
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@@ -12,4 +9,3 @@ void hard_reset(void);
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void soft_reset(void);
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#endif
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#endif
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@@ -30,7 +30,7 @@
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#include <uart8250.h>
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#endif
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#if !defined(__ROMCC__) && CONFIG_CONSOLE_SERIAL_UART
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#if CONFIG_CONSOLE_SERIAL_UART
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unsigned char uart_rx_byte(void);
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void uart_tx_byte(unsigned char data);
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void uart_tx_flush(void);
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@@ -114,7 +114,6 @@
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/* Line Control Settings */
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#define UART_LCS CONFIG_TTYS0_LCS
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#ifndef __ROMCC__
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#if CONFIG_CONSOLE_SERIAL8250
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unsigned char uart8250_rx_byte(unsigned base_port);
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int uart8250_can_rx_byte(unsigned base_port);
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@@ -145,8 +144,6 @@ void oxford_init(void);
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#endif
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#endif
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#endif /* __ROMCC__ */
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#endif /* CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM */
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#endif /* UART8250_H */
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@@ -34,7 +34,6 @@ struct ehci_debug_info {
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u8 bufidx;
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};
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#ifndef __ROMCC__
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void enable_usbdebug(unsigned int port);
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int dbgp_bulk_write_x(struct ehci_debug_info *dbg_info, const char *bytes, int size);
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int dbgp_bulk_read_x(struct ehci_debug_info *dbg_info, void *data, int size);
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@@ -47,4 +46,3 @@ void usbdebug_tx_byte(struct ehci_debug_info *info, unsigned char data);
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void usbdebug_tx_flush(struct ehci_debug_info *info);
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int usbdebug_init(unsigned ehci_bar, unsigned offset, struct ehci_debug_info *info);
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#endif
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#endif
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