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mb/google/skyrim: Fix eSPI configuration

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* Use GPE 24 since it doesn't conflict with any existing GEVENTS.
* Remove IRQ 12 mapping since it's not used.
* Unmask IRQ1 in PM registers.
* Use the new SMITYPE_ESPI_SCI_B SCI.

BUG=b:227282870
TEST=Build and boot to OS in Skyrim.

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7e9816d67500365ed1d2ee39ef184a1f60321ca1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Jon Murphy
2022-04-18 13:19:23 -06:00
committed by Felix Held
parent 5a5de338e6
commit 3f62507de0
4 changed files with 9 additions and 4 deletions
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4
src/mainboard/google/skyrim/ec.c
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@@ -10,8 +10,8 @@
static const struct sci_source espi_sci_sources[] = { static const struct sci_source espi_sci_sources[] = {
{ {
.scimap = SMITYPE_ESPI_SYS, .scimap = SMITYPE_ESPI_SCI_B,
.gpe = GEVENT_3, .gpe = EC_SCI_GPI,
.direction = SMI_SCI_LVL_HIGH, /* enum smi_sci_lvl */ .direction = SMI_SCI_LVL_HIGH, /* enum smi_sci_lvl */
.level = SMI_SCI_EDG, /* enum smi_sci_dir */ .level = SMI_SCI_EDG, /* enum smi_sci_dir */
} }

5
src/mainboard/google/skyrim/mainboard.c
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@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */ /* SPDX-License-Identifier: GPL-2.0-or-later */
#include <amdblocks/acpimmio.h>
#include <amdblocks/amd_pci_util.h> #include <amdblocks/amd_pci_util.h>
#include <baseboard/variants.h> #include <baseboard/variants.h>
#include <console/console.h> #include <console/console.h>
@@ -111,6 +112,10 @@ static void mainboard_enable(struct device *dev)
init_tables(); init_tables();
/* Initialize the PIRQ data structures for consumption */ /* Initialize the PIRQ data structures for consumption */
pirq_setup(); pirq_setup();
/* TODO: b/184678786 - Move into espi_config */
/* Unmask eSPI IRQ 1 (Keyboard) */
pm_write32(PM_ESPI_INTR_CTRL, PM_ESPI_DEV_INTR_MASK & ~(BIT(1)));
} }
struct chip_operations mainboard_ops = { struct chip_operations mainboard_ops = {

2
src/mainboard/google/skyrim/variants/baseboard/devicetree.cb
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@@ -35,7 +35,7 @@ chip soc/amd/sabrina
.oob_ch_en = 0, .oob_ch_en = 0,
.flash_ch_en = 0, .flash_ch_en = 0,
.vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1) | ESPI_VW_IRQ_LEVEL_HIGH(12), .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1),
}" }"
register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL |

2
src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h
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@@ -52,7 +52,7 @@
*/ */
/* Set GPI for SCI */ /* Set GPI for SCI */
#define EC_SCI_GPI GEVENT_3 /* eSPI system event -> GPE 3 */ #define EC_SCI_GPI GEVENT_24 /* eSPI system event -> GPE 24 */
/* Enable LID switch and provide wake pin for EC */ /* Enable LID switch and provide wake pin for EC */
#define EC_ENABLE_LID_SWITCH #define EC_ENABLE_LID_SWITCH