sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/common/block/gpio: Change group offset calculation

Browse Source 
Add group information for each gpio community and use it to
calculate offset of a pad within its group. Original implementation
assumed that the number of gpios in each group is same but that lead to
a bug for cnl since numbers differ for each group.

BUG=b:69616750
TEST=Need to test again on SKL,CNL,APL,GLK

Change-Id: I02ab1d878bc83d32222be074bd2db5e23adaf580
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/22571
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Bora Guvendik
2017-11-22 13:48:12 -08:00
committed by Aaron Durbin
parent 7e2fe06a46
commit 3f672323b5
6 changed files with 185 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

41
src/soc/intel/skylake/gpio.c
View File

@ -20,6 +20,7 @@
#include <soc/pcr_ids.h>
#include <soc/pm.h>
static const struct reset_mapping rst_map[] = {
{ .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30},
{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30},
@ -33,6 +34,38 @@ static const struct reset_mapping rst_map_com2[] = {
{ .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30},
};
static const struct pad_group skl_community_com0_groups[] = {
INTEL_GPP(GPP_A0, GPP_A0, GPP_A23), /* GPP A */
INTEL_GPP(GPP_A0, GPP_B0, GPP_B23), /* GPP B */
};
static const struct pad_group skl_community_com1_groups[] = {
INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP C */
#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H)
INTEL_GPP(GPP_C0, GPP_D0, GPP_D23), /* GPP D */
INTEL_GPP(GPP_C0, GPP_E0, GPP_E12), /* GPP E */
INTEL_GPP(GPP_C0, GPP_F0, GPP_F23), /* GPP F */
INTEL_GPP(GPP_C0, GPP_G0, GPP_G23), /* GPP G */
INTEL_GPP(GPP_C0, GPP_H0, GPP_H23), /* GPP H */
#else
INTEL_GPP(GPP_C0, GPP_D0, GPP_D23), /* GPP D */
INTEL_GPP(GPP_C0, GPP_E0, GPP_E23), /* GPP E */
#endif
};
static const struct pad_group skl_community_com3_groups[] = {
#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H)
INTEL_GPP(GPP_I0, GPP_I0, GPP_I10), /* GPP I */
#else
INTEL_GPP(GPP_F0, GPP_F0, GPP_F23), /* GPP F */
INTEL_GPP(GPP_F0, GPP_G0, GPP_G7), /* GPP G */
#endif
};
static const struct pad_group skl_community_com2_groups[] = {
INTEL_GPP(GPD0, GPD0, GPD11), /* GPP GDP */
};
static const struct pad_community skl_gpio_communities[] = {
{
.port = PID_GPIOCOM0,
@ -48,6 +81,8 @@ static const struct pad_community skl_gpio_communities[] = {
.acpi_path = "\\_SB.PCI0.GPIO",
.reset_map = rst_map,
.num_reset_vals = ARRAY_SIZE(rst_map),
.groups = skl_community_com0_groups,
.num_groups = ARRAY_SIZE(skl_community_com0_groups),
}, {
.port = PID_GPIOCOM1,
.first_pad = GPP_C0,
@ -66,6 +101,8 @@ static const struct pad_community skl_gpio_communities[] = {
.acpi_path = "\\_SB.PCI0.GPIO",
.reset_map = rst_map,
.num_reset_vals = ARRAY_SIZE(rst_map),
.groups = skl_community_com1_groups,
.num_groups = ARRAY_SIZE(skl_community_com1_groups),
}, {
.port = PID_GPIOCOM3,
#if IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H)
@ -85,6 +122,8 @@ static const struct pad_community skl_gpio_communities[] = {
.acpi_path = "\\_SB.PCI0.GPIO",
.reset_map = rst_map,
.num_reset_vals = ARRAY_SIZE(rst_map),
.groups = skl_community_com3_groups,
.num_groups = ARRAY_SIZE(skl_community_com3_groups),
}, {
.port = PID_GPIOCOM2,
.first_pad = GPD0,
@ -99,6 +138,8 @@ static const struct pad_community skl_gpio_communities[] = {
.acpi_path = "\\_SB.PCI0.GPIO",
.reset_map = rst_map_com2,
.num_reset_vals = ARRAY_SIZE(rst_map_com2),
.groups = skl_community_com2_groups,
.num_groups = ARRAY_SIZE(skl_community_com2_groups),
}
};