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Merge remote-tracking branch 'upstream/master' into system76

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Jeremy Soller 2020-01-27 12:28:25 -07:00
commit 3f76a2ec4c
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65 changed files with 2116 additions and 722 deletions
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2
3rdparty/vboot vendored

@ -1 +1 @@
Subproject commit 2843aa62ba7bcaab2abccf16e3f1b8bd7e058fdb
Subproject commit f5367d598a985520a8c935f68ac90d295c7b8d8e

1
Documentation/mainboard/index.md
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@ -13,6 +13,7 @@ This section contains documentation about coreboot on specific mainboards.
## ASUS
- [F2A85-M](asus/f2a85-m.md)
- [P5Q](asus/p5q.md)
- [P8H61-M LX](asus/p8h61-m_lx.md)
- [P8H61-M Pro](asus/p8h61-m_pro.md)
- [P8Z77-M Pro](asus/p8z77-m_pro.md)

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5
Documentation/mainboard/system76/lemp9.md
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@ -1,4 +1,3 @@
# System76 Lemur Pro (lemp9)
## Specs
@ -19,8 +18,8 @@
- HDMI video
- USB-C DisplayPort video
- Memory
- 8-GB DDR4 Samsung K4AAG165WA-BCTD (Channel 0)
- 8-GB/16-GB/32-GB DDR4 SO-DIMM (Channel 1)
- Channel 0: 8-GB on-board DDR4 Samsung K4AAG165WA-BCTD
- Channel 1: 8-GB/16-GB/32-GB DDR4 SO-DIMM
- Networking
- M.2 PCIe/CNVi WiFi/Bluetooth
- Sound

3
configs/config.asus_p2b_ramdebug Normal file
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@ -0,0 +1,3 @@
CONFIG_VENDOR_ASUS=y
CONFIG_BOARD_ASUS_P2B=y
CONFIG_DEBUG_RAM_SETUP=y

4
src/Kconfig
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@ -1087,10 +1087,6 @@ endmenu
source "src/lib/Kconfig"
config ENABLE_APIC_EXT_ID
bool
default n
config WARNINGS_ARE_ERRORS
bool
default y

20
src/arch/x86/include/arch/acpi_device.h
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@ -303,6 +303,26 @@ struct acpi_gpio {
.pin_count = 1, \
.pins = { (gpio) } }
/* Level Triggered Active High GPIO interrupt with wake */
#define ACPI_GPIO_IRQ_LEVEL_HIGH_WAKE(gpio) { \
.type = ACPI_GPIO_TYPE_INTERRUPT, \
.pull = ACPI_GPIO_PULL_DEFAULT, \
.irq.mode = ACPI_IRQ_LEVEL_TRIGGERED, \
.irq.polarity = ACPI_IRQ_ACTIVE_HIGH, \
.irq.wake = ACPI_IRQ_WAKE, \
.pin_count = 1, \
.pins = { (gpio) } }
/* Level Triggered Active Low GPIO interrupt with wake */
#define ACPI_GPIO_IRQ_LEVEL_LOW_WAKE(gpio) { \
.type = ACPI_GPIO_TYPE_INTERRUPT, \
.pull = ACPI_GPIO_PULL_DEFAULT, \
.irq.mode = ACPI_IRQ_LEVEL_TRIGGERED, \
.irq.polarity = ACPI_IRQ_ACTIVE_LOW, \
.irq.wake = ACPI_IRQ_WAKE, \
.pin_count = 1, \
.pins = { (gpio) } }
/* Write GpioIo() or GpioInt() descriptor to SSDT AML output */
void acpi_device_write_gpio(const struct acpi_gpio *gpio);

26
src/ec/google/wilco/commands.c
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@ -224,3 +224,29 @@ void die_notify(void)
wilco_ec_mailbox(WILCO_EC_MSG_DEFAULT, KB_ERR_CODE,
&err_code, 1, NULL, 0);
}
/*
* EC CPU ID data struct
* MBOX[2] = 0xFF
* MBOX[3] = CPUID_Low
* MBOX[4] = CPUID_Mid
* MBOX[5] = CPUID_High
* MBOX[6] = CPU_Core
* MBOX[7] = GPU_Core
* MBOX[8] = Reserved
*/
int wilco_ec_set_cpuid(uint32_t cpuid, uint8_t cpu_cores, uint8_t gpu_cores)
{
uint8_t cpu_id[7] = {0}, i;
cpu_id[0] = 0xff;
for (i = 1; i < 4; i++) {
cpu_id[i] = cpuid & 0xff;
cpuid = cpuid >> 8;
}
cpu_id[4] = cpu_cores;
cpu_id[5] = gpu_cores;
return wilco_ec_mailbox(WILCO_EC_MSG_DEFAULT, KB_CPU_ID, cpu_id,
ARRAY_SIZE(cpu_id), NULL, 0);
}

16
src/ec/google/wilco/commands.h
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@ -52,6 +52,8 @@ enum {
KB_BIOS_PROGRESS = 0xc2,
/* Inform the EC that a fatal error occurred */
KB_ERR_CODE = 0x7b,
/* Set CPU ID */
KB_CPU_ID = 0xbf,
};
enum ec_ram_addr {
@ -337,4 +339,18 @@ int wilco_ec_signed_fw(void);
*/
void wilco_ec_save_post_code(uint8_t post_code);
/**
* wilco_ec_set_cpuid
*
* Set CPU ID to EC.
*
* @cpuid: read CPU ID from cpu_eax(1)
* @cpu_cores: cores of CPU
* @gpu_cores: cores of GPU
*
* Returns 0 if EC command was successful
* Returns -1 if EC command failed
*/
int wilco_ec_set_cpuid(uint32_t cpuid, uint8_t cpu_cores, uint8_t gpu_cores);
#endif /* EC_GOOGLE_WILCO_COMMANDS_H */

2
src/lib/Makefile.inc
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@ -338,7 +338,7 @@ LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(
# Include spd ROM data
$(LIB_SPD_BIN): $(LIB_SPD_DEPS)
for f in $(LIB_SPD_DEPS); \
do for c in $$(cat $$f | grep -v ^#); \
do for c in $$(cat $$f | grep --binary-files=text -v ^#); \
do printf $$(printf '\%o' 0x$$c); \
done; \
done > $@

53
src/mainboard/gigabyte/ga-b75m-d3h/acpi/pci.asl Normal file
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@ -0,0 +1,53 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2020 Bill Xie <persmule@hardenedlinux.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
// Intel PCI to PCI bridge 0:1e.0
Device (PCIB)
{
Name (_ADR, 0x001E0000) // _ADR: Address
Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake
Method (_PRT) // _PRT: PCI Interrupt Routing Table
{
If (PICM) {
Return (Package() {
Package() { 0x0001ffff, 0, 0, 0x13 },
Package() { 0x0001ffff, 1, 0, 0x12 },
Package() { 0x0001ffff, 2, 0, 0x10 },
Package() { 0x0001ffff, 3, 0, 0x14 },
#if CONFIG(BOARD_GIGABYTE_GA_B75_D3V)
Package() { 0x0002ffff, 0, 0, 0x12 },
Package() { 0x0002ffff, 1, 0, 0x10 },
Package() { 0x0002ffff, 2, 0, 0x14 },
Package() { 0x0002ffff, 3, 0, 0x13 },
#endif
})
}
Return (Package() {
Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
#if CONFIG(BOARD_GIGABYTE_GA_B75_D3V)
Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKA, 0 },
Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKE, 0 },
Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
#endif
})
}
}

1
src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl
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@ -37,6 +37,7 @@ DefinitionBlock(
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
#include "acpi/pci.asl"
}
}
}

16
src/mainboard/google/dedede/Kconfig
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@ -1,5 +1,10 @@
config BOARD_GOOGLE_BASEBOARD_DEDEDE
def_bool n
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_ESPI
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select MAINBOARD_HAS_CHROMEOS
select SOC_INTEL_JASPERLAKE
if BOARD_GOOGLE_BASEBOARD_DEDEDE
@ -8,6 +13,13 @@ config BASEBOARD_DEDEDE_LAPTOP
def_bool n
select SYSTEM_TYPE_LAPTOP
config CHROMEOS
bool
default y
select EC_GOOGLE_CHROMEEC_SWITCHES
select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
select VBOOT_LID_SWITCH
config DEVICETREE
string
default "variants/baseboard/devicetree.cb"
@ -32,4 +44,8 @@ config UART_FOR_CONSOLE
int
default 2
config VARIANT_DIR
string
default "dedede" if BOARD_GOOGLE_DEDEDE
endif #BOARD_GOOGLE_BASEBOARD_DEDEDE

13
src/mainboard/google/dedede/Makefile.inc
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@ -1,6 +1,19 @@
bootblock-y += bootblock.c
bootblock-$(CONFIG_CHROMEOS) += chromeos.c
verstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-y += mainboard.c
ramstage-y += ec.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
subdirs-y += variants/baseboard
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR))
subdirs-y += variants/$(VARIANT_DIR)
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include

7
src/mainboard/google/dedede/bootblock.c
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@ -6,9 +6,14 @@
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include <baseboard/variants.h>
#include <bootblock_common.h>
void bootblock_mainboard_init(void)
{
/* TODO: Perform mainboard initialization */
const struct pad_config *pads;
size_t num;
pads = variant_early_gpio_table(&num);
gpio_configure_pads(pads, num);
}

39
src/mainboard/google/dedede/chromeos.c Normal file
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@ -0,0 +1,39 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2020 The coreboot project Authors.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <boot/coreboot_tables.h>
#include <gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
void fill_lb_gpios(struct lb_gpios *gpios)
{
struct lb_gpio chromeos_gpios[] = {
{-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
{-1, ACTIVE_HIGH, 0, "power"},
{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
};
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
}
int get_write_protect_state(void)
{
/* No write protect */
return 0;
}
void mainboard_chromeos_acpi_generate(void)
{
const struct cros_gpio *gpios;
size_t num;
gpios = variant_cros_gpios(&num);
chromeos_acpi_gpio_generate(gpios, num);
}

53
src/mainboard/google/dedede/dsdt.asl Normal file
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@ -0,0 +1,53 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2020 The coreboot project Authors.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include <arch/acpi.h>
#include <variant/ec.h>
#include <variant/gpio.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
0x02, /* DSDT revision: ACPI v2.0 and up */
OEM_ID,
ACPI_TABLE_CREATOR,
0x20110725 /* OEM revision */
)
{
/* Some generic macros */
#include <soc/intel/tigerlake/acpi/platform.asl>
/* global NVS and variables */
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
/* CPU */
#include <cpu/intel/common/acpi/cpu.asl>
Scope (\_SB) {
Device (PCI0)
{
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
#include <soc/intel/tigerlake/acpi/southbridge.asl>
}
}
/* Chrome OS specific */
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl>
/* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
/* ACPI code for EC SuperIO functions */
#include <ec/google/chromeec/acpi/superio.asl>
/* ACPI code for EC functions */
#include <ec/google/chromeec/acpi/ec.asl>
}
}

29
src/mainboard/google/dedede/ec.c Normal file
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@ -0,0 +1,29 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2020 The coreboot project Authors.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include <arch/acpi.h>
#include <console/console.h>
#include <ec/ec.h>
#include <ec/google/chromeec/ec.h>
#include <intelblocks/lpc_lib.h>
#include <variant/ec.h>
void mainboard_ec_init(void)
{
static const struct google_chromeec_event_info info = {
.log_events = MAINBOARD_EC_LOG_EVENTS,
.sci_events = MAINBOARD_EC_SCI_EVENTS,
.s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
.s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
.s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
};
printk(BIOS_ERR, "mainboard: EC init\n");
google_chromeec_events_init(&info, acpi_is_wakeup_s3());
}

25
src/mainboard/google/dedede/mainboard.c
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@ -6,16 +6,37 @@
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include <arch/acpi.h>
#include <baseboard/variants.h>
#include <device/device.h>
#include <ec/ec.h>
#include <vendorcode/google/chromeos/chromeos.h>
static void mainboard_init(void *chip_info)
{
/* TODO: Perform mainboard initialization */
const struct pad_config *pads;
size_t num;
pads = variant_gpio_table(&num);
gpio_configure_pads(pads, num);
}
static void mainboard_dev_init(struct device *dev)
{
mainboard_ec_init();
}
static unsigned long mainboard_write_acpi_tables(
struct device *device, unsigned long current, acpi_rsdp_t *rsdp)
{
return current;
}
static void mainboard_enable(struct device *dev)
{
/* TODO: Enable mainboard */
dev->ops->init = mainboard_dev_init;
dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
}
struct chip_operations mainboard_ops = {

37
src/mainboard/google/dedede/smihandler.c Normal file
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@ -0,0 +1,37 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2020 The coreboot project Authors.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include <baseboard/variants.h>
#include <cpu/x86/smm.h>
#include <ec/google/chromeec/smm.h>
#include <intelblocks/smihandler.h>
#include <variant/ec.h>
void mainboard_smi_gpi_handler(const struct gpi_status *sts)
{
/* TODO: Process SMI events from GPI */
}
void mainboard_smi_sleep(u8 slp_typ)
{
const struct pad_config *pads;
size_t num;
pads = variant_sleep_gpio_table(&num);
gpio_configure_pads(pads, num);
chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
MAINBOARD_EC_S5_WAKE_EVENTS);
}
int mainboard_smi_apmc(u8 apmc)
{
chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
MAINBOARD_EC_SMI_EVENTS);
return 0;
}

5
src/mainboard/google/dedede/variants/baseboard/Makefile.inc Normal file
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@ -0,0 +1,5 @@
bootblock-y += gpio.c
ramstage-y += gpio.c
smm-y += gpio.c

53
src/mainboard/google/dedede/variants/baseboard/gpio.c Normal file
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@ -0,0 +1,53 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2020 The coreboot project Authors.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <commonlib/helpers.h>
#include <vendorcode/google/chromeos/chromeos.h>
/* Pad configuration in ramstage*/
static const struct pad_config gpio_table[] = {
/* ToDo: Fill gpio configuration */
};
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
/* ToDo: Fill early gpio configuration */
};
const struct pad_config *__weak variant_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(gpio_table);
return gpio_table;
}
const struct pad_config *__weak variant_early_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(early_gpio_table);
return early_gpio_table;
}
/* GPIO settings before entering sleep. */
static const struct pad_config sleep_gpio_table[] = {
};
const struct pad_config *__weak variant_sleep_gpio_table(size_t *num)
{
*num = ARRAY_SIZE(sleep_gpio_table);
return sleep_gpio_table;
}
static const struct cros_gpio cros_gpios[] = {
};
const struct cros_gpio *__weak variant_cros_gpios(size_t *num)
{
*num = ARRAY_SIZE(cros_gpios);
return cros_gpios;
}

82
src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h Normal file
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@ -0,0 +1,82 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2020 The coreboot project Authors.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef __BASEBOARD_EC_H__
#define __BASEBOARD_EC_H__
#include <ec/ec.h>
#include <ec/google/chromeec/ec_commands.h>
#include <baseboard/gpio.h>
#define MAINBOARD_EC_SCI_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
#define MAINBOARD_EC_SMI_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
/* EC can wake from S5 with lid or power button */
#define MAINBOARD_EC_S5_WAKE_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
/*
* EC can wake from S3/S0ix with:
* 1. Lid open
* 2. Power button
* 3. Key press
* 4. Mode change
*/
#define MAINBOARD_EC_S3_WAKE_EVENTS \
(MAINBOARD_EC_S5_WAKE_EVENTS |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS)
/* Log EC wake events plus EC shutdown events */
#define MAINBOARD_EC_LOG_EVENTS \
(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
/*
* ACPI related definitions for ASL code.
*/
/* Enable EC backed ALS device in ACPI */
#define EC_ENABLE_ALS_DEVICE
/* Enable LID switch and provide wake pin for EC */
#define EC_ENABLE_LID_SWITCH
#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
/* Enable Tablet switch */
#define EC_ENABLE_TBMC_DEVICE
/* Enable EC backed PD MCU device in ACPI */
#define EC_ENABLE_PD_MCU_DEVICE
#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
#endif /* __BASEBOARD_EC_H__ */

6
src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h
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@ -12,4 +12,10 @@
#include <soc/gpe.h>
#include <soc/gpio.h>
/* eSPI virtual wire reporting */
#define EC_SCI_GPI GPE0_ESPI
/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
#define GPE_EC_WAKE GPE0_LAN_WAK
#endif /* __BASEBOARD_GPIO_H__ */

8
src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h
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@ -12,4 +12,12 @@
#include <soc/gpio.h>
#include <stdint.h>
/* The next set of functions return the gpio table and fill in the number of
* entries for each table. */
const struct pad_config *variant_gpio_table(size_t *num);
const struct pad_config *variant_early_gpio_table(size_t *num);
const struct pad_config *variant_sleep_gpio_table(size_t *num);
const struct cros_gpio *variant_cros_gpios(size_t *num);
#endif /*__BASEBOARD_VARIANTS_H__ */

14
src/mainboard/google/dedede/variants/dedede/include/variant/ec.h Normal file
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@ -0,0 +1,14 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2020 The coreboot project Authors.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef MAINBOARD_EC_H
#define MAINBOARD_EC_H
#include <baseboard/ec.h>
#endif

14
src/mainboard/google/dedede/variants/dedede/include/variant/gpio.h Normal file
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@ -0,0 +1,14 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2020 The coreboot project Authors.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef MAINBOARD_GPIO_H
#define MAINBOARD_GPIO_H
#include <baseboard/gpio.h>
#endif /* MAINBOARD_GPIO_H */

12
src/mainboard/google/drallion/variants/drallion/devicetree.cb
View File

@ -65,7 +65,7 @@ chip soc/intel/cannonlake
register "PchHdaIDispCodecDisconnect" = "1"
register "PchHdaAudioLinkHda" = "1"
# VR Settings Configuration for 4 Domains
# VR Settings Configuration for 2/4 Domains
#+----------------+-------+-------+-------+-------+
#| Domain/Setting | SA | IA | GTUS | GTS |
#+----------------+-------+-------+-------+-------+
@ -76,7 +76,7 @@ chip soc/intel/cannonlake
#| Psi4Enable | 1 | 1 | 1 | 1 |
#| ImonSlope | 0 | 0 | 0 | 0 |
#| ImonOffset | 0 | 0 | 0 | 0 |
#| IccMax | 6A | 70A | 31A | 31A |
#| IccMax | 6A | 35/70A| 31A | 31A |
#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
#| AcLoadline | 10.3 | 1.8 | 3.1 | 3.1 |
#| DcLoadline | 10.3 | 1.8 | 3.1 | 3.1 |
@ -90,7 +90,7 @@ chip soc/intel/cannonlake
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(6),
.icc_max = 0,
.voltage_limit = 1520,
.ac_loadline = 1030,
.dc_loadline = 1030,
@ -105,7 +105,7 @@ chip soc/intel/cannonlake
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(70),
.icc_max = 0,
.voltage_limit = 1520,
.ac_loadline = 180,
.dc_loadline = 180,
@ -120,7 +120,7 @@ chip soc/intel/cannonlake
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(31),
.icc_max = 0,
.voltage_limit = 1520,
.ac_loadline = 310,
.dc_loadline = 310,
@ -135,7 +135,7 @@ chip soc/intel/cannonlake
.psi4enable = 1,
.imon_slope = 0x0,
.imon_offset = 0x0,
.icc_max = VR_CFG_AMP(31),
.icc_max = 0,
.voltage_limit = 1520,
.ac_loadline = 310,
.dc_loadline = 310,

35
src/mainboard/google/hatch/variants/dratini/include/variant/acpi/dptf.asl
View File

@ -38,6 +38,11 @@
#define DPTF_TSR1_ACTIVE_AC5 36
#define DPTF_TSR1_ACTIVE_AC6 33
#define DPTF_TSR2_SENSOR_ID 2
#define DPTF_TSR2_SENSOR_NAME "Thermal Sensor - CPU"
#define DPTF_TSR2_PASSIVE 105
#define DPTF_TSR2_CRITICAL 105
#define DPTF_ENABLE_CHARGER
#define DPTF_ENABLE_FAN_CONTROL
@ -57,15 +62,15 @@ Name (DFPS, Package () {
* These are initial reference values.
*/
/* Control, Trip Point, Speed, NoiseLevel, Power */
Package () {90, 0xFFFFFFFF, 6700, 220, 2200},
Package () {80, 0xFFFFFFFF, 5800, 180, 1800},
Package () {70, 0xFFFFFFFF, 5000, 145, 1450},
Package () {60, 0xFFFFFFFF, 4900, 115, 1150},
Package () {50, 0xFFFFFFFF, 3838, 90, 900},
Package () {40, 0xFFFFFFFF, 2904, 55, 550},
Package () {30, 0xFFFFFFFF, 2337, 30, 300},
Package () {20, 0xFFFFFFFF, 1608, 15, 150},
Package () {10, 0xFFFFFFFF, 800, 10, 100},
Package () {100, 0xFFFFFFFF, 6700, 220, 2200},
Package () {90, 0xFFFFFFFF, 5800, 180, 1800},
Package () {80, 0xFFFFFFFF, 5000, 145, 1450},
Package () {70, 0xFFFFFFFF, 4900, 115, 1150},
Package () {63, 0xFFFFFFFF, 3838, 90, 900},
Package () {58, 0xFFFFFFFF, 2904, 55, 550},
Package () {54, 0xFFFFFFFF, 2337, 30, 300},
Package () {50, 0xFFFFFFFF, 1608, 15, 150},
Package () {45, 0xFFFFFFFF, 800, 10, 100},
Package () {0, 0xFFFFFFFF, 0, 0, 50}
})
@ -84,6 +89,11 @@ Name (DART, Package () {
\_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 100, 80, 70, 60, 50, 40, 30,
0, 0, 0
},
Package () {
\_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 100, 80, 70, 60, 50, 40, 30,
0, 0, 0
},
})
Name (DTRT, Package () {
@ -96,6 +106,9 @@ Name (DTRT, Package () {
/* CPU Throttle Effect on CPU (TSR1) */
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 },
/* CPU Throttle Effect on CPU (TSR2) */
Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 60, 0, 0, 0, 0 },
})
Name (MPPC, Package ()
@ -112,8 +125,8 @@ Name (MPPC, Package ()
Package () { /* Power Limit 2 */
1, /* PowerLimitIndex, 1 for Power Limit 2 */
15000, /* PowerLimitMinimum */
25000, /* PowerLimitMaximum */
28000, /* TimeWindowMinimum */
51000, /* PowerLimitMaximum */
51000, /* TimeWindowMinimum */
32000, /* TimeWindowMaximum */
1000 /* StepSize */
}

2
src/mainboard/google/hatch/variants/dratini/overridetree.cb
View File

@ -1,4 +1,6 @@
chip soc/intel/cannonlake
register "tdp_pl1_override" = "15"
register "tdp_pl2_override" = "51"
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,

2
src/mainboard/google/hatch/variants/kohaku/gpio.c
View File

@ -45,6 +45,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, INVERT),
/* C12 : EN_PP3300_TSP_DX */
PAD_CFG_GPO(GPP_C12, 0, DEEP),
/* C13 : EC_PCH_INT_L - needs to wake the system */
PAD_CFG_GPI_IRQ_WAKE(GPP_C13, NONE, PLTRST, LEVEL, INVERT),
/* C15 : EN_PP3300_DIG_DX */
PAD_CFG_GPO(GPP_C15, 0, DEEP),
/* C23 : UART2_CTS# ==> NC */

10
src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h
View File

@ -20,4 +20,12 @@
#define EC_ENABLE_MULTIPLE_DPTF_PROFILES
#endif
#undef MAINBOARD_EC_S3_WAKE_EVENTS
#define MAINBOARD_EC_S3_WAKE_EVENTS \
(MAINBOARD_EC_S5_WAKE_EVENTS |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
#endif /* VARIANT_EC_H */

1
src/mainboard/google/hatch/variants/puff/overridetree.cb
View File

@ -270,6 +270,7 @@ chip soc/intel/cannonlake
device pci 1c.0 on
chip drivers/net
register "customized_leds" = "0x05af"
register "wake" = "GPE0_DW1_07" # GPP_C7
device pci 00.0 on end
end
end # FSP requires func0 be enabled.

1
src/mainboard/google/octopus/Kconfig
View File

@ -22,6 +22,7 @@ config BOARD_GOOGLE_BASEBOARD_OCTOPUS
select MAINBOARD_HAS_SPI_TPM_CR50
select MAINBOARD_HAS_TPM2
select GOOGLE_SMBIOS_MAINBOARD_VERSION
select NO_BOOTBLOCK_CONSOLE
select NO_FMAP_CACHE
if BOARD_GOOGLE_BASEBOARD_OCTOPUS

2
src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c
View File

@ -40,7 +40,7 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
}
static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM0_NAME),
};
const struct cros_gpio *variant_cros_gpios(size_t *num)

523
src/mainboard/intel/tglrvp/acpi/mipi_camera.asl Normal file
View File

@ -0,0 +1,523 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2020 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
Scope (\_SB.PCI0.IPU0)
{
Name (_DSD, Package (0x02)
{
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
Package (0x02)
{
Package (0x02)
{
"port0",
"PRT0"
},
Package (0x02)
{
"port1",
"PRT1"
}
}
})
Name (PRT0, Package (0x04)
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package (0x01)
{
Package (0x02)
{
"port",
One
}
},
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
Package (0x01)
{
Package (0x02)
{
"endpoint0",
"EP00"
}
}
})
Name (PRT1, Package (0x04)
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package (0x01)
{
Package (0x02)
{
"port",
2
}
},
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
Package (0x01)
{
Package (0x02)
{
"endpoint0",
"EP10"
}
}
})
}
Scope (_SB.PCI0.IPU0)
{
Name (EP00, Package (0x02)
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package (0x04)
{
Package (0x02)
{
"endpoint",
Zero
},
Package (0x02)
{
"clock-lanes",
Zero
},
Package (0x02)
{
"data-lanes",
Package (0x04)
{
One,
0x02,
0x03,
0x04
}
},
Package (0x02)
{
"remote-endpoint",
Package (0x03)
{
^I2C3.CAM0,
Zero,
Zero
}
}
}
})
Name (EP10, Package (0x02)
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package (0x04)
{
Package (0x02)
{
"endpoint",
Zero
},
Package (0x02)
{
"clock-lanes",
Zero
},
Package (0x02)
{
"data-lanes",
Package (0x04)
{
One,
0x02,
0x03,
0x04
}
},
Package (0x02)
{
"remote-endpoint",
Package (0x03)
{
^I2C5.CAM1,
Zero,
Zero
}
}
}
})
}
Scope (\_SB.PCI0.I2C3)
{
PowerResource (RCPR, 0x00, 0x0000)
{
Name (STA, Zero)
Method (_ON, 0, Serialized)
{
If ((STA == Zero))
{
/* Enable CLK0 with 19.2MHz */
MCCT(0,1,1)
/* Pull PWREN(GPIO B23) high */
STXS(GPP_B23)
Sleep(5)
/* Pull RST(GPIO C15) low */
CTXS(GPP_C15)
Sleep(5)
/* Pull RST high */
STXS(GPP_C15)
Sleep(5)
Store(1,STA)
}
}
Method (_OFF, 0, Serialized)
{
If ((STA == One))
{
/* Pull RST low */
CTXS(GPP_C15)
/* Pull PWREN low */
CTXS(GPP_B23)
/* Disable CLK0 */
MCCT(0,0,1)
Store(0,STA)
}
}
Method (_STA, 0, NotSerialized)
{
Return (STA)
}
}
Device (CAM0)
{
Name (_HID, "OVTI8856")
Name (_UID, Zero)
Name (_DDN, "Ov 8856 Camera")
Method (_STA, 0, NotSerialized)
{
Return (0x0F)
}
Name (_CRS, ResourceTemplate ()
{
I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80,
AddressingMode7Bit, "\\_SB.PCI0.I2C3",
0x00, ResourceConsumer, ,
)
})
Name (_PR0, Package (0x01)
{
RCPR
})
Name (_PR3, Package (0x01)
{
RCPR
})
Name (_DSD, Package (0x04)
{
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
Package (0x01)
{
Package (0x02)
{
"port0",
"PRT0"
}
},
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package (0x02)
{
Package (0x02)
{
"clock-frequency",
0x0124F800
},
Package (0x02)
{
"lens-focus",
Package (0x01)
{
VCM0
}
}
}
})
Name (PRT0, Package (0x04)
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package (0x01)
{
Package (0x02)
{
"port",
Zero
}
},
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
Package (0x01)
{
Package (0x02)
{
"endpoint0",
"EP00"
}
}
})
Name (EP00, Package (0x02)
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package (0x03)
{
Package (0x02)
{
"endpoint",
Zero
},
Package (0x02)
{
"link-frequencies",
Package (0x01)
{
0x325AA000
}
},
Package (0x02)
{
"remote-endpoint",
Package (0x03)
{
IPU0,
Zero,
Zero
}
}
}
})
}
Device (VCM0)
{
Name (_HID, "PRP0001")
Name (_UID, 0x03)
Name (_DDN, "DW9714 VCM")
Method (_STA, 0, NotSerialized)
{
Return (0x0F)
}
Name (_CRS, ResourceTemplate ()
{
I2cSerialBus (0x000C, ControllerInitiated, 0x00061A80,
AddressingMode7Bit, "\\_SB.PCI0.I2C3",
0x00, ResourceConsumer, ,
)
})
Name (_DEP, Package (0x01)
{
CAM0
})
Name (_PR0, Package (0x01)
{
RCPR
})
Name (_PR3, Package (0x01)
{
RCPR
})
Name (_DSD, Package (0x02)
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package (0x01)
{
Package (0x02)
{
"compatible",
"dongwoon,dw9714"
}
}
})
}
}
Scope (\_SB.PCI0.I2C5)
{
PowerResource (FCPR, 0x00, 0x0000)
{
Name (STA, Zero)
Method (_ON, 0, Serialized)
{
If ((STA == Zero))
{
/* Enable CLK1 with 19.2MHz */
MCCT(1,1,1)
/* Pull PWREN(GPIO R6) high */
STXS(GPP_R6)
Sleep(5)
/* Pull RST(GPIO H12) low */
CTXS(GPP_H12)
Sleep(5)
/* Pull RST high */
STXS(GPP_H12)
Sleep(5)
Store(1,STA)
}
}
Method (_OFF, 0, Serialized)
{
If ((STA == One))
{
/* Pull RST low */
CTXS(GPP_H12)
/* Pull PWREN low */
CTXS(GPP_R6)
/* Disable CLK1 */
MCCT(1,0,1)
Store(0,STA)
}
}
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (STA)
}
}
Device (CAM1)
{
Name (_HID, "OVTI8856")
Name (_UID, Zero)
Name (_DDN, "Ov 8856 Camera")
Method (_STA, 0, NotSerialized)
{
Return (0x0F)
}
Name (_CRS, ResourceTemplate ()
{
I2cSerialBus (0x0010, ControllerInitiated, 0x00061A80,
AddressingMode7Bit, "\\_SB.PCI0.I2C5",
0x00, ResourceConsumer, ,
)
})
Name (_PR0, Package (0x01)
{
FCPR
})
Name (_PR3, Package (0x01)
{
FCPR
})
Name (_DSD, Package (0x04)
{
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
Package (0x01)
{
Package (0x02)
{
"port0",
"PRT0"
}
},
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package (0x01)
{
Package (0x02)
{
"clock-frequency",
0x0124F800
}
}
})
Name (PRT0, Package (0x04)
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package (0x01)
{
Package (0x02)
{
"port",
Zero
}
},
ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
Package (0x01)
{
Package (0x02)
{
"endpoint0",
"EP00"
}
}
})
Name (EP00, Package (0x02)
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
Package (0x03)
{
Package (0x02)
{
"endpoint",
Zero
},
Package (0x02)
{
"link-frequencies",
Package (0x01)
{
0x325AA000
}
},
Package (0x02)
{
"remote-endpoint",
Package (0x03)
{
IPU0,
One,
Zero
}
}
}
})
}
}

3
src/mainboard/intel/tglrvp/dsdt.asl
View File

@ -65,4 +65,7 @@ DefinitionBlock(
/* Mainboard specific */
#include "acpi/mainboard.asl"
/* Camera */
#include <soc/intel/tigerlake/acpi/ipu.asl>
#include "acpi/mipi_camera.asl"
}

12
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
View File

@ -35,7 +35,7 @@ chip soc/intel/tigerlake
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[3]" = "1"
register "PcieRpEnable[8]" = "1"
register "PcieRpEnable[9]" = "1"
register "PcieRpEnable[10]" = "1"
register "PcieClkSrcClkReq[1]" = "1"
register "PcieClkSrcClkReq[2]" = "2"
@ -45,6 +45,10 @@ chip soc/intel/tigerlake
register "PcieClkSrcUsage[2]" = "0x3"
register "PcieClkSrcUsage[3]" = "0x8"
register "SataSalpSupport" = "1"
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"
register "SerialIoI2cMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
@ -122,7 +126,7 @@ chip soc/intel/tigerlake
device pci 16.3 off end # CSME 0xA0E3
device pci 16.4 off end # HECI3 0xA0E4
device pci 16.5 off end # HECI4 0xA0E5
device pci 17.0 off end # SATA 0xA0D3
device pci 17.0 on end # SATA 0xA0D3
device pci 19.0 off end # I2C4 0xA0C5
device pci 19.1 on end # I2C5 0xA0C6
device pci 19.2 on end # UART2 0xA0C7
@ -135,8 +139,8 @@ chip soc/intel/tigerlake
device pci 1c.6 off end # RP7 0xA0BE
device pci 1c.7 off end # RP8 0xA0BF
device pci 1d.0 on end # RP9 0xA0B0
device pci 1d.1 on end # RP10 0xA0B1
device pci 1d.2 off end # RP11 0xA0B2
device pci 1d.1 off end # RP10 0xA0B1
device pci 1d.2 on end # RP11 0xA0B2
device pci 1d.3 off end # RP12 0xA0B3
device pci 1e.0 off end # UART0 0xA0A8
device pci 1e.1 off end # UART1 0xA0A9

10
src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
View File

@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2019 Intel Corporation.
* Copyright (C) 2020 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -22,6 +22,12 @@ static const struct pad_config gpio_table[] = {
/* PCH M.2 SSD */
PAD_CFG_GPO(GPP_B16, 1, PLTRST),
PAD_CFG_GPO(GPP_H0, 1, PLTRST),
/* Camera */
PAD_CFG_GPO(GPP_B23, 0, PLTRST),
PAD_CFG_GPO(GPP_C15, 0, PLTRST),
PAD_CFG_GPO(GPP_R6, 0, PLTRST),
PAD_CFG_GPO(GPP_H12, 0, PLTRST),
};
/* Early pad configuration in bootblock */
@ -42,7 +48,7 @@ const struct pad_config *variant_early_gpio_table(size_t *num)
}
static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM0_NAME),
};
const struct cros_gpio *variant_cros_gpios(size_t *num)

3
src/mainboard/lenovo/x201/romstage.c
View File

@ -54,9 +54,6 @@ static void set_fsb_frequency(void)
void mainboard_pre_raminit(void)
{
outb(0x50, 0x15ec);
outb(inb(0x15ee) & 0x70, 0x15ee);
set_fsb_frequency();
}

3
src/mainboard/portwell/m107/dsdt.asl
View File

@ -43,6 +43,5 @@ DefinitionBlock(
}
}
/* Mainboard specific sleep states */
#include "acpi/sleepstates.asl"
#include <southbridge/intel/common/acpi/sleepstates.asl>
}

2
src/mainboard/system76/lemp9/acpi/mainboard.asl
View File

@ -13,8 +13,6 @@
* GNU General Public License for more details.
*/
#define COLOR_KEYBOARD 0
Scope (\_SB) {
#include "ac.asl"
#include "battery.asl"

30
src/mainboard/system76/lemp9/acpi/s76.asl
View File

@ -27,9 +27,6 @@ Device (S76D) {
Debug = "S76D: RSET"
SAPL(0)
SKBL(0)
#if COLOR_KEYBOARD
SKBC(0xFFFFFF)
#endif
}
Method (INIT, 0, Serialized) {
@ -77,32 +74,6 @@ Device (S76D) {
}
}
#if COLOR_KEYBOARD
// Set KB LED Brightness
Method (SKBL, 1, Serialized) {
If (^^PCI0.LPCB.EC0.ECOK) {
^^PCI0.LPCB.EC0.FDAT = 6
^^PCI0.LPCB.EC0.FBUF = Arg0
^^PCI0.LPCB.EC0.FBF1 = 0
^^PCI0.LPCB.EC0.FBF2 = Arg0
^^PCI0.LPCB.EC0.FCMD = 0xCA
}
}
// Set Keyboard Color
Method (SKBC, 1, Serialized) {
If (^^PCI0.LPCB.EC0.ECOK) {
^^PCI0.LPCB.EC0.FDAT = 0x3
^^PCI0.LPCB.EC0.FBUF = (Arg0 & 0xFF)
^^PCI0.LPCB.EC0.FBF1 = ((Arg0 >> 16) & 0xFF)
^^PCI0.LPCB.EC0.FBF2 = ((Arg0 >> 8) & 0xFF)
^^PCI0.LPCB.EC0.FCMD = 0xCA
Return (Arg0)
} Else {
Return (0)
}
}
#else
// Get KB LED
Method (GKBL, 0, Serialized) {
Local0 = 0
@ -123,5 +94,4 @@ Device (S76D) {
^^PCI0.LPCB.EC0.FCMD = 0xCA
}
}
#endif
}

3
src/northbridge/intel/i440bx/debug.c
View File

@ -14,6 +14,7 @@
#include <console/console.h>
#include <device/pci_ops.h>
#include <spd.h>
#include <southbridge/intel/i82371eb/i82371eb.h>
#include "raminit.h"
void dump_spd_registers(void)
@ -32,7 +33,7 @@ void dump_spd_registers(void)
if ((j & 0xf) == 0) {
printk(BIOS_DEBUG, "\n%02x: ", j);
}
status = spd_read_byte(device, j);
status = smbus_read_byte(device, j);
if (status < 0) {
printk(BIOS_DEBUG, "bad device\n");
break;

17
src/northbridge/intel/i440bx/raminit.c
View File

@ -22,6 +22,7 @@
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <console/console.h>
#include <timestamp.h>
#include "i440bx.h"
#include "raminit.h"
@ -356,10 +357,7 @@ static const u8 register_values[] = {
* 1 = Enable
* 0 = Disable
*/
/* Enable normal refresh and the gated clock. */
// TODO: Only do this later?
// PMCR, 0x00, 0x14,
PMCR, 0x00, 0x00,
/* PMCR will be set later. */
/* Enable SCRR.SRRAEN and let BX choose the SRR. */
SCRR + 1, 0x00, 0x10,
@ -984,13 +982,6 @@ static void sdram_set_spd_registers(void)
/* Setup DRAM buffer strength. */
set_dram_buffer_strength();
/* TODO: Set PMCR? */
// pci_write_config8(NB, PMCR, 0x14);
pci_write_config8(NB, PMCR, 0x10);
/* TODO: This is for EDO memory only. */
pci_write_config8(NB, DRAMT, 0x03);
}
static void sdram_enable(void)
@ -1029,7 +1020,7 @@ static void sdram_enable(void)
/* 6. Finally enable refresh. */
PRINT_DEBUG("RAM Enable 6: Enable refresh\n");
// pci_write_config8(NB, PMCR, 0x10);
pci_write_config8(NB, PMCR, 0x10);
spd_enable_refresh();
udelay(1);
@ -1043,6 +1034,7 @@ void __weak disable_spd(void) { }
void sdram_initialize(void)
{
timestamp_add_now(TS_BEFORE_INITRAM);
enable_spd();
dump_spd_registers();
@ -1051,4 +1043,5 @@ void sdram_initialize(void)
sdram_enable();
disable_spd();
timestamp_add_now(TS_AFTER_INITRAM);
}

3
src/northbridge/intel/sandybridge/raminit_common.c
View File

@ -497,7 +497,6 @@ void dram_zones(ramctr_timing *ctrl, int training)
}
}
#define HOST_BRIDGE PCI_DEV(0, 0, 0)
#define DEFAULT_TCK TCK_800MHZ
unsigned int get_mem_min_tck(void)
@ -595,7 +594,7 @@ void dram_memorymap(ramctr_timing *ctrl, int me_uma_size)
mmiosize = get_mmio_size();
ggc = pci_read_config16(NORTHBRIDGE, GGC);
ggc = pci_read_config16(HOST_BRIDGE, GGC);
if (!(ggc & 2)) {
gfxstolen = ((ggc >> 3) & 0x1f) * 32;
gttsize = ((ggc >> 8) & 0x3);

7
src/northbridge/intel/sandybridge/raminit_common.h
View File

@ -18,6 +18,8 @@
#ifndef RAMINIT_COMMON_H
#define RAMINIT_COMMON_H
#include <stdint.h>
#define BASEFREQ 133
#define tDLLK 512
@ -136,8 +138,9 @@ typedef struct ramctr_timing_st {
dimm_info info;
} ramctr_timing;
#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
#define NORTHBRIDGE PCI_DEV(0, 0x0, 0)
#define HOST_BRIDGE PCI_DEV(0, 0, 0)
#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
#define FOR_ALL_LANES for (lane = 0; lane < NUM_LANES; lane++)
#define FOR_ALL_CHANNELS for (channel = 0; channel < NUM_CHANNELS; channel++)
#define FOR_ALL_POPULATED_RANKS for (slotrank = 0; slotrank < NUM_SLOTRANKS; slotrank++) if (ctrl->rankmap[channel] & (1 << slotrank))

2
src/security/vboot/Kconfig
View File

@ -28,7 +28,7 @@ config VBOOT
default n
select VBOOT_LIB
select VBOOT_MOCK_SECDATA if !TPM1 && !TPM2
depends on !MISSING_BOARD_RESET
depends on 0 = 0 # Must have a 'depends on' or board overrides will break it.
help
Enabling VBOOT will use vboot to verify the components of the firmware
(stages, payload, etc).

4
src/soc/intel/common/block/include/intelblocks/systemagent.h
View File

@ -43,13 +43,13 @@ void bootblock_systemagent_early_init(void);
* Fixed MMIO range
* INDEX = Either PCI configuration space registers or MMIO offsets
* mapped from REG.
* BASE = 32 bit Address.
* BASE = 64 bit Address.
* SIZE = base length
* DESCRIPTION = Name of the register/offset.
*/
struct sa_mmio_descriptor {
unsigned int index;
uintptr_t base;
uint64_t base;
size_t size;
const char *description;
};

15
src/soc/intel/common/block/systemagent/systemagent_early.c
View File

@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Intel Corporation.
* Copyright (C) 2017-2020 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -71,7 +71,7 @@ void sa_set_pci_bar(const struct sa_mmio_descriptor *fixed_set_resources,
int i;
for (i = 0; i < count; i++) {
uintptr_t base;
uint64_t base;
unsigned int index;
index = fixed_set_resources[i].index;
@ -83,8 +83,9 @@ void sa_set_pci_bar(const struct sa_mmio_descriptor *fixed_set_resources,
return;
base = fixed_set_resources[i].base;
pci_write_config32(SA_DEV_ROOT, index, base | 1);
if (base >> 32)
pci_write_config32(SA_DEV_ROOT, index + 4, base >> 32);
pci_write_config32(SA_DEV_ROOT, index, (base & 0xffffffff) | 1);
}
}
@ -99,12 +100,14 @@ void sa_set_mch_bar(const struct sa_mmio_descriptor *fixed_set_resources,
int i;
for (i = 0; i < count; i++) {
uintptr_t base;
uint64_t base;
unsigned int index;
base = fixed_set_resources[i].base;
index = fixed_set_resources[i].index;
write32((void *)(MCH_BASE_ADDRESS + index), base | 1);
if (base >> 32)
write32((void *)(MCH_BASE_ADDRESS + index + 4), base >> 32);
write32((void *)(MCH_BASE_ADDRESS + index), (base & 0xffffffff) | 1);
}
}

3
src/soc/intel/skylake/acpi/pch.asl
View File

@ -23,6 +23,9 @@
#include <soc/gpe.h>
#include <soc/pcr_ids.h>
/* PCI IRQ assignment */
#include "pci_irqs.asl"
/* GPIO Controller */
#include "gpio.asl"

30
src/soc/intel/skylake/acpi/systemagent.asl
View File

@ -17,8 +17,10 @@
#include <soc/iomap.h>
Name (_HID, EISAID ("PNP0A08")) /* PCIe */
Name (_CID, EISAID ("PNP0A03")) /* PCI */
Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
Name (_SEG, Zero) // _SEG: PCI Segment
Name (_UID, Zero) // _UID: Unique ID
Device (MCHC)
{
@ -30,26 +32,27 @@ Device (MCHC)
Offset(0x40), /* EPBAR (0:0:0:40) */
EPEN, 1, /* Enable */
, 11,
EPBR, 20, /* EPBAR [31:12] */
EPBR, 27, /* EPBAR [38:12] */
Offset(0x48), /* MCHBAR (0:0:0:48) */
MHEN, 1, /* Enable */
, 14,
MHBR, 17, /* MCHBAR [31:15] */
MHBR, 24, /* MCHBAR [38:15] */
Offset(0x60), /* PCIEXBAR (0:0:0:60) */
PXEN, 1, /* Enable */
PXSZ, 2, /* PCI Express Size */
, 23,
PXBR, 6, /* PCI Express BAR [31:26] */
PXBR, 13, /* PCI Express BAR [38:26] */
Offset(0x68), /* DMIBAR (0:0:0:68) */
DIEN, 1, /* Enable */
, 11,
DIBR, 20, /* DMIBAR [31:12] */
DIBR, 27, /* DMIBAR [38:12] */
Offset (0x70), /* ME Base Address */
MEBA, 64,
Offset (0xa0),
TOM, 64, /* Top of Used Memory */
TUUD, 64, /* Top of Upper Used Memory */
@ -182,11 +185,13 @@ Method (_CRS, 0, Serialized)
0x00000000, PCH_PRESERVED_BASE_ADDRESS, 0xfe7fffff,
0x00000000, PCH_PRESERVED_BASE_SIZE)
#if !CONFIG(TPM_CR50)
/* TPM Area (0xfed40000-0xfed44fff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
0x00005000)
#endif
})
/* Find PCI resource area in MCRS */
@ -292,19 +297,9 @@ Device (PDRC)
*/
Memory32Fixed (ReadWrite, 0, 0, PCIX)
/* MISC ICH TTT base address reserved for the
* TxT module use.
*/
Memory32Fixed (ReadWrite, 0xFED20000, 0x20000)
/* VTD engine memory range. */
Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE)
/* MISC ICH. Check if the hard code meets the
* real configuration.
*/
Memory32Fixed (ReadWrite, 0xFED45000, 0x4B000, TPMM)
/* FLASH range */
Memory32Fixed (ReadOnly, 0, CONFIG_ROM_SIZE, FIOH)
@ -336,6 +331,3 @@ Device (PDRC)
Return (BUF0)
}
}
/* PCI IRQ assignment */
#include "pci_irqs.asl"

1
src/soc/intel/tigerlake/Kconfig
View File

@ -56,6 +56,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
select SOC_INTEL_COMMON_BLOCK_CPU
select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
select SOC_INTEL_COMMON_BLOCK_HDA
select SOC_INTEL_COMMON_BLOCK_SA

206
src/soc/intel/tigerlake/acpi/gpio.asl
View File

@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2019 Intel Corp.
* Copyright (C) 2020 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -16,60 +16,97 @@
#include <soc/irq.h>
#include <soc/pcr_ids.h>
Device (GPIO)
Device (GCM0)
{
Name (_HID, "INT3455")
Name (_HID, "INT34C5")
Name (_UID, 0)
Name (_DDN, "GPIO Controller")
Name (_DDN, "GPIO Controller Community 0")
Name (RBUF, ResourceTemplate()
{
Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM0)
Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
{ GPIO_IRQ14 }
})
Method (_CRS, 0, NotSerialized)
{
Name (RBUF, ResourceTemplate()
{
Memory32Fixed (ReadWrite, 0, 0, COM0)
Memory32Fixed (ReadWrite, 0, 0, COM1)
Memory32Fixed (ReadWrite, 0, 0, COM2)
Memory32Fixed (ReadWrite, 0, 0, COM4)
Memory32Fixed (ReadWrite, 0, 0, COM5)
Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
{ GPIO_IRQ14 }
})
/* GPIO Community 0 */
CreateDWordField (RBUF, COM0._BAS, BAS0)
CreateDWordField (RBUF, COM0._LEN, LEN0)
Store (PCRB (PID_GPIOCOM0), BAS0)
Store (GPIO_BASE_SIZE, LEN0)
/* GPIO Community 1 */
CreateDWordField (RBUF, COM1._BAS, BAS1)
CreateDWordField ( RBUF, COM1._LEN, LEN1)
Store (PCRB (PID_GPIOCOM1), BAS1)
Store (GPIO_BASE_SIZE, LEN1)
/* GPIO Community 2 */
CreateDWordField (RBUF, COM2._BAS, BAS2)
CreateDWordField (RBUF, COM2._LEN, LEN2)
Store (PCRB (PID_GPIOCOM2), BAS2)
Store (GPIO_BASE_SIZE, LEN2)
/* GPIO Community 4 */
CreateDWordField (RBUF, COM4._BAS, BAS4)
CreateDWordField (RBUF, COM4._LEN, LEN4)
Store (PCRB (PID_GPIOCOM4), BAS4)
Store (GPIO_BASE_SIZE, LEN4)
/* GPIO Community 5 */
CreateDWordField (RBUF, COM5._BAS, BAS5)
CreateDWordField (RBUF, COM5._LEN, LEN5)
Store (PCRB (PID_GPIOCOM5), BAS5)
Store (GPIO_BASE_SIZE, LEN5)
Return (RBUF)
CreateDWordField (^RBUF, ^COM0._BAS, BAS0)
BAS0 = ^^PCRB (PID_GPIOCOM0)
Return (^RBUF)
}
Method (_STA)
{
Return (0xF)
}
}
Method (_STA, 0, NotSerialized)
Device (GCM1)
{
Name (_HID, "INT34C5")
Name (_UID, 1)
Name (_DDN, "GPIO Controller Community 1")
Name (RBUF, ResourceTemplate()
{
Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM1)
Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
{ GPIO_IRQ14 }
})
Method (_CRS, 0, NotSerialized)
{
CreateDWordField (^RBUF, ^COM1._BAS, BAS1)
BAS1 = ^^PCRB (PID_GPIOCOM1)
Return (^RBUF)
}
Method (_STA)
{
Return (0xF)
}
}
Device (GCM4)
{
Name (_HID, "INT34C5")
Name (_UID, 4)
Name (_DDN, "GPIO Controller Community 4")
Name (RBUF, ResourceTemplate()
{
Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM4)
Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
{ GPIO_IRQ14 }
})
Method (_CRS, 0, NotSerialized)
{
CreateDWordField (^RBUF, ^COM4._BAS, BAS4)
BAS4 = ^^PCRB (PID_GPIOCOM4)
Return (^RBUF)
}
Method (_STA)
{
Return (0xF)
}
}
Device (GCM5)
{
Name (_HID, "INT34C5")
Name (_UID, 5)
Name (_DDN, "GPIO Controller Community 5")
Name (RBUF, ResourceTemplate()
{
Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, COM5)
Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
{ GPIO_IRQ14 }
})
Method (_CRS, 0, NotSerialized)
{
CreateDWordField (^RBUF, ^COM5._BAS, BAS5)
BAS5 = ^^PCRB (PID_GPIOCOM5)
Return (^RBUF)
}
Method (_STA)
{
Return (0xF)
}
@ -82,38 +119,37 @@ Device (GPIO)
Method (GADD, 1, NotSerialized)
{
/* GPIO Community 0 */
If (Arg0 >= GPP_G0 && Arg0 <= GPP_A23)
If (Arg0 >= GPP_B0 && Arg0 <= GPP_A24)
{
Local0 = PID_GPIOCOM0
Subtract (Arg0, GPP_A0, Local1)
Local1 = Arg0 - GPP_B0
}
/* GPIO Community 1 */
If (Arg0 >= GPP_H0 && Arg0 <= GPP_F19)
If (Arg0 >= GPP_S0 && Arg0 <= vI2S2_RXD)
{
Local0 = PID_GPIOCOM1
Subtract (Arg0, GPP_D0, Local1)
Local1 = Arg0 - GPP_S0
}
/* GPIO Community 2 */
If (Arg0 >= GPD0 && Arg0 <= GPD11)
If (Arg0 >= GPD0 && Arg0 <= GPD_DRAM_RESETB)
{
Local0 = PID_GPIOCOM2
Subtract (Arg0, GPD0, Local1)
Local1 = Arg0 - GPD0
}
/* GPIO Community 4 */
If (Arg0 >= GPP_C0 && Arg0 <= GPP_E23)
If (Arg0 >= GPP_C0 && Arg0 <= GPP_DBG_PMODE)
{
Local0 = PID_GPIOCOM4
Subtract (Arg0, GPP_C0, Local1)
Local1 = Arg0 - GPP_C0
}
/* GPIO Community 05*/
If (Arg0 >= GPP_R0 && Arg0 <= GPP_S7)
/* GPIO Community 5 */
If (Arg0 >= GPP_R0 && Arg0 <= GPP_CLK_LOOPBK)
{
Local0 = PID_GPIOCOM5
Subtract (Arg0, GPP_R0, Local1)
Local1 = Arg0 - GPP_R0
}
Store (PCRB (Local0), Local2)
Add (Local2, PAD_CFG_BASE, Local2)
Return (Add (Local2, Multiply (Local1, 16)))
Local2 = PCRB(Local0) + PAD_CFG_BASE + (Local1 * 16)
Return (Local2)
}
/*
@ -127,7 +163,51 @@ Method (GRXS, 1, Serialized)
{
VAL0, 32
}
And (GPIORXSTATE_MASK, ShiftRight (VAL0, GPIORXSTATE_SHIFT), Local0)
Local0 = GPIORXSTATE_MASK & (VAL0 >> GPIORXSTATE_SHIFT)
Return (Local0)
}
/*
* Get GPIO Tx Value
* Arg0 - GPIO Number
*/
Method (GTXS, 1, Serialized)
{
OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
Field (PREG, AnyAcc, NoLock, Preserve)
{
VAL0, 32
}
Local0 = GPIOTXSTATE_MASK & VAL0
Return (Local0)
}
/*
* Set GPIO Tx Value
* Arg0 - GPIO Number
*/
Method (STXS, 1, Serialized)
{
OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
Field (PREG, AnyAcc, NoLock, Preserve)
{
VAL0, 32
}
VAL0 |= GPIOTXSTATE_MASK
}
/*
* Clear GPIO Tx Value
* Arg0 - GPIO Number
*/
Method (CTXS, 1, Serialized)
{
OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
Field (PREG, AnyAcc, NoLock, Preserve)
{
VAL0, 32
}
VAL0 &= ~GPIOTXSTATE_MASK
}

21
src/mainboard/portwell/m107/acpi/sleepstates.asl → src/soc/intel/tigerlake/acpi/ipu.asl
View File

@ -1,13 +1,11 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
* Copyright (C) 2018 Eltan B.V.
* Copyright (C) 2020 Intel Corporation.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
@ -15,6 +13,11 @@
* GNU General Public License for more details.
*/
Name(\_S0, Package(){0x0,0x0,0x0,0x0})
Name(\_S4, Package(){0x6,0x6,0x0,0x0})
Name(\_S5, Package(){0x7,0x7,0x0,0x0})
Scope (\_SB.PCI0)
{
Device (IPU0)
{
Name (_ADR, 0x00050000)
Name (_DDN, "Camera and Imaging Subsystem")
}
}

14
src/soc/intel/tigerlake/fsp_params_tgl.c
View File

@ -121,6 +121,20 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* PCH UART selection for FSP Debug */
params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
/* SATA */
dev = pcidev_on_root(PCH_DEV_SLOT_SATA, 0);
if (!dev)
params->SataEnable = 0;
else {
params->SataEnable = dev->enabled;
params->SataMode = config->SataMode;
params->SataSalpSupport = config->SataSalpSupport;
memcpy(params->SataPortsEnable, config->SataPortsEnable,
sizeof(params->SataPortsEnable));
memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
sizeof(params->SataPortsDevSlp));
}
mainboard_silicon_init_params(params);
}

102
src/soc/intel/tigerlake/gpio.c
View File

@ -14,24 +14,23 @@
* GNU General Public License for more details.
*/
#include <intelblocks/gpio.h>
#include <intelblocks/pcr.h>
#include <soc/pcr_ids.h>
#include <soc/pmc.h>
/*
* This file is created based on Intel Tiger Lake Processor PCH Datasheet
* Document number: 575857
* Chapter number: 27
*/
#include <intelblocks/gpio.h>
#include <intelblocks/pcr.h>
#include <soc/pcr_ids.h>
#include <soc/pmc.h>
static const struct reset_mapping rst_map[] = {
{ .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 },
{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
{ .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
};
static const struct reset_mapping rst_map_com0[] = {
static const struct reset_mapping rst_map_com2[] = {
{ .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
{ .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
@ -39,55 +38,46 @@ static const struct reset_mapping rst_map_com0[] = {
};
/*
* The GPIO driver for Tigerlake on Windows/Linux expects 32 GPIOs per pad
* group, regardless of whether or not there is a physical pad for each
* exposed GPIO number.
*
* This results in the OS having a sparse GPIO map, and devices that need
* to export an ACPI GPIO must use the OS expected number.
*
* Not all pins are usable as GPIO and those groups do not have a pad base.
*
* This layout matches the Linux kernel pinctrl map for CNL-LP at:
* This layout matches the Linux kernel pinctrl map for TGL-LP at:
* linux/drivers/pinctrl/intel/pinctrl-tigerlake.c
*/
static const struct pad_group tgl_community0_groups[] = {
INTEL_GPP_BASE(GPP_G0, GPP_G0, GPP_G7, 0), /* GPP_G */
INTEL_GPP_BASE(GPP_G0, GPP_B0, GPP_B23, 32), /* GPP_B */
INTEL_GPP(GPP_G0, GPIO_RSVD_0, GPIO_RSVD_1),
INTEL_GPP_BASE(GPP_G0, GPP_A0, GPP_A23, 64), /* GPP_A */
INTEL_GPP(GPP_B0, GPP_B0, GPP_B25), /* GPP_B */
INTEL_GPP(GPP_B0, GPP_T0, GPP_T15), /* GPP_T */
INTEL_GPP(GPP_B0, GPP_A0, GPP_A24), /* GPP_A */
};
static const struct pad_group tgl_community1_groups[] = {
INTEL_GPP_BASE(GPP_H0, GPP_H0, GPP_H23, 96), /* GPP_H */
INTEL_GPP_BASE(GPP_H0, GPP_D0, GPIO_RSVD_2, 128), /* GPP_D */
INTEL_GPP_BASE(GPP_H0, GPP_F0, GPP_F19, 160), /* GPP_F */
INTEL_GPP(GPP_S0, GPP_S0, GPP_S7), /* GPP_S */
INTEL_GPP(GPP_S0, GPP_H0, GPP_H23), /* GPP_H */
INTEL_GPP(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK), /* GPP_D */
INTEL_GPP(GPP_S0, GPP_U0, GPP_GSPI6_CLK_LOOPBK), /* GPP_U */
INTEL_GPP(GPP_S0, CNV_BTEN, vI2S2_RXD), /* GPP_VGPIO */
};
/* This community is not visible to the OS */
static const struct pad_group tgl_community2_groups[] = {
INTEL_GPP(GPD0, GPD0, GPD11), /* GPD */
INTEL_GPP(GPD0, GPD0, GPD_DRAM_RESETB), /* GPD */
};
static const struct pad_group tgl_community4_groups[] = {
INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 224), /* GPP_C */
INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E23, 256), /* GPP_E */
INTEL_GPP(GPP_C0, GPIO_RSVD_3, GPIO_RSVD_8),
INTEL_GPP(GPP_C0, GPP_C0, GPP_C23), /* GPP_C */
INTEL_GPP(GPP_C0, GPP_F0, GPP_F_CLK_LOOPBK), /* GPP_F */
INTEL_GPP(GPP_C0, GPP_L_BKLTEN, GPP_MLK_RSTB), /* GPP_HVCMOS */
INTEL_GPP(GPP_C0, GPP_E0, GPP_E_CLK_LOOPBK), /* GPP_E */
INTEL_GPP(GPP_C0, GPP_JTAG_TDO, GPP_DBG_PMODE), /* GPP_JTAG */
};
static const struct pad_group tgl_community5_groups[] = {
INTEL_GPP_BASE(GPP_R0, GPP_R0, GPP_R7, 288), /* GPP_R */
INTEL_GPP_BASE(GPP_C0, GPP_S0, GPP_S7, 320), /* GPP_S */
INTEL_GPP(GPP_R0, GPP_R0, GPP_R7), /* GPP_R */
INTEL_GPP(GPP_R0, GPP_SPI_IO_2, GPP_CLK_LOOPBK), /* GPP_SPI */
};
static const struct pad_community tgl_communities[TOTAL_GPIO_COMM] = {
/* GPP G, B, A */
[COMM_0] = {
static const struct pad_community tgl_communities[] = {
[COMM_0] = { /* GPP B, T, A */
.port = PID_GPIOCOM0,
.first_pad = GPP_G0,
.last_pad = GPP_A23,
.first_pad = GPP_B0,
.last_pad = GPP_A24,
.num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
@ -96,18 +86,17 @@ static const struct pad_community tgl_communities[TOTAL_GPIO_COMM] = {
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPP_GBA",
.name = "GPP_BTA",
.acpi_path = "\\_SB.PCI0.GPIO",
.reset_map = rst_map_com0,
.num_reset_vals = ARRAY_SIZE(rst_map_com0),
.reset_map = rst_map,
.num_reset_vals = ARRAY_SIZE(rst_map),
.groups = tgl_community0_groups,
.num_groups = ARRAY_SIZE(tgl_community0_groups),
},
/* GPP H, D, F */
[COMM_1] = {
[COMM_1] = { /* GPP S, D, H, U, VGPIO */
.port = PID_GPIOCOM1,
.first_pad = GPP_H0,
.last_pad = GPP_F19,
.first_pad = GPP_S0,
.last_pad = vI2S2_RXD,
.num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
@ -116,18 +105,17 @@ static const struct pad_community tgl_communities[TOTAL_GPIO_COMM] = {
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPP_HDF",
.name = "GPP_SDHU",
.acpi_path = "\\_SB.PCI0.GPIO",
.reset_map = rst_map,
.num_reset_vals = ARRAY_SIZE(rst_map),
.groups = tgl_community1_groups,
.num_groups = ARRAY_SIZE(tgl_community1_groups),
},
/* GPD */
[COMM_2] = {
[COMM_2] = { /* GPD */
.port = PID_GPIOCOM2,
.first_pad = GPD0,
.last_pad = GPD11,
.last_pad = GPD_DRAM_RESETB,
.num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
@ -138,16 +126,15 @@ static const struct pad_community tgl_communities[TOTAL_GPIO_COMM] = {
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPD",
.acpi_path = "\\_SB.PCI0.GPIO",
.reset_map = rst_map,
.num_reset_vals = ARRAY_SIZE(rst_map),
.reset_map = rst_map_com2,
.num_reset_vals = ARRAY_SIZE(rst_map_com2),
.groups = tgl_community2_groups,
.num_groups = ARRAY_SIZE(tgl_community2_groups),
},
/* GPP C, E */
[COMM_3] = {
[COMM_4] = { /* GPP F, C, HVCOS, E, JTAG */
.port = PID_GPIOCOM4,
.first_pad = GPP_C0,
.last_pad = GPP_E23,
.last_pad = GPP_DBG_PMODE,
.num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
@ -156,18 +143,17 @@ static const struct pad_community tgl_communities[TOTAL_GPIO_COMM] = {
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPP_CE",
.name = "GPP_FCE",
.acpi_path = "\\_SB.PCI0.GPIO",
.reset_map = rst_map,
.num_reset_vals = ARRAY_SIZE(rst_map),
.groups = tgl_community4_groups,
.num_groups = ARRAY_SIZE(tgl_community4_groups),
},
/* GPP R, S */
[COMM_4] = {
[COMM_5] = { /* GPP R, SPI */
.port = PID_GPIOCOM5,
.first_pad = GPP_R0,
.last_pad = GPP_S7,
.last_pad = GPP_CLK_LOOPBK,
.num_gpi_regs = NUM_GPIO_COM5_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
@ -176,7 +162,7 @@ static const struct pad_community tgl_communities[TOTAL_GPIO_COMM] = {
.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
.name = "GPP_RS",
.name = "GPP_CPU_VBPIO",
.acpi_path = "\\_SB.PCI0.GPIO",
.reset_map = rst_map,
.num_reset_vals = ARRAY_SIZE(rst_map),

7
src/soc/intel/tigerlake/include/soc/gpio.h
View File

@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Intel Corp.
* Copyright (C) 2020 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -19,6 +19,9 @@
#include <soc/gpio_defs.h>
#include <intelblocks/gpio.h>
#define CROS_GPIO_DEVICE_NAME "INT3455:00"
#define CROS_GPIO_COMM0_NAME "INT34C5:00"
#define CROS_GPIO_COMM1_NAME "INT34C5:01"
#define CROS_GPIO_COMM4_NAME "INT34C5:02"
#define CROS_GPIO_COMM5_NAME "INT34C5:03"
#endif

464
src/soc/intel/tigerlake/include/soc/gpio_defs.h
View File

@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Intel Corp.
* Copyright (C) 2020 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -21,7 +21,6 @@
#endif
#include <soc/gpio_soc_defs.h>
#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */
#define NUM_GPIO_COMx_GPI_REGS(n) \
@ -43,222 +42,264 @@
* IOxAPIC IRQs for the GPIOs
*/
/* Group G */
#define GPP_G0_IRQ 0x18
#define GPP_G1_IRQ 0x19
#define GPP_G2_IRQ 0x1a
#define GPP_G3_IRQ 0x1b
#define GPP_G4_IRQ 0x1c
#define GPP_G5_IRQ 0x1d
#define GPP_G6_IRQ 0x1e
#define GPP_G7_IRQ 0x1f
/* Group B */
#define GPP_B0_IRQ 0x20
#define GPP_B1_IRQ 0x21
#define GPP_B2_IRQ 0x22
#define GPP_B3_IRQ 0x23
#define GPP_B4_IRQ 0x24
#define GPP_B5_IRQ 0x25
#define GPP_B6_IRQ 0x26
#define GPP_B7_IRQ 0x27
#define GPP_B8_IRQ 0x28
#define GPP_B9_IRQ 0x29
#define GPP_B10_IRQ 0x2a
#define GPP_B11_IRQ 0x2b
#define GPP_B12_IRQ 0x2c
#define GPP_B13_IRQ 0x2d
#define GPP_B14_IRQ 0x2e
#define GPP_B15_IRQ 0x2f
#define GPP_B16_IRQ 0x30
#define GPP_B17_IRQ 0x31
#define GPP_B18_IRQ 0x32
#define GPP_B19_IRQ 0x33
#define GPP_B20_IRQ 0x34
#define GPP_B21_IRQ 0x35
#define GPP_B22_IRQ 0x36
#define GPP_B23_IRQ 0x37
#define GPP_B0_IRQ 0x18
#define GPP_B1_IRQ 0x19
#define GPP_B2_IRQ 0x1A
#define GPP_B3_IRQ 0x1B
#define GPP_B4_IRQ 0x1C
#define GPP_B5_IRQ 0x1D
#define GPP_B6_IRQ 0x1E
#define GPP_B7_IRQ 0x1F
#define GPP_B8_IRQ 0x20
#define GPP_B9_IRQ 0x21
#define GPP_B10_IRQ 0x22
#define GPP_B11_IRQ 0x23
#define GPP_B12_IRQ 0x24
#define GPP_B13_IRQ 0x25
#define GPP_B14_IRQ 0x26
#define GPP_B15_IRQ 0x27
#define GPP_B16_IRQ 0x28
#define GPP_B17_IRQ 0x29
#define GPP_B18_IRQ 0x2A
#define GPP_B19_IRQ 0x2B
#define GPP_B20_IRQ 0x2C
#define GPP_B21_IRQ 0x2D
#define GPP_B22_IRQ 0x2E
#define GPP_B23_IRQ 0x2F
/* Group T */
#define GPP_T0_IRQ 0x30
#define GPP_T1_IRQ 0x31
#define GPP_T2_IRQ 0x32
#define GPP_T3_IRQ 0x33
#define GPP_T4_IRQ 0x34
#define GPP_T5_IRQ 0x35
#define GPP_T6_IRQ 0x36
#define GPP_T7_IRQ 0x37
#define GPP_T8_IRQ 0x38
#define GPP_T9_IRQ 0x39
#define GPP_T10_IRQ 0x3A
#define GPP_T11IRQ 0x3B
#define GPP_T12_IRQ 0x3C
#define GPP_T13_IRQ 0x3D
#define GPP_T14_IRQ 0x3E
#define GPP_T15_IRQ 0x3F
/* Group A */
#define GPP_A0_IRQ 0x38
#define GPP_A1_IRQ 0x39
#define GPP_A2_IRQ 0x3a
#define GPP_A3_IRQ 0x3b
#define GPP_A4_IRQ 0x3c
#define GPP_A5_IRQ 0x3d
#define GPP_A6_IRQ 0x3e
#define GPP_A7_IRQ 0x3f
#define GPP_A8_IRQ 0x40
#define GPP_A9_IRQ 0x41
#define GPP_A10_IRQ 0x42
#define GPP_A11_IRQ 0x43
#define GPP_A12_IRQ 0x44
#define GPP_A13_IRQ 0x45
#define GPP_A14_IRQ 0x46
#define GPP_A15_IRQ 0x47
#define GPP_A16_IRQ 0x48
#define GPP_A17_IRQ 0x49
#define GPP_A18_IRQ 0x4a
#define GPP_A19_IRQ 0x4b
#define GPP_A20_IRQ 0x4c
#define GPP_A21_IRQ 0x4d
#define GPP_A22_IRQ 0x4e
#define GPP_A23_IRQ 0x4f
#define GPP_A0_IRQ 0x40
#define GPP_A1_IRQ 0x41
#define GPP_A2_IRQ 0x42
#define GPP_A3_IRQ 0x43
#define GPP_A4_IRQ 0x44
#define GPP_A5_IRQ 0x45
#define GPP_A6_IRQ 0x46
#define GPP_A7_IRQ 0x47
#define GPP_A8_IRQ 0x48
#define GPP_A9_IRQ 0x49
#define GPP_A10_IRQ 0x4A
#define GPP_A11_IRQ 0x4B
#define GPP_A12_IRQ 0x4C
#define GPP_A13_IRQ 0x4D
#define GPP_A14_IRQ 0x4E
#define GPP_A15_IRQ 0x4F
#define GPP_A16_IRQ 0x50
#define GPP_A17_IRQ 0x51
#define GPP_A18_IRQ 0x52
#define GPP_A19_IRQ 0x53
#define GPP_A20_IRQ 0x54
#define GPP_A21_IRQ 0x55
#define GPP_A22_IRQ 0x56
#define GPP_A23_IRQ 0x57
/* Group R */
#define GPP_R0_IRQ 0x58
#define GPP_R1_IRQ 0x59
#define GPP_R2_IRQ 0x5A
#define GPP_R3_IRQ 0x5B
#define GPP_R4_IRQ 0x5C
#define GPP_R5_IRQ 0x5D
#define GPP_R6_IRQ 0x5E
#define GPP_R7_IRQ 0x5F
/* Group H */
#define GPP_H0_IRQ 0x70
#define GPP_H1_IRQ 0x71
#define GPP_H2_IRQ 0x72
#define GPP_H3_IRQ 0x73
#define GPP_H4_IRQ 0x74
#define GPP_H5_IRQ 0x75
#define GPP_H6_IRQ 0x76
#define GPP_H7_IRQ 0x77
#define GPP_H8_IRQ 0x18
#define GPP_H9_IRQ 0x19
#define GPP_H10_IRQ 0x1a
#define GPP_H11_IRQ 0x1b
#define GPP_H12_IRQ 0x1c
#define GPP_H13_IRQ 0x1d
#define GPP_H14_IRQ 0x1e
#define GPP_H15_IRQ 0x1f
#define GPP_H16_IRQ 0x20
#define GPP_H17_IRQ 0x21
#define GPP_H18_IRQ 0x22
#define GPP_H19_IRQ 0x23
#define GPP_H20_IRQ 0x24
#define GPP_H21_IRQ 0x25
#define GPP_H22_IRQ 0x26
#define GPP_H23_IRQ 0x27
/* Group D */
#define GPP_D0_IRQ 0x28
#define GPP_D1_IRQ 0x29
#define GPP_D2_IRQ 0x2a
#define GPP_D3_IRQ 0x2b
#define GPP_D4_IRQ 0x2c
#define GPP_D5_IRQ 0x2d
#define GPP_D6_IRQ 0x2e
#define GPP_D7_IRQ 0x2f
#define GPP_D8_IRQ 0x30
#define GPP_D9_IRQ 0x31
#define GPP_D10_IRQ 0x32
#define GPP_D11_IRQ 0x33
#define GPP_D12_IRQ 0x34
#define GPP_D13_IRQ 0x35
#define GPP_D14_IRQ 0x36
#define GPP_D15_IRQ 0x37
#define GPP_D16_IRQ 0x38
#define GPP_D17_IRQ 0x39
#define GPP_D18_IRQ 0x3a
#define GPP_D19_IRQ 0x3b
/* Group F */
#define GPP_F0_IRQ 0x40
#define GPP_F1_IRQ 0x41
#define GPP_F2_IRQ 0x42
#define GPP_F3_IRQ 0x43
#define GPP_F4_IRQ 0x44
#define GPP_F5_IRQ 0x45
#define GPP_F6_IRQ 0x46
#define GPP_F7_IRQ 0x47
#define GPP_F8_IRQ 0x48
#define GPP_F9_IRQ 0x49
#define GPP_F10_IRQ 0x4a
#define GPP_F11_IRQ 0x4b
#define GPP_F12_IRQ 0x4c
#define GPP_F13_IRQ 0x4d
#define GPP_F14_IRQ 0x4e
#define GPP_F15_IRQ 0x4f
#define GPP_F16_IRQ 0x50
#define GPP_F17_IRQ 0x51
#define GPP_F18_IRQ 0x52
#define GPP_F19_IRQ 0x53
/* Group GPD */
#define GPD0_IRQ 0x64
#define GPD1_IRQ 0x65
#define GPD2_IRQ 0x66
#define GPD3_IRQ 0x67
#define GPD4_IRQ 0x68
#define GPD5_IRQ 0x69
#define GPD6_IRQ 0x6a
#define GPD7_IRQ 0x6b
#define GPD8_IRQ 0x6c
#define GPD9_IRQ 0x6d
#define GPD10_IRQ 0x6e
#define GPD11_IRQ 0x6f
/* Group C */
#define GPP_C0_IRQ 0x5a
#define GPP_C1_IRQ 0x5b
#define GPP_C2_IRQ 0x5c
#define GPP_C3_IRQ 0x5d
#define GPP_C4_IRQ 0x5e
#define GPP_C5_IRQ 0x5f
#define GPP_C6_IRQ 0x60
#define GPP_C7_IRQ 0x61
#define GPP_C8_IRQ 0x62
#define GPP_C9_IRQ 0x63
#define GPP_C10_IRQ 0x64
#define GPP_C11_IRQ 0x65
#define GPP_C12_IRQ 0x66
#define GPP_C13_IRQ 0x67
#define GPP_C14_IRQ 0x68
#define GPP_C15_IRQ 0x69
#define GPP_C16_IRQ 0x6a
#define GPP_C17_IRQ 0x6b
#define GPP_C18_IRQ 0x6c
#define GPP_C19_IRQ 0x6d
#define GPP_C20_IRQ 0x6e
#define GPP_C21_IRQ 0x6f
#define GPP_C22_IRQ 0x70
#define GPP_C23_IRQ 0x71
/* Group E */
#define GPP_E0_IRQ 0x72
#define GPP_E1_IRQ 0x73
#define GPP_E2_IRQ 0x74
#define GPP_E3_IRQ 0x75
#define GPP_E4_IRQ 0x76
#define GPP_E5_IRQ 0x77
#define GPP_E6_IRQ 0x18
#define GPP_E7_IRQ 0x19
#define GPP_E8_IRQ 0x1a
#define GPP_E9_IRQ 0x1b
#define GPP_E10_IRQ 0x1c
#define GPP_E11_IRQ 0x1d
#define GPP_E12_IRQ 0x1e
#define GPP_E13_IRQ 0x1f
#define GPP_E14_IRQ 0x20
#define GPP_E15_IRQ 0x21
#define GPP_E16_IRQ 0x22
#define GPP_E17_IRQ 0x23
#define GPP_E18_IRQ 0x24
#define GPP_E19_IRQ 0x25
#define GPP_E20_IRQ 0x26
#define GPP_E21_IRQ 0x27
#define GPP_E22_IRQ 0x28
#define GPP_E23_IRQ 0x29
/* Group R*/
#define GPP_R0_IRQ 0x50
#define GPP_R1_IRQ 0x51
#define GPP_R2_IRQ 0x52
#define GPP_R3_IRQ 0x53
#define GPP_R4_IRQ 0x54
#define GPP_R5_IRQ 0x55
#define GPP_R6_IRQ 0x56
#define GPP_R7_IRQ 0x57
#define GPD0_IRQ 0x60
#define GPD1_IRQ 0x61
#define GPD2_IRQ 0x62
#define GPD3_IRQ 0x63
#define GPD4_IRQ 0x64
#define GPD5_IRQ 0x65
#define GPD6_IRQ 0x66
#define GPD7_IRQ 0x67
#define GPD8_IRQ 0x68
#define GPD9_IRQ 0x69
#define GPD10_IRQ 0x6A
#define GPD11_IRQ 0x6B
/* Group S */
#define GPP_S0_IRQ 0x5c
#define GPP_S1_IRQ 0x5d
#define GPP_S2_IRQ 0x5e
#define GPP_S3_IRQ 0x5f
#define GPP_S4_IRQ 0x60
#define GPP_S5_IRQ 0x61
#define GPP_S6_IRQ 0x62
#define GPP_S7_IRQ 0x63
#define GPP_S0_IRQ 0x6C
#define GPP_S1_IRQ 0x6D
#define GPP_S2_IRQ 0x6E
#define GPP_S3_IRQ 0x6F
#define GPP_S4_IRQ 0x70
#define GPP_S5_IRQ 0x71
#define GPP_S6_IRQ 0x72
#define GPP_S7_IRQ 0x73
/* Group H */
#define GPP_H0_IRQ 0x74
#define GPP_H1_IRQ 0x75
#define GPP_H2_IRQ 0x76
#define GPP_H3_IRQ 0x77
#define GPP_H4_IRQ 0x18
#define GPP_H5_IRQ 0x19
#define GPP_H6_IRQ 0x1A
#define GPP_H7_IRQ 0x1B
#define GPP_H8_IRQ 0x1C
#define GPP_H9_IRQ 0x1D
#define GPP_H10_IRQ 0x1E
#define GPP_H11_IRQ 0x1F
#define GPP_H12_IRQ 0x20
#define GPP_H13_IRQ 0x21
#define GPP_H14_IRQ 0x22
#define GPP_H15_IRQ 0x23
#define GPP_H16_IRQ 0x24
#define GPP_H17_IRQ 0x25
#define GPP_H18_IRQ 0x26
#define GPP_H19_IRQ 0x27
#define GPP_H20_IRQ 0x28
#define GPP_H21_IRQ 0x29
#define GPP_H22_IRQ 0x2A
#define GPP_H23_IRQ 0x2B
/* Group D */
#define GPP_D0_IRQ 0x2C
#define GPP_D1_IRQ 0x2D
#define GPP_D2_IRQ 0x2E
#define GPP_D3_IRQ 0x2F
#define GPP_D4_IRQ 0x30
#define GPP_D5_IRQ 0x31
#define GPP_D6_IRQ 0x32
#define GPP_D7_IRQ 0x33
#define GPP_D8_IRQ 0x34
#define GPP_D9_IRQ 0x35
#define GPP_D10_IRQ 0x36
#define GPP_D11_IRQ 0x37
#define GPP_D12_IRQ 0x38
#define GPP_D13_IRQ 0x39
#define GPP_D14_IRQ 0x3A
#define GPP_D15_IRQ 0x3B
#define GPP_D16_IRQ 0x3C
#define GPP_D17_IRQ 0x3D
#define GPP_D18_IRQ 0x3E
#define GPP_D19_IRQ 0x3F
/* Group U */
#define GPP_U0_IRQ 0x40
#define GPP_U1IRQ 0x41
#define GPP_U2_IRQ 0x42
#define GPP_U3_IRQ 0x43
#define GPP_U4_IRQ 0x44
#define GPP_U5_IRQ 0x45
#define GPP_U6_IRQ 0x46
#define GPP_U7_IRQ 0x47
#define GPP_U8_IRQ 0x48
#define GPP_U9_IRQ 0x49
#define GPP_U10_IRQ 0x4A
#define GPP_U11_IRQ 0x4B
#define GPP_U12_IRQ 0x4C
#define GPP_U13_IRQ 0x4D
#define GPP_U14_IRQ 0x4E
#define GPP_U15_IRQ 0x4F
#define GPP_U16_IRQ 0x50
#define GPP_U17_IRQ 0x51
#define GPP_U18_IRQ 0x52
#define GPP_U19_IRQ 0x53
#define GPP_VGPIO4_IRQ 0x54
/* Group F */
#define GPP_F0_IRQ 0x56
#define GPP_F1_IRQ 0x57
#define GPP_F2_IRQ 0x58
#define GPP_F3_IRQ 0x59
#define GPP_F4_IRQ 0x5A
#define GPP_F5_IRQ 0x5B
#define GPP_F6_IRQ 0x5C
#define GPP_F7_IRQ 0x5D
#define GPP_F8_IRQ 0x5E
#define GPP_F9_IRQ 0x5F
#define GPP_F10_IRQ 0x60
#define GPP_F11_IRQ 0x61
#define GPP_F12_IRQ 0x62
#define GPP_F13_IRQ 0x63
#define GPP_F14_IRQ 0x64
#define GPP_F15_IRQ 0x65
#define GPP_F16_IRQ 0x66
#define GPP_F17_IRQ 0x67
#define GPP_F18_IRQ 0x68
#define GPP_F19_IRQ 0x69
#define GPP_F20_IRQ 0x6A
#define GPP_F21_IRQ 0x6B
#define GPP_F22_IRQ 0x6C
#define GPP_F23_IRQ 0x6D
/* Group C */
#define GPP_C0_iIRQ 0x6E
#define GPP_C1_IRQ 0x6F
#define GPP_C2_IRQ 0x70
#define GPP_C3_IRQ 0x71
#define GPP_C4_IRQ 0x72
#define GPP_C5_IRQ 0x73
#define GPP_C6_IRQ 0x74
#define GPP_C7_IRQ 0x75
#define GPP_C8_IRQ 0x76
#define GPP_C9_IRQ 0x77
#define GPP_C10_IRQ 0x18
#define GPP_C11_IRQ 0x19
#define GPP_C12_IRQ 0x1A
#define GPP_C13_IRQ 0x1B
#define GPP_C14_IRQ 0x1C
#define GPP_C15_IRQ 0x1D
#define GPP_C16_IRQ 0x1E
#define GPP_C17_IRQ 0x1F
#define GPP_C18_IRQ 0x20
#define GPP_C19_IRQ 0x21
#define GPP_C20_IRQ 0x22
#define GPP_C21_IRQ 0x23
#define GPP_C22_IRQ 0x24
#define GPP_C23_IRQ 0x25
/* Group E */
#define GPP_E0_IRQ 0x26
#define GPP_E1_IRQ 0x27
#define GPP_E2_IRQ 0x28
#define GPP_E3_IRQ 0x29
#define GPP_E4_IRQ 0x30
#define GPP_E5_IRQ 0x31
#define GPP_E6_IRQ 0x32
#define GPP_E7_IRQ 0x33
#define GPP_E8_IRQ 0x34
#define GPP_E9_IRQ 0x35
#define GPP_E10_IRQ 0x36
#define GPP_E11_IRQ 0x37
#define GPP_E12_IRQ 0x38
#define GPP_E13_IRQ 0x39
#define GPP_E14_IRQ 0x3A
#define GPP_E15_IRQ 0x3B
#define GPP_E16_IRQ 0x3C
#define GPP_E17_IRQ 0x3D
#define GPP_E18_IRQ 0x3E
#define GPP_E19_IRQ 0x3F
#define GPP_E20_IRQ 0x40
#define GPP_E21_IRQ 0x41
#define GPP_E22_IRQ 0x42
#define GPP_E23_IRQ 0x43
/* Register defines. */
#define GPIO_MISCCFG 0x10
@ -269,8 +310,9 @@
#define GPI_INT_EN_0 0x110
#define GPI_SMI_STS_0 0x180
#define GPI_SMI_EN_0 0x1A0
#define PAD_CFG_BASE 0x600
#define PAD_CFG_BASE 0x700
#define GPIORXSTATE_MASK 0x1
#define GPIORXSTATE_SHIFT 1
#define GPIOTXSTATE_MASK 0x1
#endif

579
src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h
View File

@ -12,10 +12,8 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _SOC_TIGERLAKE_GPIO_SOC_DEFS_H_
#define _SOC_TIGERLAKE_GPIO_SOC_DEFS_H_
/*
* Most of the fixed numbers and macros are based on the GPP groups.
* The GPIO groups are accessed through register blocks called
@ -34,259 +32,354 @@
#define GPP_C 0xB
#define GPP_E 0xC
#define GPIO_NUM_GROUPS 11
#define GPIO_MAX_NUM_PER_GROUP 24
#define GPIO_MAX_NUM_PER_GROUP 27
#define COMM_0 0
#define COMM_1 1
#define COMM_2 2
/* GPIO community 3 is not exposed to be used and hence is skipped. */
#define COMM_4 3
#define COMM_5 4
/*
* GPIOs are ordered monotonically increasing to match ACPI/OS driver.
*/
/* Group G */
#define GPP_G0 0
#define GPP_G1 1
#define GPP_G2 2
#define GPP_G3 3
#define GPP_G4 4
#define GPP_G5 5
#define GPP_G6 6
#define GPP_G7 7
/* Group B */
#define GPP_B0 8
#define GPP_B1 9
#define GPP_B2 10
#define GPP_B3 11
#define GPP_B4 12
#define GPP_B5 13
#define GPP_B6 14
#define GPP_B7 15
#define GPP_B8 16
#define GPP_B9 17
#define GPP_B10 18
#define GPP_B11 19
#define GPP_B12 20
#define GPP_B13 21
#define GPP_B14 22
#define GPP_B15 23
#define GPP_B16 24
#define GPP_B17 25
#define GPP_B18 26
#define GPP_B19 27
#define GPP_B20 28
#define GPP_B21 29
#define GPP_B22 30
#define GPP_B23 31
#define GPIO_RSVD_0 32
#define GPIO_RSVD_1 33
#define GPP_B0 0
#define GPP_B1 1
#define GPP_B2 2
#define GPP_B3 3
#define GPP_B4 4
#define GPP_B5 5
#define GPP_B6 6
#define GPP_B7 7
#define GPP_B8 8
#define GPP_B9 9
#define GPP_B10 10
#define GPP_B11 11
#define GPP_B12 12
#define GPP_B13 13
#define GPP_B14 14
#define GPP_B15 15
#define GPP_B16 16
#define GPP_B17 17
#define GPP_B18 18
#define GPP_B19 19
#define GPP_B20 20
#define GPP_B21 21
#define GPP_B22 22
#define GPP_B23 23
#define GPP_B24 24 /* GSPI0_CLK_LOOPBK */
#define GPP_B25 25 /* GSPI1_CLK_LOOPBK */
/* Group T */
#define GPP_T0 26
#define GPP_T1 27
#define GPP_T2 28
#define GPP_T3 29
#define GPP_T4 30
#define GPP_T5 31
#define GPP_T6 32
#define GPP_T7 33
#define GPP_T8 34
#define GPP_T9 35
#define GPP_T10 36
#define GPP_T11 37
#define GPP_T12 38
#define GPP_T13 39
#define GPP_T14 40
#define GPP_T15 41
/* Group A */
#define GPP_A0 34
#define GPP_A1 35
#define GPP_A2 36
#define GPP_A3 37
#define GPP_A4 38
#define GPP_A5 39
#define GPP_A6 40
#define GPP_A7 41
#define GPP_A8 42
#define GPP_A9 43
#define GPP_A10 44
#define GPP_A11 45
#define GPP_A12 46
#define GPP_A13 47
#define GPP_A14 48
#define GPP_A15 49
#define GPP_A16 50
#define GPP_A17 51
#define GPP_A18 52
#define GPP_A19 53
#define GPP_A20 54
#define GPP_A21 55
#define GPP_A22 56
#define GPP_A23 57
#define GPP_A0 42
#define GPP_A1 43
#define GPP_A2 44
#define GPP_A3 45
#define GPP_A4 46
#define GPP_A5 47
#define GPP_A6 48
#define GPP_A7 49
#define GPP_A8 50
#define GPP_A9 51
#define GPP_A10 52
#define GPP_A11 53
#define GPP_A12 54
#define GPP_A13 55
#define GPP_A14 56
#define GPP_A15 57
#define GPP_A16 58
#define GPP_A17 59
#define GPP_A18 60
#define GPP_A19 61
#define GPP_A20 62
#define GPP_A21 63
#define GPP_A22 64
#define GPP_A23 65
#define GPP_A24 66 /* ESPI_CLK_LOOPBK */
#define NUM_GPIO_COM0_PADS (GPP_A23 - GPP_G0 + 1)
/* Group H */
#define GPP_H0 58
#define GPP_H1 59
#define GPP_H2 60
#define GPP_H3 61
#define GPP_H4 62
#define GPP_H5 63
#define GPP_H6 64
#define GPP_H7 65
#define GPP_H8 66
#define GPP_H9 67
#define GPP_H10 68
#define GPP_H11 69
#define GPP_H12 70
#define GPP_H13 71
#define GPP_H14 72
#define GPP_H15 73
#define GPP_H16 74
#define GPP_H17 75
#define GPP_H18 76
#define GPP_H19 77
#define GPP_H20 78
#define GPP_H21 79
#define GPP_H22 80
#define GPP_H23 81
/* Group D */
#define GPP_D0 82
#define GPP_D1 83
#define GPP_D2 84
#define GPP_D3 85
#define GPP_D4 86
#define GPP_D5 87
#define GPP_D6 88
#define GPP_D7 89
#define GPP_D8 90
#define GPP_D9 91
#define GPP_D10 92
#define GPP_D11 93
#define GPP_D12 94
#define GPP_D13 95
#define GPP_D14 96
#define GPP_D15 97
#define GPP_D16 98
#define GPP_D17 99
#define GPP_D18 100
#define GPP_D19 101
#define GPIO_RSVD_2 102
/* Group F */
#define GPP_F0 103
#define GPP_F1 104
#define GPP_F2 105
#define GPP_F3 106
#define GPP_F4 107
#define GPP_F5 108
#define GPP_F6 109
#define GPP_F7 110
#define GPP_F8 111
#define GPP_F9 112
#define GPP_F10 113
#define GPP_F11 114
#define GPP_F12 115
#define GPP_F13 116
#define GPP_F14 117
#define GPP_F15 118
#define GPP_F16 119
#define GPP_F17 120
#define GPP_F18 121
#define GPP_F19 122
#define NUM_GPIO_COM1_PADS (GPP_F19 - GPP_H0 + 1)
/* Group GPD */
#define GPD0 123
#define GPD1 124
#define GPD2 125
#define GPD3 126
#define GPD4 127
#define GPD5 128
#define GPD6 129
#define GPD7 130
#define GPD8 131
#define GPD9 132
#define GPD10 133
#define GPD11 134
#define NUM_GPIO_COM2_PADS (GPD11 - GPD0 + 1)
/* Group C */
#define GPP_C0 135
#define GPP_C1 136
#define GPP_C2 137
#define GPP_C3 138
#define GPP_C4 139
#define GPP_C5 140
#define GPP_C6 141
#define GPP_C7 142
#define GPP_C8 143
#define GPP_C9 144
#define GPP_C10 145
#define GPP_C11 146
#define GPP_C12 147
#define GPP_C13 148
#define GPP_C14 149
#define GPP_C15 150
#define GPP_C16 151
#define GPP_C17 152
#define GPP_C18 153
#define GPP_C19 154
#define GPP_C20 155
#define GPP_C21 156
#define GPP_C22 157
#define GPP_C23 158
#define GPIO_RSVD_3 159
#define GPIO_RSVD_4 160
#define GPIO_RSVD_5 161
#define GPIO_RSVD_6 162
#define GPIO_RSVD_7 163
#define GPIO_RSVD_8 164
/* Group E */
#define GPP_E0 165
#define GPP_E1 166
#define GPP_E2 167
#define GPP_E3 168
#define GPP_E4 169
#define GPP_E5 170
#define GPP_E6 171
#define GPP_E7 172
#define GPP_E8 173
#define GPP_E9 174
#define GPP_E10 175
#define GPP_E11 176
#define GPP_E12 177
#define GPP_E13 178
#define GPP_E14 179
#define GPP_E15 180
#define GPP_E16 181
#define GPP_E17 182
#define GPP_E18 183
#define GPP_E19 184
#define GPP_E20 185
#define GPP_E21 186
#define GPP_E22 187
#define GPP_E23 188
#define NUM_GPIO_COM4_PADS (GPP_E23 - GPP_C0 + 1)
/* Group R*/
#define GPP_R0 189
#define GPP_R1 190
#define GPP_R2 191
#define GPP_R3 192
#define GPP_R4 193
#define GPP_R5 194
#define GPP_R6 195
#define GPP_R7 196
#define NUM_GPIO_COM0_PADS (GPP_A24 - GPP_B0 + 1)
/* Group S */
#define GPP_S0 197
#define GPP_S1 198
#define GPP_S2 199
#define GPP_S3 200
#define GPP_S4 201
#define GPP_S5 202
#define GPP_S6 203
#define GPP_S7 204
#define GPP_S0 67
#define GPP_S1 68
#define GPP_S2 69
#define GPP_S3 70
#define GPP_S4 71
#define GPP_S5 72
#define GPP_S6 73
#define GPP_S7 74
#define NUM_GPIO_COM5_PADS (GPP_S7 - GPP_R0 + 1)
/* Group H */
#define GPP_H0 75
#define GPP_H1 76
#define GPP_H2 77
#define GPP_H3 78
#define GPP_H4 79
#define GPP_H5 80
#define GPP_H6 81
#define GPP_H7 82
#define GPP_H8 83
#define GPP_H9 84
#define GPP_H10 85
#define GPP_H11 86
#define GPP_H12 87
#define GPP_H13 88
#define GPP_H14 89
#define GPP_H15 90
#define GPP_H16 91
#define GPP_H17 92
#define GPP_H18 93
#define GPP_H19 94
#define GPP_H20 95
#define GPP_H21 96
#define GPP_H22 97
#define GPP_H23 98
#define TOTAL_PADS 205
/* Group D */
#define GPP_D0 99
#define GPP_D1 100
#define GPP_D2 101
#define GPP_D3 102
#define GPP_D4 103
#define GPP_D5 104
#define GPP_D6 105
#define GPP_D7 106
#define GPP_D8 107
#define GPP_D9 108
#define GPP_D10 109
#define GPP_D11 110
#define GPP_D12 111
#define GPP_D13 112
#define GPP_D14 113
#define GPP_D15 114
#define GPP_D16 115
#define GPP_D17 116
#define GPP_D18 117
#define GPP_D19 118
#define GPP_GSPI2_CLK_LOOPBK 119
#define COMM_0 0
#define COMM_1 1
#define COMM_2 2
#define COMM_3 3
#define COMM_4 4
#define TOTAL_GPIO_COMM 5
/* Group U */
#define GPP_U0 120
#define GPP_U1 121
#define GPP_U2 122
#define GPP_U3 123
#define GPP_U4 124
#define GPP_U5 125
#define GPP_U6 126
#define GPP_U7 127
#define GPP_U8 128
#define GPP_U9 129
#define GPP_U10 130
#define GPP_U11 131
#define GPP_U12 132
#define GPP_U13 133
#define GPP_U14 134
#define GPP_U15 135
#define GPP_U16 136
#define GPP_U17 137
#define GPP_U18 138
#define GPP_U19 139
#define GPP_GSPI3_CLK_LOOPBK 140
#define GPP_GSPI4_CLK_LOOPBK 141
#define GPP_GSPI5_CLK_LOOPBK 142
#define GPP_GSPI6_CLK_LOOPBK 143
/* Group VGPIO */
#define CNV_BTEN 144
#define CNV_BT_HOST_WAKEB 145
#define CNV_BT_IF_SELECT 146
#define vCNV_BT_UART_TXD 147
#define vCNV_BT_UART_RXD 148
#define vCNV_BT_UART_CTS_B 149
#define vCNV_BT_UART_RTS_B 150
#define vCNV_MFUART1_TXD 151
#define vCNV_MFUART1_RXD 152
#define vCNV_MFUART1_CTS_B 153
#define vCNV_MFUART1_RTS_B 154
#define vUART0_TXD 155
#define vUART0_RXD 156
#define vUART0_CTS_B 157
#define vUART0_RTS_B 158
#define vISH_UART0_TXD 159
#define vISH_UART0_RXD 160
#define vISH_UART0_CTS_B 161
#define vISH_UART0_RTS_B 162
#define vCNV_BT_I2S_BCLK 163
#define vCNV_BT_I2S_WS_SYNC 164
#define vCNV_BT_I2S_SDO 165
#define vCNV_BT_I2S_SDI 166
#define vI2S2_SCLK 167
#define vI2S2_SFRM 168
#define vI2S2_TXD 169
#define vI2S2_RXD 170
#define NUM_GPIO_COM1_PADS (vI2S2_RXD - GPP_S0 + 1)
/* Group GPD */
#define GPD0 171
#define GPD1 172
#define GPD2 173
#define GPD3 174
#define GPD4 175
#define GPD5 176
#define GPD6 177
#define GPD7 178
#define GPD8 179
#define GPD9 180
#define GPD10 181
#define GPD11 182
#define GPD_INPUT3VSEL 183
#define GPD_SLP_LANB 184
#define GPD__SLP_SUSB 185
#define GPD_WAKEB 186
#define GPD_DRAM_RESETB 187
#define NUM_GPIO_COM2_PADS (GPD_DRAM_RESETB - GPD0 + 1)
/* Group C */
#define GPP_C0 188
#define GPP_C1 189
#define GPP_C2 190
#define GPP_C3 191
#define GPP_C4 192
#define GPP_C5 193
#define GPP_C6 194
#define GPP_C7 195
#define GPP_C8 196
#define GPP_C9 197
#define GPP_C10 198
#define GPP_C11 199
#define GPP_C12 200
#define GPP_C13 201
#define GPP_C14 202
#define GPP_C15 203
#define GPP_C16 204
#define GPP_C17 205
#define GPP_C18 206
#define GPP_C19 207
#define GPP_C20 208
#define GPP_C21 209
#define GPP_C22 210
#define GPP_C23 211
/* Group F */
#define GPP_F0 212
#define GPP_F1 213
#define GPP_F2 214
#define GPP_F3 215
#define GPP_F4 216
#define GPP_F5 217
#define GPP_F6 218
#define GPP_F7 219
#define GPP_F8 220
#define GPP_F9 221
#define GPP_F10 222
#define GPP_F11 223
#define GPP_F12 224
#define GPP_F13 225
#define GPP_F14 226
#define GPP_F15 227
#define GPP_F16 228
#define GPP_F17 229
#define GPP_F18 230
#define GPP_F19 231
#define GPP_F20 232
#define GPP_F21 233
#define GPP_F22 234
#define GPP_F23 235
#define GPP_F_CLK_LOOPBK 236
/* Group HVCMOS */
#define GPP_L_BKLTEN 237
#define GPP_L_BKLTCTL 238
#define GPP_L_VDDEN 239
#define GPP_SYS_PWROK 240
#define GPP_SYS_RESETB 241
#define GPP_MLK_RSTB 242
/* Group E */
#define GPP_E0 243
#define GPP_E1 244
#define GPP_E2 245
#define GPP_E3 246
#define GPP_E4 247
#define GPP_E5 248
#define GPP_E6 249
#define GPP_E7 250
#define GPP_E8 251
#define GPP_E9 252
#define GPP_E10 253
#define GPP_E11 254
#define GPP_E12 255
#define GPP_E13 256
#define GPP_E14 257
#define GPP_E15 258
#define GPP_E16 259
#define GPP_E17 260
#define GPP_E18 261
#define GPP_E19 262
#define GPP_E20 263
#define GPP_E21 264
#define GPP_E22 265
#define GPP_E23 266
#define GPP_E_CLK_LOOPBK 267
/* Group JTAG */
#define GPP_JTAG_TDO 268
#define GPP_JTAG_X 269
#define GPP_JTAG_PRDYB 270
#define GPP_JTAG_PREQB 271
#define GPP_CPU_TRSTB 272
#define GPP_JTAG_TDI 273
#define GPP_JTAG_TMS 274
#define GPP_JTAG_TCK 275
#define GPP_DBG_PMODE 276
#define NUM_GPIO_COM4_PADS (GPP_DBG_PMODE - GPP_C0 + 1)
/* Group R */
#define GPP_R0 277
#define GPP_R1 278
#define GPP_R2 279
#define GPP_R3 280
#define GPP_R4 281
#define GPP_R5 282
#define GPP_R6 283
#define GPP_R7 284
/* Group SPI */
#define GPP_SPI_IO_2 285
#define GPP_SPI_IO_3 286
#define GPP_SPI_MOSI_IO_0 287
#define GPP_SPI_MOSI_IO_1 288
#define GPP_SPI_TPM_CSB 289
#define GPP_SPI_FLASH_0_CSB 290
#define GPP_SPI_FLASH_1_CSB 291
#define GPP_SPI_CLK 292
#define GPP_CLK_LOOPBK 293
#define NUM_GPIO_COM5_PADS (GPP_CLK_LOOPBK - GPP_R0 + 1)
#define TOTAL_GPIO_COMM (COMM_5 + 1)
#define TOTAL_PADS 294
#endif

5
src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
View File

@ -60,12 +60,15 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->PcieClkSrcUsage[i] = 0xff;
}
memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
sizeof(config->PcieClkSrcClkReq));
m_cfg->PrmrrSize = config->PrmrrSize;
m_cfg->EnableC6Dram = config->enable_c6dram;
/* Disable BIOS Guard */
m_cfg->BiosGuard = 0;
/* UART Debug Log*/
/* UART Debug Log */
m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ?
DEBUG_INTERFACE_UART : DEBUG_INTERFACE_TRACEHUB;
m_cfg->PcdIsaSerialUartBase = 0x0;

2
src/superio/aspeed/ast2400/superio.c
View File

@ -35,7 +35,7 @@ static void ast2400_init(struct device *dev)
pnp_enter_conf_mode(dev);
pnp_set_logical_device(dev);
/* In ESPI mode must write 0 to IRQ level on every LDN */
pnp_write_config(dev, 0x70, 0);
pnp_write_config(dev, 0x71, 0);
pnp_exit_conf_mode(dev);
}

121
src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h
View File

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -355,7 +355,17 @@ typedef struct {
/** Offset 0x01B7 - Reserved
**/
UINT8 Reserved11[178];
UINT8 Reserved11[166];
/** Offset 0x025D - IMGU CLKOUT Configuration
The configuration of IMGU CLKOUT, 0: Disable;<b>1: Enable</b>.
$EN_DIS
**/
UINT8 ImguClkOutEn[5];
/** Offset 0x0262 - Reserved
**/
UINT8 Reserved12[7];
/** Offset 0x0269 - RpClockReqMsgEnable
**/
@ -367,7 +377,37 @@ typedef struct {
/** Offset 0x026E - Reserved
**/
UINT8 Reserved12[8];
UINT8 Reserved13[3];
/** Offset 0x0271 - Program GPIOs for LFP on DDI port-A device
0=Disabled,1(Default)=eDP, 2=MIPI DSI
0:Disabled, 1:eDP, 2:MIPI DSI
**/
UINT8 DdiPortAConfig;
/** Offset 0x0272 - Program GPIOs for LFP on DDI port-B device
0(Default)=Disabled,1=eDP, 2=MIPI DSI
0:Disabled, 1:eDP, 2:MIPI DSI
**/
UINT8 DdiPortBConfig;
/** Offset 0x0273 - Enable or disable HPD of DDI port A
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPortAHpd;
/** Offset 0x0274 - Enable or disable HPD of DDI port B
0=Disable, 1(Default)=Enable
$EN_DIS
**/
UINT8 DdiPortBHpd;
/** Offset 0x0275 - Enable or disable HPD of DDI port C
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPortCHpd;
/** Offset 0x0276 - Enable or disable HPD of DDI port 1
0=Disable, 1(Default)=Enable
@ -375,9 +415,41 @@ typedef struct {
**/
UINT8 DdiPort1Hpd;
/** Offset 0x0277 - Reserved
/** Offset 0x0277 - Enable or disable HPD of DDI port 2
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 Reserved13[6];
UINT8 DdiPort2Hpd;
/** Offset 0x0278 - Enable or disable HPD of DDI port 3
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPort3Hpd;
/** Offset 0x0279 - Enable or disable HPD of DDI port 4
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPort4Hpd;
/** Offset 0x027A - Enable or disable DDC of DDI port A
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPortADdc;
/** Offset 0x027B - Enable or disable DDC of DDI port B
0=Disable, 1(Default)=Enable
$EN_DIS
**/
UINT8 DdiPortBDdc;
/** Offset 0x027C - Enable or disable DDC of DDI port C
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPortCDdc;
/** Offset 0x027D - Enable DDC setting of DDI Port 1
0(Default)=Disable, 1=Enable
@ -385,9 +457,27 @@ typedef struct {
**/
UINT8 DdiPort1Ddc;
/** Offset 0x027E - Reserved
/** Offset 0x027E - Enable DDC setting of DDI Port 2
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 Reserved14[129];
UINT8 DdiPort2Ddc;
/** Offset 0x027F - Enable DDC setting of DDI Port 3
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPort3Ddc;
/** Offset 0x0280 - Enable DDC setting of DDI Port 4
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPort4Ddc;
/** Offset 0x0281 - Reserved
**/
UINT8 Reserved14[126];
/** Offset 0x02FF - DMI Gen3 Root port preset values per lane
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
@ -507,9 +597,14 @@ typedef struct {
**/
UINT8 PcieClkSrcUsage[16];
/** Offset 0x0587 - Reserved
/** Offset 0x0587 - ClkReq-to-ClkSrc mapping
Number of ClkReq signal assigned to ClkSrc
**/
UINT8 Reserved25[21];
UINT8 PcieClkSrcClkReq[16];
/** Offset 0x0597 - Reserved
**/
UINT8 Reserved25[5];
/** Offset 0x059C - Enable PCIE RP Mask
Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
@ -737,7 +832,7 @@ typedef struct {
/** Offset 0x0775 - Reserved
**/
UINT8 Reserved39[315];
UINT8 Reserved39[355];
} FSP_M_CONFIG;
/** Fsp M UPD Configuration
@ -756,11 +851,11 @@ typedef struct {
**/
FSP_M_CONFIG FspmConfig;
/** Offset 0x08B0
/** Offset 0x08D8
**/
UINT8 UnusedUpdSpace23[6];
UINT8 UnusedUpdSpace24[6];
/** Offset 0x08B6
/** Offset 0x08DE
**/
UINT16 UpdTerminator;
} FSPM_UPD;

4
src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h
View File

@ -1,6 +1,6 @@
/** @file
Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@ -385,7 +385,7 @@ typedef struct {
/** Offset 0x03FE - HECI3 state
The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed.
0: disable, 1: enable
DEPRECATED 0: disable, 1: enable
$EN_DIS
**/
UINT8 Heci3Enabled;

43
util/superiotool/ite.c
View File

@ -942,6 +942,49 @@ static const struct superio_registers reg_table[] = {
{0x8761, "IT8761E", {
{EOT}}},
{0x8772, "IT8772F", {
{NOLDN, NULL,
{0x20,0x21,0x22,0x23,0x24,0x2e,0x2f,EOT},
{0x87,0x72,0x02,0x00,0x00,0x00,0x00,EOT}},
{0x1, "COM1",
{0x30,0x60,0x61,0x70,0xf0,0xf1,EOT},
{0x00,0x03,0xf8,0x04,0x00,0x50,EOT}},
{0x4, "Environment controller",
{0x30,0x60,0x61,0x62,0x63,0x70,0xf0,0xf1,0xf2,
0xf3,0xf4,0xf5,0xf6,0xf9,0xfa,0xfb,EOT},
{0x00,0x02,0x90,0x02,0x30,0x09,0x00,0x00,0x00,
0x00,0x00,MISC,MISC,MISC,MISC,MISC,EOT}},
{0x5, "Keyboard",
{0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf0,EOT},
{0x01,0x00,0x60,0x00,0x64,0x01,0x02,0x08,EOT}},
{0x6, "Mouse",
{0x30,0x70,0x71,0xf0,EOT},
{0x00,0x0c,0x02,0x00,EOT}},
{0x7, "GPIO",
{0x25,0x26,0x27,0x28,0x29,0x2a,0x2b,0x2c, /* 25 .. 2c */
0x60,0x61,0x62,0x63, /* 60 .. 64 */
0x70,0x71,0x72,0x73,0x74, /* 70 .. 74 */
0xb0,0xb1,0xb2,0xb3,0xb4, /* b0 .. b4 */
0xb8,0xb9,0xba,0xbb,0xbc,0xbd, /* b8 .. bd */
0xc0,0xc1,0xc2,0xc3,0xc4, /* c0 .. c4 */
0xc8,0xc9,0xca,0xcb,0xcc,0xcd, /* c8 .. cd */
0xe0,0xe1,0xe2,0xe3,0xe4,0xe9, /* e0 .. e9 */
0xf0,0xf1,0xf2,0xf3,0xf4,0xf5, /* f0 .. f5 */
0xf6,0xf7,0xf8,0xf9,0xfa,0xfb, /* f6 .. fb */
EOT},
{0x00,0xf3,0x00,0x00,0x00,0x00,MISC,0x01, /* 25 .. 2c */
0x00,0x00,0x00,0x00, /* 60 .. 64 */
0x00,0x00,0x20,0x38,0x00, /* 70 .. 74 */
0x00,0x00,0x00,0x00,0x00, /* b0 .. b4 */
0x20,0x00,0x00,0x00,0x00,0x00, /* b8 .. bd */
0x01,0x00,0x00,0x40,0x00, /* c0 .. c4 */
0x01,0x00,0x00,0x00,0x00,0x00, /* c8 .. cd */
0x00,0x00,0x00,0x00,0x00,MISC, /* e0 .. e9 */
0x00,0x00,0x00,0x00,0x00,0x00, /* f0 .. f6 */
0x00,0x00,0x00,0x00,0x00,0x00, /* f6 .. fb */
EOT}},
{0xa, "Consumer IR",
{0x30,0x60,0x61,0x70,0xf0,EOT},
{0x00,0x03,0x10,0x0b,0x06,EOT}},
{EOT}}},
{0x8780, "IT8780F", {
{EOT}}},