soc/intel/*: Get rid of custom microcode caching
Get rid of custom microcode caching in MPinit and SGX code and use the caching introduced in intel_microcode_find() instead. Change-Id: If3ccd4dcff221c88839ffeafa812f4c38cede63f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Patrick Georgi
parent
7aaea37e37
commit
3fa23b8c00
@@ -9,11 +9,10 @@
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#include <device/device.h>
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/* Parallel MP initialization support. */
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static const void *microcode_patch;
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static void pre_mp_init(void)
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{
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intel_microcode_load_unlocked(microcode_patch);
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const void *patch = intel_microcode_find();
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intel_microcode_load_unlocked(patch);
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/* Setup MTRRs based on physical address size. */
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x86_setup_mtrrs_with_detect();
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@@ -32,7 +31,7 @@ static int get_cpu_count(void)
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static void get_microcode_info(const void **microcode, int *parallel)
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{
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*microcode = microcode_patch;
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*microcode = intel_microcode_find();
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*parallel = !intel_ht_supported();
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}
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@@ -98,8 +97,6 @@ static const struct mp_ops mp_ops = {
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void mp_init_cpus(struct bus *cpu_bus)
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{
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microcode_patch = intel_microcode_find();
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if (mp_init_with_smm(cpu_bus, &mp_ops))
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printk(BIOS_ERR, "MP initialization failure.\n");
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}
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@@ -123,8 +123,6 @@ static void model_2065x_init(struct device *cpu)
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}
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/* MP initialization support. */
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static const void *microcode_patch;
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static void pre_mp_init(void)
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{
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/* Setup MTRRs based on physical address size. */
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@@ -149,8 +147,7 @@ static int get_cpu_count(void)
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static void get_microcode_info(const void **microcode, int *parallel)
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{
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microcode_patch = intel_microcode_find();
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*microcode = microcode_patch;
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*microcode = intel_microcode_find();
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*parallel = !intel_ht_supported();
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}
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@@ -160,6 +157,7 @@ static void per_cpu_smm_trigger(void)
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smm_relocate();
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/* After SMM relocation a 2nd microcode load is required. */
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const void *microcode_patch = intel_microcode_find();
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intel_microcode_load_unlocked(microcode_patch);
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}
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@@ -466,8 +466,6 @@ static void model_206ax_init(struct device *cpu)
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}
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/* MP initialization support. */
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static const void *microcode_patch;
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static void pre_mp_init(void)
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{
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/* Setup MTRRs based on physical address size. */
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@@ -492,8 +490,7 @@ static int get_cpu_count(void)
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static void get_microcode_info(const void **microcode, int *parallel)
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{
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microcode_patch = intel_microcode_find();
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*microcode = microcode_patch;
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*microcode = intel_microcode_find();
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*parallel = !intel_ht_supported();
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}
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@@ -503,6 +500,7 @@ static void per_cpu_smm_trigger(void)
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smm_relocate();
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/* After SMM relocation a 2nd microcode load is required. */
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const void *microcode_patch = intel_microcode_find();
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intel_microcode_load_unlocked(microcode_patch);
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}
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