google/snow: enable GPIO entries and CHROMEOS in building

These were not separable or it would have been two CLs.

Enable CHROMEOS configure option on snow. Write gpio support code for
the mainboard.  Right now the GPIO just returns hard-wired values for
"virtual" GPIOs.

Add a chromeos.c file for snow, needed to build.

This is tested and creates gpio table entries that our hardware can use.

Lots still missing but we can now start to fill in the blanks, since
we have enabled CHROMEOS for this board. We are getting further into
the process of actually booting a real kernel.

Change-Id: I5fdc68b0b76f9b2172271e991e11bef16f5adb27
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2467
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/vendorcode/google/chromeos/Kconfig

@@ -61,6 +61,7 @@ config FLASHMAP_OFFSET
 	hex "Flash Map Offset"
 	default 0x00670000 if NORTHBRIDGE_INTEL_SANDYBRIDGE
 	default 0x00610000 if NORTHBRIDGE_INTEL_IVYBRIDGE
+	default 0
 	help
 	  Offset of flash map in firmware image
 

src/vendorcode/google/chromeos/Makefile.inc

@@ -19,9 +19,9 @@
 
 romstage-y += chromeos.c
 ramstage-y += chromeos.c
-romstage-y += vbnv.c
-ramstage-y += vbnv.c
-romstage-y += vboot.c
+romstage-$(CONFIG_ARCH_X86) += vbnv.c
+ramstage-$(CONFIG_ARCH_X86) += vbnv.c
+romstage-$(CONFIG_ARCH_X86) += vboot.c
 ramstage-y += gnvs.c
 romstage-y += fmap.c
 ramstage-y += fmap.c