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cpu/amd: Use common AMD's MSR

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Phase 1. Due to the size of the effort, this CL is broken into several
phases.

Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
This commit is contained in:
Elyes HAOUAS
2018-10-12 10:54:30 +02:00
committed by Patrick Georgi
parent e64a585374
commit 400ce55566
82 changed files with 412 additions and 510 deletions
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3
src/cpu/amd/agesa/family12/fixme.c
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@@ -14,6 +14,7 @@
*/
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <AGESA.h>
#include "amdlib.h"
@@ -75,7 +76,7 @@ void amd_initmmio(void)
Address MSR register.
*/
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader);
/* Enable Non-Post Memory in CPU */
PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1;

12
src/cpu/amd/agesa/family12/model_12_init.c
View File

@@ -15,6 +15,8 @@
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
#include <device/device.h>
#include <string.h>
@@ -23,13 +25,7 @@
#include <cpu/x86/lapic.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/multicore.h>
#include <cpu/amd/amdfam12.h>
#define MCG_CAP 0x179
# define MCA_BANKS_MASK 0xff
#define MC0_STATUS 0x401
static void model_12_init(struct device *dev)
{
@@ -55,12 +51,12 @@ static void model_12_init(struct device *dev)
disable_cache();
/* zero the machine check error status registers */
msr = rdmsr(MCG_CAP);
msr = rdmsr(IA32_MCG_CAP);
num_banks = msr.lo & MCA_BANKS_MASK;
msr.lo = 0;
msr.hi = 0;
for (i = 0; i < num_banks; i++)
wrmsr(MC0_STATUS + (i * 4), msr);
wrmsr(IA32_MC0_STATUS + (i * 4), msr);
enable_cache();

6
src/cpu/amd/agesa/family14/fixme.c
View File

@@ -14,7 +14,7 @@
*/
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <AGESA.h>
#include "amdlib.h"
@@ -78,7 +78,7 @@ void amd_initmmio(void)
Address MSR register.
*/
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader);
/* Set Ontario Link Data */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0xE0);
@@ -96,7 +96,7 @@ void amd_initmmio(void)
/* Set P-state 0 (1600 MHz) early to save a few ms of boot time */
MsrReg = 0;
LibAmdMsrWrite (0xC0010062, &MsrReg, &StdHeader);
LibAmdMsrWrite(PS_CTL_REG, &MsrReg, &StdHeader);
}
void amd_initenv(void)

12
src/cpu/amd/agesa/family14/model_14_init.c
View File

@@ -15,6 +15,8 @@
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
#include <device/device.h>
#include <string.h>
@@ -23,15 +25,9 @@
#include <cpu/x86/lapic.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/amdfam14.h>
#include <arch/acpi.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#define MCG_CAP 0x179
# define MCA_BANKS_MASK 0xff
#define MC0_STATUS 0x401
static void model_14_init(struct device *dev)
{
u8 i;
@@ -78,12 +74,12 @@ static void model_14_init(struct device *dev)
x86_enable_cache();
/* zero the machine check error status registers */
msr = rdmsr(MCG_CAP);
msr = rdmsr(IA32_MCG_CAP);
num_banks = msr.lo & MCA_BANKS_MASK;
msr.lo = 0;
msr.hi = 0;
for (i = 0; i < num_banks; i++)
wrmsr(MC0_STATUS + (i * 4), msr);
wrmsr(IA32_MC0_STATUS + (i * 4), msr);
/* Enable the local CPU APICs */
setup_lapic();

3
src/cpu/amd/agesa/family15tn/fixme.c
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@@ -14,6 +14,7 @@
*/
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <AGESA.h>
#include "amdlib.h"
@@ -71,7 +72,7 @@ void amd_initmmio(void)
Address MSR register.
*/
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader);
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;

18
src/cpu/amd/agesa/family15tn/model_15_init.c
View File

@@ -15,8 +15,10 @@
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/smm.h>
#include <cpu/amd/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/x86/smm.h>
#include <device/device.h>
#include <string.h>
#include <cpu/x86/pae.h>
@@ -24,8 +26,6 @@
#include <cpu/x86/lapic.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/amdfam15.h>
#include <arch/acpi.h>
#include <northbridge/amd/agesa/agesa_helper.h>
@@ -73,12 +73,12 @@ static void model_15_init(struct device *dev)
x86_enable_cache();
/* zero the machine check error status registers */
msr = rdmsr(MCG_CAP);
msr = rdmsr(IA32_MCG_CAP);
num_banks = msr.lo & MCA_BANKS_MASK;
msr.lo = 0;
msr.hi = 0;
for (i = 0; i < num_banks; i++)
wrmsr(MC0_STATUS + (i * 4), msr);
wrmsr(IA32_MC0_STATUS + (i * 4), msr);
/* Enable the local CPU APICs */
setup_lapic();
@@ -108,14 +108,14 @@ static void model_15_init(struct device *dev)
printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx);
/* Set SMM base address for this CPU */
msr = rdmsr(MSR_SMM_BASE);
msr = rdmsr(SMM_BASE_MSR);
msr.lo = SMM_BASE - (cpu_idx * 0x400);
wrmsr(MSR_SMM_BASE, msr);
wrmsr(SMM_BASE_MSR, msr);
/* Enable the SMM memory window */
msr = rdmsr(MSR_SMM_MASK);
msr = rdmsr(SMM_MASK_MSR);
msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */
wrmsr(MSR_SMM_MASK, msr);
wrmsr(SMM_MASK_MSR, msr);
}
/* Write protect SMM space with SMMLOCK. */

5
src/cpu/amd/agesa/family15tn/udelay.c
View File

@@ -21,6 +21,7 @@
*/
#include <cpu/x86/msr.h>
#include <cpu/amd/msr.h>
#include <cpu/x86/tsc.h>
#include <delay.h>
#include <stdint.h>
@@ -36,11 +37,11 @@ void udelay(uint32_t us)
tsc_start = rdtscll();
/* Get the P-state. This determines which MSR to read */
msr = rdmsr(0xc0010063);
msr = rdmsr(PS_STS_REG);
pstate_idx = msr.lo & 0x07;
/* Get FID and VID for current P-State */
msr = rdmsr(0xc0010064 + pstate_idx);
msr = rdmsr(PSTATE_0_MSR + pstate_idx);
/* Extract the FID and VID values */
fid = msr.lo & 0x3f;

3
src/cpu/amd/agesa/family16kb/fixme.c
View File

@@ -14,6 +14,7 @@
*/
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <AGESA.h>
#include "amdlib.h"
@@ -71,7 +72,7 @@ void amd_initmmio(void)
Address MSR register.
*/
MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader);
LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader);
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;

8
src/cpu/amd/agesa/family16kb/model_16_init.c
View File

@@ -15,6 +15,8 @@
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
#include <device/device.h>
#include <string.h>
@@ -23,8 +25,6 @@
#include <cpu/x86/lapic.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/amdfam16.h>
#include <arch/acpi.h>
#include <northbridge/amd/agesa/agesa_helper.h>
@@ -71,12 +71,12 @@ static void model_16_init(struct device *dev)
x86_enable_cache();
/* zero the machine check error status registers */
msr = rdmsr(MCG_CAP);
msr = rdmsr(IA32_MCG_CAP);
num_banks = msr.lo & MCA_BANKS_MASK;
msr.lo = 0;
msr.hi = 0;
for (i = 0; i < num_banks; i++)
wrmsr(MC0_STATUS + (i * 4), msr);
wrmsr(IA32_MC0_STATUS + (i * 4), msr);
/* Enable the local CPU APICs */
setup_lapic();

20
src/cpu/amd/car/cache_as_ram.inc
View File

@@ -17,6 +17,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/amd/msr.h>
#include <cpu/amd/mtrr.h>
#define CacheSize CONFIG_DCACHE_RAM_SIZE
@@ -27,9 +28,6 @@
/* For CAR with Fam10h. */
#define CacheSizeAPStack CONFIG_DCACHE_AP_STACK_SIZE
#define MSR_MCFG_BASE 0xC0010058
#define MSR_BU_CFG2 0xC001102A
#define jmp_if_not_k8(x) comisd %xmm2, %xmm1; jae x
#define jmp_if_k8(x) comisd %xmm2, %xmm1; jb x
#define jmp_if_not_fam15h(x) comisd %xmm3, %xmm1; jb x
@@ -130,13 +128,13 @@ CAR_FAM10_out:
* Errata 193: Disable clean copybacks to L3 cache to allow cached ROM.
* Re-enable it in after RAM is initialized and before CAR is disabled.
*/
movl $MSR_BU_CFG2, %ecx
movl $BU_CFG2_MSR, %ecx
rdmsr
bts $15, %eax /* Set bit 15 in EDX:EAX (bit 15 in EAX). */
wrmsr
/* Erratum 343, RevGuide for Fam10h, Pub#41322 Rev. 3.33 */
movl $MSR_BU_CFG2, %ecx
movl $BU_CFG2_MSR, %ecx
rdmsr
bts $35-32, %edx /* Set bit 35 in EDX:EAX (bit 3 in EDX). */
wrmsr
@@ -171,7 +169,7 @@ CAR_FAM10_errata_applied:
#else
#error "bad MMCONF_BUS_NUMBER value"
#endif
movl $MSR_MCFG_BASE, %ecx
movl $MMIO_CONF_BASE, %ecx
wrmsr
#endif
@@ -179,7 +177,7 @@ CAR_FAM10_out_post_errata:
/* Fam15h APIC IDs do not depend on NB config bit 54 */
jmp_if_not_fam15h(skip_nb54_set)
movl $0xc001001f, %ecx /* NB_CFG_MSR */
movl $NB_CFG_MSR, %ecx
rdmsr
bts $(54 - 32), %edx /* Set NB config bit 54 */
wrmsr
@@ -227,7 +225,7 @@ skip_cu_check:
jmp_if_not_fam15h(CAR_FAM15_errata_applied)
/* Erratum 714, RevGuide for Fam15h, Pub#48063 Rev. 3.24 */
movl $MSR_BU_CFG2, %ecx
movl $BU_CFG2_MSR, %ecx
rdmsr
bts $8, %eax /* Set bit 8 in EDX:EAX (bit 8 in EAX). */
wrmsr
@@ -410,7 +408,7 @@ fam10_mtrr_setup_complete:
post_code(0xa1)
/* Disable conversion of INVD to WBINVD (INVDWBINVD = 0) */
mov $0xc0010015, %ecx
mov $HWCR_MSR, %ecx
rdmsr
btr $4, %eax
wrmsr
@@ -522,7 +520,7 @@ CAR_FAM10_ap:
* system with no obvious clues of what went wrong.
*
* So, need to get the NodeID and CoreID at first.
* If NB_CFG bit 54 is set just use initial APIC ID, otherwise need
* If NB_CFG_MSR bit 54 is set just use initial APIC ID, otherwise need
* to reverse it.
*/
@@ -539,7 +537,7 @@ CAR_FAM10_ap:
shrl $24, %ebx
/* Get the nb cfg bit 54. */
movl $0xc001001f, %ecx /* NB_CFG_MSR */
movl $NB_CFG_MSR, %ecx
rdmsr
movl %edi, %ecx /* CoreID bits */
bt $(54 - 32), %edx

17
src/cpu/amd/car/disable_cache_as_ram.c
View File

@@ -21,6 +21,7 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/msr.h>
static __always_inline uint32_t amd_fam1x_cpu_family(void)
{
@@ -72,9 +73,9 @@ void disable_cache_as_ram_real(uint8_t skip_sharedc_config)
}
/* INVDWBINVD = 1 */
msr = rdmsr(0xc0010015);
msr = rdmsr(HWCR_MSR);
msr.lo |= (0x1 << 4);
wrmsr(0xc0010015, msr);
wrmsr(HWCR_MSR, msr);
family = amd_fam1x_cpu_family();
@@ -83,15 +84,15 @@ void disable_cache_as_ram_real(uint8_t skip_sharedc_config)
/* Family 15h or later */
/* DisSS = 0 */
msr = rdmsr(0xc0011020);
msr = rdmsr(LS_CFG_MSR);
msr.lo &= ~(0x1 << 28);
wrmsr(0xc0011020, msr);
wrmsr(LS_CFG_MSR, msr);
if (!skip_sharedc_config) {
/* DisSpecTlbRld = 0 */
msr = rdmsr(0xc0011021);
msr = rdmsr(IC_CFG_MSR);
msr.lo &= ~(0x1 << 9);
wrmsr(0xc0011021, msr);
wrmsr(IC_CFG_MSR, msr);
/* Erratum 714: SpecNbReqDis = 0 */
msr = rdmsr(BU_CFG2_MSR);
@@ -101,10 +102,10 @@ void disable_cache_as_ram_real(uint8_t skip_sharedc_config)
/* DisSpecTlbRld = 0 */
/* DisHwPf = 0 */
msr = rdmsr(0xc0011022);
msr = rdmsr(DC_CFG_MSR);
msr.lo &= ~(0x1 << 4);
msr.lo &= ~(0x1 << 13);
wrmsr(0xc0011022, msr);
wrmsr(DC_CFG_MSR, msr);
}
#endif
}

61
src/cpu/amd/family_10h-family_15h/defaults.h
View File

@@ -16,6 +16,7 @@
#include <northbridge/amd/amdmct/amddefs.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/msr.h>
/*
* Default MSR and errata settings.
@@ -33,7 +34,7 @@ static const struct {
0x00000000, 0x00000000,
0xFFFFFFFF, 0xFFFFFFFF },
{ SYSCFG, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
{ SYSCFG_MSR, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_ALL,
3 << 21, 0x00000000,
3 << 21, 0x00000000 }, /* [MtrrTom2En]=1,[TOM2EnWB] = 1*/
@@ -65,92 +66,92 @@ static const struct {
1 << 10, 0x00000000,
1 << 10, 0x00000000 }, /* [GartTblWkEn]=1 */
{ DC_CFG, AMD_FAM10_ALL, AMD_PTYPE_SVR,
{ DC_CFG_MSR, AMD_FAM10_ALL, AMD_PTYPE_SVR,
0x00000000, 0x00000004,
0x00000000, 0x0000000C }, /* Family 10h: [REQ_CTR] = 1 for Server */
{ DC_CFG, AMD_DR_Bx, AMD_PTYPE_SVR,
{ DC_CFG_MSR, AMD_DR_Bx, AMD_PTYPE_SVR,
0x00000000, 0x00000000,
0x00000000, 0x00000C00 }, /* Erratum 326 */
{ NB_CFG, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_DC | AMD_PTYPE_MC,
{ NB_CFG_MSR, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_DC | AMD_PTYPE_MC,
0x00000000, 1 << 22,
0x00000000, 1 << 22 }, /* [ApicInitIDLo]=1 */
{ NB_CFG, AMD_FAM15_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC,
{ NB_CFG_MSR, AMD_FAM15_ALL, AMD_PTYPE_DC | AMD_PTYPE_MC,
1 << 23, 0x00000000,
1 << 23, 0x00000000 }, /* Erratum 663: [bit 23]=1 */
{ BU_CFG2, AMD_DR_Bx, AMD_PTYPE_ALL,
{ BU_CFG2_MSR, AMD_DR_Bx, AMD_PTYPE_ALL,
1 << 29, 0x00000000,
1 << 29, 0x00000000 }, /* For Bx Smash1GPages=1 */
{ DC_CFG, AMD_FAM10_ALL, AMD_PTYPE_ALL,
{ DC_CFG_MSR, AMD_FAM10_ALL, AMD_PTYPE_ALL,
1 << 24, 0x00000000,
1 << 24, 0x00000000 }, /* Erratum #261 [DIS_PIGGY_BACK_SCRUB]=1 */
{ LS_CFG, AMD_DR_GT_B0, AMD_PTYPE_ALL,
{ LS_CFG_MSR, AMD_DR_GT_B0, AMD_PTYPE_ALL,
0 << 1, 0x00000000,
1 << 1, 0x00000000 }, /* IDX_MATCH_ALL=0 */
{ IC_CFG, AMD_OR_C0, AMD_PTYPE_ALL,
{ IC_CFG_MSR, AMD_OR_C0, AMD_PTYPE_ALL,
0x00000000, 1 << (39-32),
0x00000000, 1 << (39-32)}, /* C0 or above [DisLoopPredictor]=1 */
{ IC_CFG, AMD_OR_C0, AMD_PTYPE_ALL,
{ IC_CFG_MSR, AMD_OR_C0, AMD_PTYPE_ALL,
0xf << 1, 0x00000000,
0xf << 1, 0x00000000}, /* C0 or above [DisIcWayFilter]=0xf */
{ BU_CFG, AMD_DR_LT_B3, AMD_PTYPE_ALL,
{ BU_CFG_MSR, AMD_DR_LT_B3, AMD_PTYPE_ALL,
1 << 21, 0x00000000,
1 << 21, 0x00000000 }, /* Erratum #254 DR B1 BU_CFG[21]=1 */
1 << 21, 0x00000000 }, /* Erratum #254 DR B1 BU_CFG_MSR[21]=1 */
{ BU_CFG, AMD_DR_LT_B3, AMD_PTYPE_ALL,
{ BU_CFG_MSR, AMD_DR_LT_B3, AMD_PTYPE_ALL,
1 << 23, 0x00000000,
1 << 23, 0x00000000 }, /* Erratum #309 BU_CFG[23]=1 */
1 << 23, 0x00000000 }, /* Erratum #309 BU_CFG_MSR[23]=1 */
{ BU_CFG, AMD_FAM15_ALL, AMD_PTYPE_ALL,
{ BU_CFG_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0 << 10, 0x00000000,
1 << 10, 0x00000000 }, /* [DcacheAgressivePriority]=0 */
/* CPUID_EXT_FEATURES */
{ CPUIDFEATURES, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_DC | AMD_PTYPE_MC,
{ CPU_ID_FEATURES_MSR, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_DC | AMD_PTYPE_MC,
1 << 28, 0x00000000,
1 << 28, 0x00000000 }, /* [HyperThreadFeatEn]=1 */
{ CPUIDFEATURES, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_DC,
{ CPU_ID_FEATURES_MSR, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_DC,
0x00000000, 1 << (33-32),
0x00000000, 1 << (33-32) }, /* [ExtendedFeatEn]=1 */
{ DE_CFG, AMD_OR_B2, AMD_PTYPE_ALL,
{ DE_CFG_MSR, AMD_OR_B2, AMD_PTYPE_ALL,
1 << 10, 0x00000000,
1 << 10, 0x00000000 }, /* Bx [ResyncPredSingleDispDis]=1 */
{ BU_CFG2, AMD_DRBH_Cx, AMD_PTYPE_ALL,
{ BU_CFG2_MSR, AMD_DRBH_Cx, AMD_PTYPE_ALL,
0x00000000, 1 << (35-32),
0x00000000, 1 << (35-32) }, /* Erratum 343 (set to 0 after CAR, in post_cache_as_ram()/model_10xxx_init() ) */
{ BU_CFG3, AMD_OR_B2, AMD_PTYPE_ALL,
{ BU_CFG3_MSR, AMD_OR_B2, AMD_PTYPE_ALL,
0x00000000, 1 << (42-32),
0x00000000, 1 << (42-32)}, /* Bx [PwcDisableWalkerSharing]=1 */
{ BU_CFG3, AMD_OR_C0, AMD_PTYPE_ALL,
{ BU_CFG3_MSR, AMD_OR_C0, AMD_PTYPE_ALL,
1 << 22, 0x00000000,
1 << 22, 0x00000000}, /* C0 or above [PfcDoubleStride]=1 */
{ EX_CFG, AMD_OR_C0, AMD_PTYPE_ALL,
{ EX_CFG_MSR, AMD_OR_C0, AMD_PTYPE_ALL,
0x00000000, 1 << (54-32),
0x00000000, 1 << (54-32)}, /* C0 or above [LateSbzResync]=1 */
{ LS_CFG2, AMD_OR_C0, AMD_PTYPE_ALL,
{ LS_CFG2_MSR, AMD_OR_C0, AMD_PTYPE_ALL,
1 << 23, 0x00000000,
1 << 23, 0x00000000}, /* C0 or above [DisScbThreshold]=1 */
{ LS_CFG2, AMD_OR_C0, AMD_PTYPE_ALL,
{ LS_CFG2_MSR, AMD_OR_C0, AMD_PTYPE_ALL,
1 << 14, 0x00000000,
1 << 14, 0x00000000}, /* C0 or above [ForceSmcCheckFlowStDis]=1 */
{ LS_CFG2, AMD_OR_C0, AMD_PTYPE_ALL,
{ LS_CFG2_MSR, AMD_OR_C0, AMD_PTYPE_ALL,
1 << 12, 0x00000000,
1 << 12, 0x00000000}, /* C0 or above [ForceBusLockDis]=1 */
@@ -170,19 +171,19 @@ static const struct {
0x00000010, 0x00000000,
0xffffffff, 0x00000000}, /* OsvwId4 = 0x1 */
{ BU_CFG2, AMD_DR_Dx, AMD_PTYPE_ALL,
{ BU_CFG2_MSR, AMD_DR_Dx, AMD_PTYPE_ALL,
0x00000000, 1 << (50-32),
0x00000000, 1 << (50-32)}, /* D0 or Above, RdMmExtCfgQwEn*/
{ BU_CFG2, AMD_FAM15_ALL, AMD_PTYPE_ALL,
{ BU_CFG2_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0x00000000, 0x0 << (36-32),
0x00000000, 0x3 << (36-32)}, /* [ThrottleNbInterface]=0 */
{ BU_CFG2, AMD_FAM15_ALL, AMD_PTYPE_ALL,
{ BU_CFG2_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL,
1 << 10, 0x00000000,
1 << 10, 0x00000000}, /* [VicResyncChkEn]=1 */
{ BU_CFG2, AMD_FAM15_ALL, AMD_PTYPE_ALL,
{ BU_CFG2_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL,
1 << 11, 0x00000000,
1 << 11, 0x00000000}, /* Erratum 503: [bit 11]=1 */
@@ -198,7 +199,7 @@ static const struct {
0x00000000, 1 << (55 - 32),
0x00000000, 1 << (55 - 32)}, /* [PerfCtrExtCore]=1 */
{ IBS_OP_DATA3, AMD_FAM15_ALL, AMD_PTYPE_ALL,
{ IBS_OP_DATA3_MSR, AMD_FAM15_ALL, AMD_PTYPE_ALL,
0 << 16, 0x00000000,
1 << 16, 0x00000000}, /* [IbsDcMabHit]=0 */

74
src/cpu/amd/family_10h-family_15h/fidvid.c
View File

@@ -89,6 +89,7 @@ b.- prep_fid_change(...)
*/
#include <cpu/amd/msr.h>
#include <inttypes.h>
#include <northbridge/amd/amdht/AsPsDefs.h>
@@ -146,12 +147,12 @@ static void applyBoostFIDOffset(pci_devfn_t dev, uint32_t nodeid)
&& ((cpuid_ecx(0x80000008) & NC_MASK) == 5) ) {
u32 core = get_node_core_id_x().coreid;
u32 asymetricBoostThisCore = ((pci_read_config32(dev, 0x10C) >> (core*2))) & 3;
msr_t msr = rdmsr(PS_REG_BASE);
msr_t msr = rdmsr(PSTATE_0_MSR);
u32 cpuFid = msr.lo & PS_CPU_FID_MASK;
cpuFid = cpuFid + asymetricBoostThisCore;
msr.lo &= ~PS_CPU_FID_MASK;
msr.lo |= cpuFid;
wrmsr(PS_REG_BASE , msr);
wrmsr(PSTATE_0_MSR, msr);
} else if (is_fam15h()) {
uint32_t dword = pci_read_config32(NODE_PCI(nodeid, 4), 0x15c);
uint8_t boost_count = (dword >> 2) & 0x7;
@@ -173,12 +174,12 @@ static void enableNbPState1(pci_devfn_t dev)
u32 nbVid1 = (pci_read_config32(dev, 0x1F4) & NB_VID1_MASK) >> NB_VID1_SHIFT;
u32 i;
for (i = nbPState; i < NM_PS_REG; i++) {
msr_t msr = rdmsr(PS_REG_BASE + i);
msr_t msr = rdmsr(PSTATE_0_MSR + i);
if (msr.hi & PS_EN_MASK ) {
msr.hi |= NB_DID_M_ON;
msr.lo &= NB_VID_MASK_OFF;
msr.lo |= ( nbVid1 << NB_VID_POS);
wrmsr(PS_REG_BASE + i, msr);
wrmsr(PSTATE_0_MSR + i, msr);
}
}
}
@@ -189,10 +190,10 @@ static u8 setPStateMaxVal(pci_devfn_t dev)
{
u8 i, maxpstate=0;
for (i = 0; i < NM_PS_REG; i++) {
msr_t msr = rdmsr(PS_REG_BASE + i);
msr_t msr = rdmsr(PSTATE_0_MSR + i);
if (msr.hi & PS_IDD_VALUE_MASK) {
msr.hi |= PS_EN_MASK;
wrmsr(PS_REG_BASE + i, msr);
wrmsr(PSTATE_0_MSR + i, msr);
}
if (msr.hi & PS_EN_MASK) {
maxpstate = i;
@@ -215,16 +216,16 @@ static void dualPlaneOnly(pci_devfn_t dev)
&& (cpuRev & (AMD_DR_Cx | AMD_DR_Ex))) {
if ((pci_read_config32(dev, 0x1FC) & DUAL_PLANE_ONLY_MASK)
&& (pci_read_config32(dev, 0xA0) & PVI_MODE)) {
if (cpuid_edx(0x80000007) & CPB_MASK) {
if (cpuid_edx(CPUID_EXT_PM) & CPB_MASK) {
// revision E only, but E is apparently not supported yet, therefore untested
msr_t minPstate = rdmsr(0xC0010065);
wrmsr(0xC0010065, rdmsr(0xC0010068));
wrmsr(0xC0010068, minPstate);
msr_t minPstate = rdmsr(PSTATE_1_MSR);
wrmsr(PSTATE_1_MSR, rdmsr(PSTATE_4_MSR));
wrmsr(PSTATE_4_MSR, minPstate);
} else {
msr_t msr;
msr.lo=0; msr.hi=0;
wrmsr(0xC0010064, rdmsr(0xC0010068) );
wrmsr(0xC0010068, msr);
wrmsr(PSTATE_0_MSR, rdmsr(PSTATE_4_MSR));
wrmsr(PSTATE_4_MSR, msr);
}
//FIXME: CPTC2 and HTC_REG should get max per node, not per core ?
@@ -307,7 +308,7 @@ static void recalculateVsSlamTimeSettingOnCorePre(pci_devfn_t dev)
prep_fid_change, one might use F4x1[F0:E0] instead, but
theoretically MSRC001_00[68:64] are equal to them after
reset. */
msr = rdmsr(0xC0010064);
msr = rdmsr(PSTATE_0_MSR);
highVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F);
if (!(msr.hi & 0x80000000)) {
printk(BIOS_ERR,"P-state info in MSRC001_0064 is invalid !!!\n");
@@ -325,15 +326,16 @@ static void recalculateVsSlamTimeSettingOnCorePre(pci_devfn_t dev)
}
/* Get PSmax's index */
msr = rdmsr(0xC0010061);
msr = rdmsr(PS_LIM_REG);
bValue = (u8) ((msr.lo >> PS_MAX_VAL_SHFT) & BIT_MASK_3);
/* Get PSmax's VID */
msr = rdmsr(0xC0010064 + bValue);
msr = rdmsr(PSTATE_0_MSR + bValue);
lowVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F);
if (!(msr.hi & 0x80000000)) {
printk(BIOS_ERR,"P-state info in MSR%8x is invalid !!!\n",0xC0010064 + bValue);
lowVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0+(bValue*4))
printk(BIOS_ERR, "P-state info in MSR%8x is invalid !!!\n",
PSTATE_0_MSR + bValue);
lowVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0+(bValue*4))
>> PS_CPU_VID_SHFT) & 0x7F);
}
@@ -644,7 +646,7 @@ void prep_fid_change(void)
static void waitCurrentPstate(u32 target_pstate) {
msr_t initial_msr = rdmsr(TSC_MSR);
msr_t pstate_msr = rdmsr(CUR_PSTATE_MSR);
msr_t pstate_msr = rdmsr(PS_STS_REG);
msr_t tsc_msr;
u8 timedout;
@@ -655,7 +657,7 @@ static void waitCurrentPstate(u32 target_pstate) {
* misunderstand this...
*/
u32 corrected_timeout = ((pstate_msr.lo==1)
&& (!(rdmsr(0xC0010065).lo & NB_DID_M_ON)) ) ?
&& (!(rdmsr(PSTATE_1_MSR).lo & NB_DID_M_ON))) ?
WAIT_PSTATE_TIMEOUT*2 : WAIT_PSTATE_TIMEOUT;
msr_t timeout;
@@ -667,19 +669,19 @@ static void waitCurrentPstate(u32 target_pstate) {
// assuming TSC ticks at 1.25 ns per tick (800 MHz)
do {
pstate_msr = rdmsr(CUR_PSTATE_MSR);
pstate_msr = rdmsr(PS_STS_REG);
tsc_msr = rdmsr(TSC_MSR);
timedout = (tsc_msr.hi > timeout.hi)
|| ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo ));
} while ( (pstate_msr.lo != target_pstate) && (! timedout) );
if (pstate_msr.lo != target_pstate) {
msr_t limit_msr = rdmsr(0xc0010061);
msr_t limit_msr = rdmsr(PS_LIM_REG);
printk(BIOS_ERR, "*** APIC ID %02x: timed out waiting for P-state %01x. Current P-state %01x P-state current limit MSRC001_0061=%08x %08x\n",
cpuid_ebx(0x00000001) >> 24, target_pstate, pstate_msr.lo, limit_msr.hi, limit_msr.lo);
do { // should we just go on instead ?
pstate_msr = rdmsr(CUR_PSTATE_MSR);
pstate_msr = rdmsr(PS_STS_REG);
} while ( pstate_msr.lo != target_pstate );
}
}
@@ -689,10 +691,10 @@ static void set_pstate(u32 nonBoostedPState) {
uint8_t skip_wait;
// Transition P0 for calling core.
msr = rdmsr(0xC0010062);
msr = rdmsr(PS_CTL_REG);
msr.lo = nonBoostedPState;
wrmsr(0xC0010062, msr);
wrmsr(PS_CTL_REG, msr);
if (is_fam15h()) {
/* Do not wait for the first (even) set of cores to transition on Family 15h systems */
@@ -718,7 +720,7 @@ static void UpdateSinglePlaneNbVid(void)
/* copy higher voltage (lower VID) of NBVID & CPUVID to both */
for (i = 0; i < 5; i++) {
msr = rdmsr(PS_REG_BASE + i);
msr = rdmsr(PSTATE_0_MSR + i);
nbVid = (msr.lo & PS_CPU_VID_M_ON) >> PS_CPU_VID_SHFT;
cpuVid = (msr.lo & PS_NB_VID_M_ON) >> PS_NB_VID_SHFT;
@@ -729,7 +731,7 @@ static void UpdateSinglePlaneNbVid(void)
msr.lo = msr.lo & PS_BOTH_VID_OFF;
msr.lo = msr.lo | (u32) ((nbVid) << PS_NB_VID_SHFT);
msr.lo = msr.lo | (u32) ((nbVid) << PS_CPU_VID_SHFT);
wrmsr(PS_REG_BASE + i, msr);
wrmsr(PSTATE_0_MSR + i, msr);
}
}
}
@@ -751,16 +753,16 @@ static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid, u32 dev, u8 pviMode)
* for SVI and Single-Plane PVI Systems
*/
msr = rdmsr(0xc0010071);
msr = rdmsr(MSR_COFVID_STS);
startup_pstate = (msr.hi >> (32 - 32)) & 0x07;
/* Copy startup pstate to P1 and P0 MSRs. Set the maxvid for
* this node in P0. Then transition to P1 for corex and P0
* for core0. These setting will be cleared by the warm reset
*/
msr = rdmsr(0xC0010064 + startup_pstate);
wrmsr(0xC0010065, msr);
wrmsr(0xC0010064, msr);
msr = rdmsr(PSTATE_0_MSR + startup_pstate);
wrmsr(PSTATE_1_MSR, msr);
wrmsr(PSTATE_0_MSR, msr);
/* missing step 2 from BDKG , F3xDC[PstateMaxVal] =
* max(1,F3xDC[PstateMaxVal] ) because it would take
@@ -773,7 +775,7 @@ static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid, u32 dev, u8 pviMode)
msr.lo &= ~0xFE000000; // clear nbvid
msr.lo |= (newNbVid << 25);
wrmsr(0xC0010064, msr);
wrmsr(PSTATE_0_MSR, msr);
if (pviMode) { /* single plane*/
UpdateSinglePlaneNbVid();
@@ -944,14 +946,14 @@ static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll,u8 pviMode)
/* write newNbVid to P-state Reg's NbVid if its NbDid=0 */
for (i = 0; i < 5; i++) {
msr = rdmsr(0xC0010064 + i);
msr = rdmsr(PSTATE_0_MSR + i);
/* NbDid (bit 22 of P-state Reg) == 0 or NbVidUpdatedAll = 1 */
if ( (msr.hi & PS_IDD_VALUE_MASK)
&& (msr.hi & PS_EN_MASK)
&&(((msr.lo & PS_NB_DID_MASK) == 0) || NbVidUpdatedAll)) {
msr.lo &= PS_NB_VID_M_OFF;
msr.lo |= (newNbVid & 0x7F) << PS_NB_VID_SHFT;
wrmsr(0xC0010064 + i, msr);
wrmsr(PSTATE_0_MSR + i, msr);
}
}
@@ -962,7 +964,7 @@ static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll,u8 pviMode)
UpdateSinglePlaneNbVid();
}
/* For each core in the system, transition all cores to StartupPstate */
msr = rdmsr(0xC0010071);
msr = rdmsr(MSR_COFVID_STS);
StartupPstate = msr.hi & 0x07;
/* Set and wait for StartupPstate to set. */
@@ -1027,9 +1029,9 @@ void init_fidvid_stage2(u32 apicid, u32 nodeid)
if (!is_fam15h()) {
/* Set TSC to tick at the P0 ndfid rate */
msr = rdmsr(HWCR);
msr = rdmsr(HWCR_MSR);
msr.lo |= 1 << 24;
wrmsr(HWCR, msr);
wrmsr(HWCR_MSR, msr);
}
}

45
src/cpu/amd/family_10h-family_15h/init_cpus.c
View File

@@ -14,6 +14,7 @@
* GNU General Public License for more details.
*/
#include <cpu/amd/msr.h>
#include "init_cpus.h"
#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE)
@@ -39,7 +40,7 @@
#if IS_ENABLED(CONFIG_PCI_IO_CFG_EXT)
static void set_EnableCf8ExtCfg(void)
{
// set the NB_CFG[46]=1;
// set the NB_CFG_MSR[46]=1;
msr_t msr;
msr = rdmsr(NB_CFG_MSR);
// EnableCf8ExtCfg: We need that to access CONFIG_PCI_IO_CFG_EXT 4K range
@@ -332,9 +333,9 @@ static void STOP_CAR_AND_CPU(uint8_t skip_sharedc_config, uint32_t apicid)
/* Family 10h or earlier */
/* Disable L2 IC to L3 connection (Only for CAR) */
msr = rdmsr(BU_CFG2);
msr = rdmsr(BU_CFG2_MSR);
msr.lo &= ~(1 << ClLinesToNbDis);
wrmsr(BU_CFG2, msr);
wrmsr(BU_CFG2_MSR, msr);
} else {
/* Family 15h or later
* DRAM setup is delayed on Fam15 in order to prevent
@@ -739,13 +740,13 @@ static void AMD_Errata298(void)
}
if (affectedRev) {
msr = rdmsr(HWCR);
msr = rdmsr(HWCR_MSR);
msr.lo |= 0x08; /* Set TlbCacheDis bit[3] */
wrmsr(HWCR, msr);
wrmsr(HWCR_MSR, msr);
msr = rdmsr(BU_CFG);
msr = rdmsr(BU_CFG_MSR);
msr.lo |= 0x02; /* Set TlbForceMemTypeUc bit[1] */
wrmsr(BU_CFG, msr);
wrmsr(BU_CFG_MSR, msr);
msr = rdmsr(OSVW_ID_Length);
msr.lo |= 0x01; /* OS Visible Workaround - MSR */
@@ -805,7 +806,7 @@ static void AMD_SetupPSIVID_d(u32 platform_type, u8 node)
*/
for (i = 4; i >= 0; i--) {
msr = rdmsr(PS_REG_BASE + i);
msr = rdmsr(PSTATE_0_MSR + i);
/* Pstate valid? */
if (msr.hi & PS_EN_MASK) {
dword = pci_read_config32(NODE_PCI(i, 3), 0xA0);
@@ -1010,7 +1011,7 @@ void cpuSetAMDMSR(uint8_t node_id)
enable_experimental_memory_speed_boost = !!nvram;
uint32_t f3x1fc = pci_read_config32(NODE_PCI(node_id, 3), 0x1fc);
msr = rdmsr(FP_CFG);
msr = rdmsr(FP_CFG_MSR);
msr.hi &= ~(0x7 << (42-32)); /* DiDtCfg4 */
msr.hi |= (((f3x1fc >> 17) & 0x7) << (42-32));
msr.hi &= ~(0x1 << (41-32)); /* DiDtCfg5 */
@@ -1027,19 +1028,19 @@ void cpuSetAMDMSR(uint8_t node_id)
msr.lo |= (((f3x1fc >> 1) & 0x1f) << 18);
msr.lo &= ~(0x1 << 16); /* DiDtMode */
msr.lo |= ((f3x1fc & 0x1) << 16);
wrmsr(FP_CFG, msr);
wrmsr(FP_CFG_MSR, msr);
if (enable_experimental_memory_speed_boost) {
msr = rdmsr(BU_CFG3);
msr = rdmsr(BU_CFG3_MSR);
msr.lo |= (0x3 << 20); /* PfcStrideMul = 0x3 */
wrmsr(BU_CFG3, msr);
wrmsr(BU_CFG3_MSR, msr);
}
}
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB800)
if (revision & (AMD_DR_GT_D0 | AMD_FAM15_ALL)) {
/* Set up message triggered C1E */
msr = rdmsr(0xc0010055);
msr = rdmsr(MSR_INTPEND);
msr.lo &= ~0xffff; /* IOMsgAddr = ACPI_PM_EVT_BLK */
msr.lo |= ACPI_PM_EVT_BLK & 0xffff;
msr.lo |= (0x1 << 29); /* BmStsClrOnHltEn = 1 */
@@ -1047,11 +1048,11 @@ void cpuSetAMDMSR(uint8_t node_id)
msr.lo &= ~(0x1 << 28); /* C1eOnCmpHalt = 0 */
msr.lo &= ~(0x1 << 27); /* SmiOnCmpHalt = 0 */
}
wrmsr(0xc0010055, msr);
wrmsr(MSR_INTPEND, msr);
msr = rdmsr(0xc0010015);
msr = rdmsr(HWCR_MSR);
msr.lo |= (0x1 << 12); /* HltXSpCycEn = 1 */
wrmsr(0xc0010015, msr);
wrmsr(HWCR_MSR, msr);
}
if (revision & (AMD_DR_Ex | AMD_FAM15_ALL)) {
@@ -1063,9 +1064,9 @@ void cpuSetAMDMSR(uint8_t node_id)
if (enable_c_states) {
/* Set up the C-state base address */
msr_t c_state_addr_msr;
c_state_addr_msr = rdmsr(0xc0010073);
c_state_addr_msr = rdmsr(MSR_CSTATE_ADDRESS);
c_state_addr_msr.lo = ACPI_CPU_P_LVL2; /* CstateAddr = ACPI_CPU_P_LVL2 */
wrmsr(0xc0010073, c_state_addr_msr);
wrmsr(MSR_CSTATE_ADDRESS, c_state_addr_msr);
}
}
#else
@@ -1079,9 +1080,9 @@ void cpuSetAMDMSR(uint8_t node_id)
if (!enable_cpb) {
/* Disable Core Performance Boost */
msr = rdmsr(0xc0010015);
msr = rdmsr(HWCR_MSR);
msr.lo |= (0x1 << 25); /* CpbDis = 1 */
wrmsr(0xc0010015, msr);
wrmsr(HWCR_MSR, msr);
}
}
@@ -1826,12 +1827,12 @@ static void cpuInitializeMCA(void)
u8 i;
if (cpuid_edx(1) & 0x4080) { /* MCE and MCA (edx[7] and edx[14]) */
msr = rdmsr(MCG_CAP);
msr = rdmsr(IA32_MCG_CAP);
if (msr.lo & MCG_CTL_P) { /* MCG_CTL_P bit is set? */
msr.lo &= 0xFF;
msr.lo--;
msr.lo <<= 2; /* multiply the count by 4 */
reg = MC0_STA + msr.lo;
reg = IA32_MC0_STATUS + msr.lo;
msr.lo = msr.hi = 0;
for (i = 0; i < 4; i++) {
wrmsr(reg, msr);

10
src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
View File

@@ -16,6 +16,8 @@
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
#include <device/device.h>
#include <device/pci.h>
@@ -28,11 +30,7 @@
#include <cpu/amd/model_10xxx_rev.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/multicore.h>
#include <cpu/amd/msr.h>
#define MC0_STATUS 0x401
static inline uint8_t is_gt_rev_d(void)
{
@@ -110,12 +108,12 @@ static void model_10xxx_init(struct device *dev)
disable_cache();
/* zero the machine check error status registers */
msr = rdmsr(MCG_CAP);
msr = rdmsr(IA32_MCG_CAP);
num_banks = msr.lo & MCA_BANKS_MASK;
msr.lo = 0;
msr.hi = 0;
for (i = 0; i < num_banks; i++)
wrmsr(MC0_STATUS + (i * 4), msr);
wrmsr(IA32_MC0_STATUS + (i * 4), msr);
enable_cache();

5
src/cpu/amd/family_10h-family_15h/monotonic_timer.c
View File

@@ -16,12 +16,11 @@
#include <stdint.h>
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/msr.h>
#include <timer.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <northbridge/amd/amdht/AsPsDefs.h>
#include <cpu/amd/msr.h>
static struct monotonic_counter {
int initialized;
@@ -62,7 +61,7 @@ static void init_timer(void)
wrmsr(HWCR_MSR, msr);
/* Get core Pstate 0 frequency in MHz */
msr = rdmsr(0xC0010064 + boost_capable);
msr = rdmsr(PSTATE_0_MSR + boost_capable);
cpufid = (msr.lo & 0x3f);
cpudid = (msr.lo & 0x1c0) >> 6;
mono_counter.core_frequency = (100 * (cpufid + 0x10)) / (0x01 << cpudid);

16
src/cpu/amd/family_10h-family_15h/powernow_acpi.c
View File

@@ -19,6 +19,7 @@
#include <stdint.h>
#include <option.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/msr.h>
#include <arch/acpigen.h>
#include <cpu/amd/powernow.h>
#include <device/pci.h>
@@ -111,7 +112,7 @@ static void write_cstates_for_core(int coreID)
cstate.resource.space_id = ACPI_ADDRESS_SPACE_IO;
cstate.resource.bit_width = 8;
cstate.resource.bit_offset = 0;
cstate.resource.addrl = rdmsr(0xc0010073).lo + 1;
cstate.resource.addrl = rdmsr(MSR_CSTATE_ADDRESS).lo + 1;
cstate.resource.addrh = 0;
cstate.resource.resv = 1;
} else {
@@ -121,7 +122,7 @@ static void write_cstates_for_core(int coreID)
cstate.resource.space_id = ACPI_ADDRESS_SPACE_IO;
cstate.resource.bit_width = 8;
cstate.resource.bit_offset = 0;
cstate.resource.addrl = rdmsr(0xc0010073).lo;
cstate.resource.addrl = rdmsr(MSR_CSTATE_ADDRESS).lo;
cstate.resource.addrh = 0;
cstate.resource.resv = 1;
}
@@ -268,7 +269,8 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
if (fam15h)
/* Set P_LVL2 P_BLK entry */
*(((uint8_t *)pcontrol_blk) + 0x04) = (rdmsr(0xc0010073).lo + 1) & 0xff;
*(((uint8_t *)pcontrol_blk) + 0x04) =
(rdmsr(MSR_CSTATE_ADDRESS).lo + 1) & 0xff;
uint8_t pviModeFlag;
uint8_t Pstate_max;
@@ -296,15 +298,15 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
pviModeFlag = 0;
/* Get PSmax's index */
msr = rdmsr(0xC0010061);
msr = rdmsr(PS_LIM_REG);
Pstate_max = (uint8_t) ((msr.lo >> PS_MAX_VAL_SHFT) & ((fam15h)?BIT_MASK_7:BIT_MASK_3));
/* Determine if all enabled Pstates have the same fidvid */
uint8_t i;
uint8_t cpufid_prev = (rdmsr(0xC0010064).lo & 0x3f);
uint8_t cpufid_prev = (rdmsr(PSTATE_0_MSR).lo & 0x3f);
uint8_t all_enabled_cores_have_same_cpufid = 1;
for (i = 1; i < Pstate_max; i++) {
cpufid = rdmsr(0xC0010064 + i).lo & 0x3f;
cpufid = rdmsr(PSTATE_0_MSR + i).lo & 0x3f;
if (cpufid != cpufid_prev) {
all_enabled_cores_have_same_cpufid = 0;
break;
@@ -318,7 +320,7 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
/* Populate tables with all Pstate information */
for (Pstate_num = 0; Pstate_num < Pstate_max; Pstate_num++) {
/* Get power state information */
msr = rdmsr(0xC0010064 + Pstate_num + boost_count);
msr = rdmsr(PSTATE_0_MSR + Pstate_num + boost_count);
cpufid = (msr.lo & 0x3f);
cpudid = (msr.lo & 0x1c0) >> 6;
cpuvid = (msr.lo & 0xfe00) >> 9;

3
src/cpu/amd/family_10h-family_15h/tsc_freq.c
View File

@@ -15,6 +15,7 @@
#include <stdint.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/msr.h>
#include <cpu/x86/tsc.h>
unsigned long tsc_freq_mhz(void)
@@ -29,7 +30,7 @@ unsigned long tsc_freq_mhz(void)
* to MHz. See also the Family 15h BKDG
* Rev. 3.14 page 569.
*/
msr = rdmsr(0xc0010064);
msr = rdmsr(PSTATE_0_MSR);
cpufid = (msr.lo & 0x3f);
cpudid = (msr.lo & 0x1c0) >> 6;

4
src/cpu/amd/pi/00630F01/fixme.c
View File

@@ -14,8 +14,8 @@
*/
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <Porting.h>
#include <AGESA.h>
#include <amdlib.h>
@@ -79,7 +79,7 @@ void amd_initmmio(void)
*/
MsrReg = CONFIG_MMCONF_BASE_ADDRESS |
(LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader);
/* Set ROM cache onto WP to decrease post time */
MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;

18
src/cpu/amd/pi/00630F01/model_15_init.c
View File

@@ -15,8 +15,10 @@
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/smm.h>
#include <cpu/amd/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/x86/smm.h>
#include <device/device.h>
#include <device/pci.h>
#include <string.h>
@@ -25,8 +27,6 @@
#include <cpu/x86/lapic.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/amdfam15.h>
#include <arch/acpi.h>
static void model_15_init(struct device *dev)
@@ -70,12 +70,12 @@ static void model_15_init(struct device *dev)
x86_enable_cache();
/* zero the machine check error status registers */
msr = rdmsr(MCG_CAP);
msr = rdmsr(IA32_MCG_CAP);
num_banks = msr.lo & MCA_BANKS_MASK;
msr.lo = 0;
msr.hi = 0;
for (i = 0; i < num_banks; i++)
wrmsr(MC0_STATUS + (i * 4), msr);
wrmsr(IA32_MC0_STATUS + (i * 4), msr);
/* Enable the local CPU APICs */
setup_lapic();
@@ -105,14 +105,14 @@ static void model_15_init(struct device *dev)
printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx);
/* Set SMM base address for this CPU */
msr = rdmsr(MSR_SMM_BASE);
msr = rdmsr(SMM_BASE_MSR);
msr.lo = SMM_BASE - (cpu_idx * 0x400);
wrmsr(MSR_SMM_BASE, msr);
wrmsr(SMM_BASE_MSR, msr);
/* Enable the SMM memory window */
msr = rdmsr(MSR_SMM_MASK);
msr = rdmsr(SMM_MASK_MSR);
msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */
wrmsr(MSR_SMM_MASK, msr);
wrmsr(SMM_MASK_MSR, msr);
}
/* Write protect SMM space with SMMLOCK. */

5
src/cpu/amd/pi/00630F01/udelay.c
View File

@@ -21,6 +21,7 @@
*/
#include <cpu/x86/msr.h>
#include <cpu/amd/msr.h>
#include <cpu/x86/tsc.h>
#include <delay.h>
#include <stdint.h>
@@ -36,11 +37,11 @@ void udelay(uint32_t us)
tsc_start = rdtscll();
/* Get the P-state. This determines which MSR to read */
msr = rdmsr(0xc0010063);
msr = rdmsr(PS_STS_REG);
pstate_idx = msr.lo & 0x07;
/* Get FID and VID for current P-State */
msr = rdmsr(0xc0010064 + pstate_idx);
msr = rdmsr(PSTATE_0_MSR + pstate_idx);
/* Extract the FID and VID values */
fid = msr.lo & 0x3f;

4
src/cpu/amd/pi/00660F01/fixme.c
View File

@@ -14,8 +14,8 @@
*/
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <Porting.h>
#include <AGESA.h>
#include <amdlib.h>
@@ -80,7 +80,7 @@ void amd_initmmio(void)
*/
MsrReg = CONFIG_MMCONF_BASE_ADDRESS |
(LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader);
/* For serial port */
PciData = 0xFF03FFD5;

8
src/cpu/amd/pi/00660F01/model_15_init.c
View File

@@ -15,6 +15,8 @@
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
#include <device/device.h>
#include <device/pci.h>
@@ -24,8 +26,6 @@
#include <cpu/x86/lapic.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/amdfam15.h>
#include <arch/acpi.h>
#include <amdlib.h>
@@ -82,12 +82,12 @@ static void model_15_init(struct device *dev)
x86_enable_cache();
/* zero the machine check error status registers */
msr = rdmsr(MCG_CAP);
msr = rdmsr(IA32_MCG_CAP);
num_banks = msr.lo & MCA_BANKS_MASK;
msr.lo = 0;
msr.hi = 0;
for (i = 0; i < num_banks; i++)
wrmsr(MC0_STATUS + (i * 4), msr);
wrmsr(IA32_MC0_STATUS + (i * 4), msr);
/* Enable the local CPU APICs */
setup_lapic();

4
src/cpu/amd/pi/00730F01/fixme.c
View File

@@ -14,8 +14,8 @@
*/
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <Porting.h>
#include <AGESA.h>
#include <amdlib.h>
@@ -80,7 +80,7 @@ void amd_initmmio(void)
*/
MsrReg = CONFIG_MMCONF_BASE_ADDRESS |
(LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader);
LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader);
/* For serial port */
PciData = 0xFF03FFD5;

8
src/cpu/amd/pi/00730F01/model_16_init.c
View File

@@ -15,6 +15,8 @@
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
#include <device/device.h>
#include <device/pci.h>
@@ -24,8 +26,6 @@
#include <cpu/x86/lapic.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/amdfam16.h>
#include <arch/acpi.h>
static void model_16_init(struct device *dev)
@@ -67,12 +67,12 @@ static void model_16_init(struct device *dev)
x86_enable_cache();
/* zero the machine check error status registers */
msr = rdmsr(MCG_CAP);
msr = rdmsr(IA32_MCG_CAP);
num_banks = msr.lo & MCA_BANKS_MASK;
msr.lo = 0;
msr.hi = 0;
for (i = 0; i < num_banks; i++)
wrmsr(MC0_STATUS + (i * 4), msr);
wrmsr(IA32_MC0_STATUS + (i * 4), msr);
/* Enable the local CPU APICs */
setup_lapic();