cpu/amd: Use common AMD's MSR

Phase 1. Due to the size of the effort, this CL is broken into several phases. Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-12 10:54:30 +02:00
parent e64a585374
commit 400ce55566
82 changed files with 412 additions and 510 deletions
--- a/src/northbridge/amd/agesa/family12/northbridge.c
+++ b/src/northbridge/amd/agesa/family12/northbridge.c
@@ -29,6 +29,7 @@
 #include <cbmem.h>

 #include <cpu/x86/lapic.h>
+#include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>

 #include "sb_cimx.h"
@@ -306,7 +307,7 @@ static void read_resources(struct device *dev)
 	 * It is not honored by the coreboot resource allocator if it is in
 	 * the CPU_CLUSTER.
 	 */
-	mmconf_resource(dev, 0xc0010058);
+	mmconf_resource(dev, MMIO_CONF_BASE);

 	printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);
 }
--- a/src/northbridge/amd/agesa/family14/northbridge.c
+++ b/src/northbridge/amd/agesa/family14/northbridge.c
@@ -27,13 +27,11 @@
 #include <lib.h>
 #include <cpu/cpu.h>
 #include <cbmem.h>
-
 #include <cpu/x86/lapic.h>
+#include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
-
 #include <northbridge/amd/agesa/state_machine.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
-
 #include <sb_cimx.h>

 #define FX_DEVS 1
@@ -298,7 +296,7 @@ static void nb_read_resources(struct device *dev)
 	 * It is not honored by the coreboot resource allocator if it is in
 	 * the CPU_CLUSTER.
 	 */
-	mmconf_resource(dev, 0xc0010058);
+	mmconf_resource(dev, MMIO_CONF_BASE);
 }

 static void set_resource(struct device *dev, struct resource *resource,
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -29,14 +29,12 @@
 #include <cpu/cpu.h>
 #include <cbmem.h>
 #include <AGESA.h>
-
 #include <cpu/x86/lapic.h>
+#include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
-
 #include <Porting.h>
 #include <Options.h>
 #include <Topology.h>
-
 #include <northbridge/amd/agesa/state_machine.h>
 #include <northbridge/amd/agesa/agesa_helper.h>

@@ -307,7 +305,7 @@ static void nb_read_resources(struct device *dev)
 	 * It is not honored by the coreboot resource allocator if it is in
 	 * the CPU_CLUSTER.
 	 */
-	mmconf_resource(dev, 0xc0010058);
+	mmconf_resource(dev, MMIO_CONF_BASE);
 }

 static void set_resource(struct device *dev, struct resource *resource, u32 nodeid)
--- a/src/northbridge/amd/agesa/family16kb/northbridge.c
+++ b/src/northbridge/amd/agesa/family16kb/northbridge.c
@@ -27,15 +27,13 @@
 #include <lib.h>
 #include <cpu/cpu.h>
 #include <cbmem.h>
-
 #include <cpu/x86/lapic.h>
+#include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
-
 #include <Porting.h>
 #include <AGESA.h>
 #include <Options.h>
 #include <Topology.h>
-
 #include <northbridge/amd/agesa/state_machine.h>
 #include <northbridge/amd/agesa/agesa_helper.h>

@@ -306,7 +304,7 @@ static void read_resources(struct device *dev)
 	 * It is not honored by the coreboot resource allocator if it is in
 	 * the APIC_CLUSTER.
 	 */
-	mmconf_resource(dev, 0xc0010058);
+	mmconf_resource(dev, MMIO_CONF_BASE);
 }

 static void set_resource(struct device *dev, struct resource *resource, u32 nodeid)
--- a/src/northbridge/amd/amdfam10/northbridge.c
+++ b/src/northbridge/amd/amdfam10/northbridge.c
@@ -28,7 +28,6 @@
 #include <smbios.h>
 #include <cpu/cpu.h>
 #include <delay.h>
-
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/cache.h>
 #include <cpu/amd/mtrr.h>
@@ -734,7 +733,7 @@ static void amdfam10_domain_read_resources(struct device *dev)
 	pci_domain_read_resources(dev);

 	/* We have MMCONF_SUPPORT, create the resource window. */
-	mmconf_resource(dev, 0xc0010058);
+	mmconf_resource(dev, MMIO_CONF_BASE);

 	/* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */
 	ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10);
--- a/src/northbridge/amd/amdht/AsPsDefs.h
+++ b/src/northbridge/amd/amdht/AsPsDefs.h
@@ -21,19 +21,6 @@
 #define APIC_BAR 0x1b			/* APIC_BAR register */
 #define APIC_BAR_BP 0x100		/* APIC_BAR BSP bit */

-#define PS_LIM_REG 0xC0010061		/* P-state Current Limit Register */
-#define PS_MAX_VAL_SHFT 4		/* P-state Maximum Value shift position */
-
-#define PS_CTL_REG 0xC0010062		/* P-state Control Register */
-#define PS_CMD_MASK_OFF 0xfffffff8	/* P-state Control Register CMD Mask OFF */
-
-#define PS_STS_REG 0xC0010063		/* P-state Status Register */
-#define PS_STS_MASK 0x7		/* P-state Status Mask */
-
-#define PS_REG_BASE 0xC0010064		/* P-state Register base */
-#define PS_MAX_REG 0xC0010068		/* Maximum P-State Register */
-#define PS_MIN_REG 0xC0010064		/* Mimimum P-State Register */
-
 /* P-state register offset */
 #define PS_REG0 0			/* offset for P0 */
 #define PS_REG1 1			/* offset for P1 */
@@ -286,7 +273,6 @@


 #define TSC_MSR 0x10
-#define CUR_PSTATE_MSR 0xc0010063
 #define TSC_FREQ_SEL_SHIFT 24

 #define TSC_FREQ_SEL_MASK (1 << TSC_FREQ_SEL_SHIFT)
--- a/src/northbridge/amd/amdmct/amddefs.h
+++ b/src/northbridge/amd/amdmct/amddefs.h
@@ -120,42 +120,6 @@
 #define HTPHY_DIRECT_MAP		0x20000000
 #define HTPHY_DIRECT_OFFSET_MASK	0xE000FFFF

-
-/*
- * Various AMD MSRs
- */
-#define CPUID_EXT_PM		0x80000007
-#define CPUID_MODEL		1
-#define MCG_CAP			0x00000179
-	#define MCG_CTL_P	8
-	#define MCA_BANKS_MASK	0xff
-#define MC0_CTL			0x00000400
-#define MC0_STA			(MC0_CTL + 1)
-#define MC4_MISC0		0x00000413
-#define MC4_MISC1		0xC0000408
-#define MC4_MISC2		0xC0000409
-#define FS_Base			0xC0000100
-#define SYSCFG			0xC0010010
-#define HWCR			0xC0010015
-#define NB_CFG			0xC001001F
-#define FidVidStatus		0xC0010042
-#define MC1_CTL_MASK		0xC0010045
-#define MC4_CTL_MASK		0xC0010048
-#define OSVW_ID_Length		0xC0010140
-#define OSVW_Status		0xC0010141
-#define CPUIDFEATURES		0xC0011004
-#define LS_CFG			0xC0011020
-#define IC_CFG			0xC0011021
-#define DC_CFG			0xC0011022
-#define BU_CFG			0xC0011023
-#define FP_CFG			0xC0011028
-#define DE_CFG			0xC0011029
-#define BU_CFG2			0xC001102A
-#define BU_CFG3			0xC001102B
-#define EX_CFG			0xC001102C
-#define LS_CFG2			0xC001102D
-#define IBS_OP_DATA3		0xC0011037
-
 /*
 * Processor package types
 */
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -33,9 +33,9 @@
 * supported.
 */

-#include "mct_d.h"
-
 #include <string.h>
+#include <cpu/amd/msr.h>
+#include "mct_d.h"

 static u8 ReconfigureDIMMspare_D(struct MCTStatStruc *pMCTstat,
 					struct DCTStatStruc *pDCTstatA);
@@ -3686,7 +3686,7 @@ void mct_SetClToNB_D(struct MCTStatStruc *pMCTstat,
 	// FIXME: Maybe check the CPUID? - not for now.
 	// pDCTstat->LogicalCPUID;

-	msr = BU_CFG2;
+	msr = BU_CFG2_MSR;
 	_RDMSR(msr, &lo, &hi);
 	lo |= 1 << ClLinesToNbDis;
 	_WRMSR(msr, lo, hi);
@@ -3703,7 +3703,7 @@ void mct_ClrClToNB_D(struct MCTStatStruc *pMCTstat,
 	// FIXME: Maybe check the CPUID? - not for now.
 	// pDCTstat->LogicalCPUID;

-	msr = BU_CFG2;
+	msr = BU_CFG2_MSR;
 	_RDMSR(msr, &lo, &hi);
 	if (!pDCTstat->ClToNB_flag)
 		lo &= ~(1 << ClLinesToNbDis);
@@ -3721,7 +3721,7 @@ void mct_SetWbEnhWsbDis_D(struct MCTStatStruc *pMCTstat,
 	// FIXME: Maybe check the CPUID? - not for now.
 	// pDCTstat->LogicalCPUID;

-	msr = BU_CFG;
+	msr = BU_CFG_MSR;
 	_RDMSR(msr, &lo, &hi);
 	hi |= (1 << WbEnhWsbDis_D);
 	_WRMSR(msr, lo, hi);
@@ -3737,7 +3737,7 @@ void mct_ClrWbEnhWsbDis_D(struct MCTStatStruc *pMCTstat,
 	// FIXME: Maybe check the CPUID? - not for now.
 	// pDCTstat->LogicalCPUID;

-	msr = BU_CFG;
+	msr = BU_CFG_MSR;
 	_RDMSR(msr, &lo, &hi);
 	hi &= ~(1 << WbEnhWsbDis_D);
 	_WRMSR(msr, lo, hi);
@@ -3845,7 +3845,7 @@ static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat,
 		return;
 	}

-	addr = HWCR;
+	addr = HWCR_MSR;
 	_RDMSR(addr, &lo, &hi);
 	if (lo & (1<<17)) {		/* save the old value */
 		wrap32dis = 1;
@@ -3877,7 +3877,7 @@ static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat,
 		}
 	}
 	if (!wrap32dis) {
-		addr = HWCR;
+		addr = HWCR_MSR;
 		_RDMSR(addr, &lo, &hi);
 		lo &= ~(1<<17);		/* restore HWCR.wrap32dis */
 		_WRMSR(addr, lo, hi);
--- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
@@ -13,9 +13,10 @@
 * GNU General Public License for more details.
 */

-#include "mct_d.h"
 #include <cpu/x86/cr.h>
+#include <cpu/amd/msr.h>
 #include <cpu/amd/mtrr.h>
+#include "mct_d.h"

 static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat,
 				struct DCTStatStruc *pDCTstat, u16 like,
@@ -286,7 +287,7 @@ static void TrainDQSRdWrPos_D(struct MCTStatStruc *pMCTstat,
 	cr4 |= (1<<9);		/* OSFXSR enable SSE2 */
 	write_cr4(cr4);

-	addr = HWCR;
+	addr = HWCR_MSR;
 	_RDMSR(addr, &lo, &hi);
 	if (lo & (1<<17)) {
 		_Wrap32Dis = 1;
@@ -368,7 +369,7 @@ static void TrainDQSRdWrPos_D(struct MCTStatStruc *pMCTstat,
 		mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC);
 	}
 	if (!_Wrap32Dis) {
-		addr = HWCR;
+		addr = HWCR_MSR;
 		_RDMSR(addr, &lo, &hi);
 		lo &= ~(1<<17);		/* restore HWCR.wrap32dis */
 		_WRMSR(addr, lo, hi);
--- a/src/northbridge/amd/amdmct/mct/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct/mctsrc.c
@@ -14,8 +14,9 @@
 * GNU General Public License for more details.
 */

-#include "mct_d.h"
 #include <cpu/x86/cr.h>
+#include <cpu/amd/msr.h>
+#include "mct_d.h"

 /******************************************************************************
 Description: Receiver En and DQS Timing Training feature for DDR 2 MCT
@@ -170,7 +171,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat,
 	write_cr4(cr4);
 	print_t("TrainRcvrEn: 2\n");

-	msr = HWCR;
+	msr = HWCR_MSR;
 	_RDMSR(msr, &lo, &hi);
 	//FIXME: Why use SSEDIS
 	if (lo & (1 << 17)) {	/* save the old value */
@@ -443,7 +444,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat,
 	}

 	if (!_Wrap32Dis) {
-		msr = HWCR;
+		msr = HWCR_MSR;
 		_RDMSR(msr, &lo, &hi);
 		lo &= ~(1<<17);		/* restore HWCR.wrap32dis */
 		_WRMSR(msr, lo, hi);
--- a/src/northbridge/amd/amdmct/mct/mcttmrl.c
+++ b/src/northbridge/amd/amdmct/mct/mcttmrl.c
@@ -13,8 +13,9 @@
 * GNU General Public License for more details.
 */

-#include "mct_d.h"
 #include <cpu/x86/cr.h>
+#include <cpu/amd/msr.h>
+#include "mct_d.h"

 /*
 * Description: Max Read Latency Training feature for DDR 2 MCT
@@ -132,7 +133,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat,
 	cr4 |= (1<<9);			/* OSFXSR enable SSE2 */
 	write_cr4(cr4);

-	addr = HWCR;
+	addr = HWCR_MSR;
 	_RDMSR(addr, &lo, &hi);
 	if (lo & (1<<17)) {		/* save the old value */
 		_Wrap32Dis = 1;
@@ -182,7 +183,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat,
 	}

 	if (!_Wrap32Dis) {
-		addr = HWCR;
+		addr = HWCR_MSR;
 		_RDMSR(addr, &lo, &hi);
 		lo &= ~(1<<17);	/* restore HWCR.wrap32dis */
 		_WRMSR(addr, lo, hi);
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -32,18 +32,19 @@
 * supported.
 */

-#include "mct_d_gcc.h"
-#include "mct_d.h"
 #include <console/console.h>
 #include <northbridge/amd/amdfam10/debug.h>
 #include <northbridge/amd/amdfam10/raminit.h>
 #include <northbridge/amd/amdfam10/amdfam10.h>
 #include <reset.h>
 #include <cpu/x86/msr.h>
+#include <cpu/amd/msr.h>
 #include <arch/acpi.h>
 #include <string.h>
 #include <device/dram/ddr3.h>
 #include "s3utils.h"
+#include "mct_d_gcc.h"
+#include "mct_d.h"

 static u8 ReconfigureDIMMspare_D(struct MCTStatStruc *pMCTstat,
 					struct DCTStatStruc *pDCTstatA);
@@ -7770,7 +7771,7 @@ void mct_SetClToNB_D(struct MCTStatStruc *pMCTstat,
 	/* FIXME: Maybe check the CPUID? - not for now. */
 	/* pDCTstat->LogicalCPUID; */

-	msr = BU_CFG2;
+	msr = BU_CFG2_MSR;
 	_RDMSR(msr, &lo, &hi);
 	lo |= 1 << ClLinesToNbDis;
 	_WRMSR(msr, lo, hi);
@@ -7786,7 +7787,7 @@ void mct_ClrClToNB_D(struct MCTStatStruc *pMCTstat,
 	/* FIXME: Maybe check the CPUID? - not for now. */
 	/* pDCTstat->LogicalCPUID; */

-	msr = BU_CFG2;
+	msr = BU_CFG2_MSR;
 	_RDMSR(msr, &lo, &hi);
 	if (!pDCTstat->ClToNB_flag)
 		lo &= ~(1<<ClLinesToNbDis);
@@ -7803,7 +7804,7 @@ void mct_SetWbEnhWsbDis_D(struct MCTStatStruc *pMCTstat,
 	/* FIXME: Maybe check the CPUID? - not for now. */
 	/* pDCTstat->LogicalCPUID; */

-	msr = BU_CFG;
+	msr = BU_CFG_MSR;
 	_RDMSR(msr, &lo, &hi);
 	hi |= (1 << WbEnhWsbDis_D);
 	_WRMSR(msr, lo, hi);
@@ -7818,7 +7819,7 @@ void mct_ClrWbEnhWsbDis_D(struct MCTStatStruc *pMCTstat,
 	/* FIXME: Maybe check the CPUID? - not for now. */
 	/* pDCTstat->LogicalCPUID; */

-	msr = BU_CFG;
+	msr = BU_CFG_MSR;
 	_RDMSR(msr, &lo, &hi);
 	hi &= ~(1 << WbEnhWsbDis_D);
 	_WRMSR(msr, lo, hi);
@@ -8048,7 +8049,7 @@ static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat,
 		return;
 	}

-	addr = HWCR;
+	addr = HWCR_MSR;
 	_RDMSR(addr, &lo, &hi);
 	if (lo & (1<<17)) {		/* save the old value */
 		wrap32dis = 1;
@@ -8079,7 +8080,7 @@ static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat,
 	}

 	if (!wrap32dis) {
-		addr = HWCR;
+		addr = HWCR_MSR;
 		_RDMSR(addr, &lo, &hi);
 		lo &= ~(1<<17);		/* restore HWCR.wrap32dis */
 		_WRMSR(addr, lo, hi);
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
@@ -17,9 +17,10 @@
 #include <inttypes.h>
 #include <console/console.h>
 #include <string.h>
+#include <cpu/amd/msr.h>
+#include <cpu/amd/mtrr.h>
 #include "mct_d.h"
 #include "mct_d_gcc.h"
-#include <cpu/amd/mtrr.h>

 static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat,
 				struct DCTStatStruc *pDCTstat, u16 like,
@@ -431,7 +432,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat,
 	cr4 |= (1<<9);		/* OSFXSR enable SSE2 */
 	write_cr4(cr4);

-	addr = HWCR;
+	addr = HWCR_MSR;
 	_RDMSR(addr, &lo, &hi);
 	if (lo & (1<<17)) {
 		_Wrap32Dis = 1;
@@ -830,7 +831,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat,
 		mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC);
 	}
 	if (!_Wrap32Dis) {
-		addr = HWCR;
+		addr = HWCR_MSR;
 		_RDMSR(addr, &lo, &hi);
 		lo &= ~(1<<17);		/* restore HWCR.wrap32dis */
 		_WRMSR(addr, lo, hi);
@@ -1648,7 +1649,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat,
 	cr4 |= (1<<9);		/* OSFXSR enable SSE2 */
 	write_cr4(cr4);

-	addr = HWCR;
+	addr = HWCR_MSR;
 	_RDMSR(addr, &lo, &hi);
 	if (lo & (1<<17)) {
 		_Wrap32Dis = 1;
@@ -1861,7 +1862,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat,
 		mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC);
 	}
 	if (!_Wrap32Dis) {
-		addr = HWCR;
+		addr = HWCR_MSR;
 		_RDMSR(addr, &lo, &hi);
 		lo &= ~(1<<17);		/* restore HWCR.wrap32dis */
 		_WRMSR(addr, lo, hi);
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
@@ -22,9 +22,10 @@
 #include <inttypes.h>
 #include <console/console.h>
 #include <string.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/msr.h>
 #include "mct_d.h"
 #include "mct_d_gcc.h"
-#include <cpu/x86/msr.h>

 static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat,
 				struct DCTStatStruc *pDCTstat, u8 Pass);
@@ -661,14 +662,15 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat,
 	cr4 |= (1 << 9);	/* OSFXSR enable SSE2 */
 	write_cr4(cr4);

-	msr = rdmsr(HWCR);
+	msr = rdmsr(HWCR_MSR);
 	/* FIXME: Why use SSEDIS */
 	if (msr.lo & (1 << 17)) {	/* save the old value */
 		_Wrap32Dis = 1;
 	}
 	msr.lo |= (1 << 17);	/* HWCR.wrap32dis */
 	msr.lo &= ~(1 << 15);	/* SSEDIS */
-	wrmsr(HWCR, msr);	/* Setting wrap32dis allows 64-bit memory references in real mode */
+	wrmsr(HWCR_MSR, msr);	/* Setting wrap32dis allows 64-bit memory
+				   references in real mode */

 	_DisableDramECC = mct_DisableDimmEccEn_D(pMCTstat, pDCTstat);

@@ -996,9 +998,9 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat,
 	}

 	if (!_Wrap32Dis) {
-		msr = rdmsr(HWCR);
+		msr = rdmsr(HWCR_MSR);
 		msr.lo &= ~(1<<17);	/* restore HWCR.wrap32dis */
-		wrmsr(HWCR, msr);
+		wrmsr(HWCR_MSR, msr);
 	}
 	if (!_SSE2) {
 		cr4 = read_cr4();
@@ -1254,7 +1256,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
 	cr4 |= (1 << 9);	/* OSFXSR enable SSE2 */
 	write_cr4(cr4);

-	msr = HWCR;
+	msr = HWCR_MSR;
 	_RDMSR(msr, &lo, &hi);
 	/* FIXME: Why use SSEDIS */
 	if (lo & (1 << 17)) {	/* save the old value */
@@ -1498,7 +1500,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
 	}

 	if (!_Wrap32Dis) {
-		msr = HWCR;
+		msr = HWCR_MSR;
 		_RDMSR(msr, &lo, &hi);
 		lo &= ~(1<<17);		/* restore HWCR.wrap32dis */
 		_WRMSR(msr, lo, hi);
@@ -1613,7 +1615,7 @@ void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat,
 	cr4 |= (1 << 9);	/* OSFXSR enable SSE2 */
 	write_cr4(cr4);

-	msr = HWCR;
+	msr = HWCR_MSR;
 	_RDMSR(msr, &lo, &hi);
 	/* FIXME: Why use SSEDIS */
 	if (lo & (1 << 17)) {	/* save the old value */
@@ -1718,7 +1720,7 @@ void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat,
 	}

 	if (!_Wrap32Dis) {
-		msr = HWCR;
+		msr = HWCR_MSR;
 		_RDMSR(msr, &lo, &hi);
 		lo &= ~(1<<17);		/* restore HWCR.wrap32dis */
 		_WRMSR(msr, lo, hi);
--- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c
@@ -21,6 +21,7 @@
 #include <inttypes.h>
 #include <console/console.h>
 #include <string.h>
+#include <cpu/amd/msr.h>
 #include "mct_d.h"
 #include "mct_d_gcc.h"

@@ -131,7 +132,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat,
 	cr4 |= (1<<9);			/* OSFXSR enable SSE2 */
 	write_cr4(cr4);

-	addr = HWCR;
+	addr = HWCR_MSR;
 	_RDMSR(addr, &lo, &hi);
 	if (lo & (1<<17)) {		/* save the old value */
 		_Wrap32Dis = 1;
@@ -181,7 +182,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat,
 	}

 	if (!_Wrap32Dis) {
-		addr = HWCR;
+		addr = HWCR_MSR;
 		_RDMSR(addr, &lo, &hi);
 		lo &= ~(1<<17);	/* restore HWCR.wrap32dis */
 		_WRMSR(addr, lo, hi);
--- a/src/northbridge/amd/pi/00630F01/northbridge.c
+++ b/src/northbridge/amd/pi/00630F01/northbridge.c
@@ -26,23 +26,23 @@
 #include <lib.h>
 #include <cpu/cpu.h>
 #include <cbmem.h>
-
 #include <Porting.h>
 #include <AGESA.h>
 #include <FieldAccessors.h>
 #include <Topology.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/amd/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <assert.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 #if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
 #include <northbridge/amd/pi/agesawrapper.h>
 #include <northbridge/amd/pi/agesawrapper_call.h>
 #endif
-#include "northbridge.h"

-#include <cpu/x86/lapic.h>
-#include <cpu/amd/mtrr.h>
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
-#include <assert.h>
+#include "northbridge.h"

 #define MAX_NODE_NUMS MAX_NODES

@@ -315,7 +315,7 @@ static void read_resources(struct device *dev)
 	 * It is not honored by the coreboot resource allocator if it is in
 	 * the CPU_CLUSTER.
 	 */
-	mmconf_resource(dev, 0xc0010058);
+	mmconf_resource(dev, MMIO_CONF_BASE);
 }

 static void set_resource(struct device *dev, struct resource *resource, u32 nodeid)
--- a/src/northbridge/amd/pi/00660F01/northbridge.c
+++ b/src/northbridge/amd/pi/00660F01/northbridge.c
@@ -26,11 +26,15 @@
 #include <lib.h>
 #include <cpu/cpu.h>
 #include <cbmem.h>
-
 #include <Porting.h>
 #include <AGESA.h>
 #include <FieldAccessors.h>
 #include <Topology.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/amd/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 #if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
 #include <northbridge/amd/pi/agesawrapper.h>
@@ -38,11 +42,6 @@
 #endif
 #include "northbridge.h"

-#include <cpu/x86/lapic.h>
-#include <cpu/amd/mtrr.h>
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
-
 #define MAX_NODE_NUMS MAX_NODES

 #if IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)
@@ -302,7 +301,7 @@ static void read_resources(struct device *dev)
 	 * It is not honored by the coreboot resource allocator if it is in
 	 * the CPU_CLUSTER.
 	 */
-	mmconf_resource(dev, 0xc0010058);
+	mmconf_resource(dev, MMIO_CONF_BASE);
 }

 static void set_resource(struct device *dev, struct resource *resource, u32 nodeid)
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -28,11 +28,15 @@
 #include <lib.h>
 #include <cpu/cpu.h>
 #include <cbmem.h>
-
 #include <Porting.h>
 #include <AGESA.h>
 #include <FieldAccessors.h>
 #include <Topology.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/amd/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
 #include <northbridge/amd/agesa/agesa_helper.h>
 #if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER)
 #include <northbridge/amd/pi/agesawrapper.h>
@@ -40,11 +44,6 @@
 #endif
 #include "northbridge.h"

-#include <cpu/x86/lapic.h>
-#include <cpu/amd/mtrr.h>
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
-
 #define MAX_NODE_NUMS MAX_NODES

 typedef struct dram_base_mask {
@@ -312,7 +311,7 @@ static void read_resources(struct device *dev)
 	 * It is not honored by the coreboot resource allocator if it is in
 	 * the CPU_CLUSTER.
 	 */
-	mmconf_resource(dev, 0xc0010058);
+	mmconf_resource(dev, MMIO_CONF_BASE);
 }

 static void set_resource(struct device *dev, struct resource *resource, u32 nodeid)