mb/google/dedede/var/beadrix: Add a Proximity Sensor SX9324 for SAR

To meet LTE's RF Specific Absorption Rate (SAR) certification, we add a
Semtech Smart Proximity Sensor (P-Sensor) SX9324. P-Sensor connects
EC of I2C 5 bus and GPIO D22, D23, as well  as, SoC of GPIO E11, refer
to mainboard schematic.

BUG=b:213549229
BRANCH=dedede
TEST=emerge-dedede coreboot

Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: If172d13aa62503547227adf91f049ea50b948888
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63652
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/dedede/variants/beadrix/gpio.c

@@ -21,6 +21,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_C19, NONE),
 	/* C22 : UART2_RTS_N ==> NC */
 	PAD_NC(GPP_C22, NONE),
+	/* C23 : UART2_CTS_N ==> NC */
+	PAD_NC(GPP_C23, NONE),
 
 	/* D0  : WWAN_HOST_WAKE ==> WWAN_WDISABLE_L */
 	PAD_CFG_GPO(GPP_D0, 1, DEEP),
@@ -38,6 +40,10 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_D20, NONE),
 	/* D21 : WWAN_WLAN_COEX3 ==> TP */
 	PAD_NC(GPP_D21, NONE),
+	/* D22 : AP_I2C_SUB_SDA*/
+	PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
+	/* D23 : AP_I2C_SUB_SCL */
+	PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
 
 	/* E1  : EMR_RESET_L ==> NC */
 	PAD_NC(GPP_E1, NONE),
@@ -47,6 +53,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_E5, NONE),
 	/* E10 : GPP_E10/SML_DATA0 ==> NC */
 	PAD_NC(GPP_E10, NONE),
+	/* E11 : AP_I2C_SUB_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_E11, NONE, PLTRST, LEVEL, NONE),
 
 	/* G0  : SD_CMD ==> NC */
 	PAD_NC(GPP_G0, NONE),

src/mainboard/google/dedede/variants/beadrix/overridetree.cb

@@ -14,10 +14,11 @@ chip soc/intel/jasperlake
 	#|                   | for TPM communication     |
 	#|                   | before memory is up       |
 	#| I2C0              | Trackpad                  |
-	#| I2C1              | Digitizer                 |
+	#| I2C1              |                           |
 	#| I2C2              | Touchscreen               |
-	#| I2C3              | Camera                    |
+	#| I2C3              |                           |
 	#| I2C4              | Audio                     |
+	#| I2C5              | P-sensor                  |
 	#+-------------------+---------------------------+
 	register "common_soc_config" = "{
 		.gspi[0] = {
@@ -39,6 +40,18 @@ chip soc/intel/jasperlake
 		.i2c[4] = {
 			.speed = I2C_SPEED_FAST,
 		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+		},
+	}"
+
+	register "SerialIoI2cMode" = "{
+		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C1]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
 	}"
 
 	device domain 0 on
@@ -131,6 +144,60 @@ chip soc/intel/jasperlake
 				device i2c 1a on end
 			end
 		end # I2C 4
+		device pci 19.1 on
+			chip drivers/i2c/sx9324
+				register "desc" = ""SAR Proximity Sensor""
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)"
+				register "uid" = "0"
+				register "reg_gnrl_ctrl0" = "0x0a"
+				register "reg_gnrl_ctrl1" = "0x22"
+				register "reg_afe_ctrl0" = "0x20"
+				register "reg_afe_ctrl3" = "0x01"
+				register "reg_afe_ctrl4" = "0x47"
+				register "reg_afe_ctrl6" = "0x00"
+				register "reg_afe_ctrl7" = "0x47"
+				register "reg_afe_ctrl8" = "0x12"
+				register "reg_afe_ctrl9" = "0x0f"
+				register "reg_afe_ph0" = "0x37"
+				register "reg_afe_ph1" = "0x29"
+				register "reg_afe_ph2" = "0x1f"
+				register "reg_afe_ph3" = "0x3d"
+				register "reg_prox_ctrl0" = "0x0b"
+				register "reg_prox_ctrl1" = "0x0b"
+				register "reg_prox_ctrl2" = "0x20"
+				register "reg_prox_ctrl3" = "0x20"
+				register "reg_prox_ctrl4" = "0x0c"
+				register "reg_prox_ctrl5" = "0x00"
+				register "reg_prox_ctrl6" = "0x2d"
+				register "reg_prox_ctrl7" = "0xc0"
+				register "reg_adv_ctrl0" = "0x00"
+				register "reg_adv_ctrl1" = "0x00"
+				register "reg_adv_ctrl2" = "0x00"
+				register "reg_adv_ctrl3" = "0x00"
+				register "reg_adv_ctrl4" = "0x00"
+				register "reg_adv_ctrl5" = "0x05"
+				register "reg_adv_ctrl6" = "0x00"
+				register "reg_adv_ctrl7" = "0x00"
+				register "reg_adv_ctrl8" = "0x00"
+				register "reg_adv_ctrl9" = "0x00"
+				register "reg_adv_ctrl10" = "0x00"
+				register "reg_adv_ctrl11" = "0x00"
+				register "reg_adv_ctrl12" = "0x00"
+				register "reg_adv_ctrl13" = "0x00"
+				register "reg_adv_ctrl14" = "0x80"
+				register "reg_adv_ctrl15" = "0x0c"
+				register "reg_adv_ctrl16" = "0x04"
+				register "reg_adv_ctrl17" = "0x70"
+				register "reg_adv_ctrl18" = "0x40"
+				register "reg_adv_ctrl19" = "0x00"
+				register "reg_adv_ctrl20" = "0x00"
+				register "reg_irq_msk" = "0x6f"
+				register "reg_irq_cfg0" = "0x00"
+				register "reg_irq_cfg1" = "0x80"
+				register "reg_irq_cfg2" = "0x00"
+				device i2c 28 on end
+			end
+		end # I2C 5
 		device pci 1c.6 off end # PCI Express Root Port 7 / SATA_0. Baseboard/devicetree.cb is off
 		device pci 1c.7 off end # PCI Express Root Port 8 / SATA_1
 		device pci 1f.3 on