google/glados: add new board
Change-Id: I0c196ff84484717c59c59d11bb7230b5920e0654 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10997 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Patrick Georgi
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Patrick Georgi
Patrick Georgi
parent
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commit
406313d46d
315
src/mainboard/google/glados/gpio.h
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315
src/mainboard/google/glados/gpio.h
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Google Inc.
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* Copyright (C) 2015 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#ifndef MAINBOARD_GPIO_H
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#define MAINBOARD_GPIO_H
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#include <soc/gpio.h>
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const GPIO_INIT_CONFIG mainboard_gpio_table[] = {
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/* RCIN# */
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{GPIO_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* LAD0 */
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{GPIO_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* LAD1 */
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{GPIO_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut,
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GpioOutDefault, GpioIntDis, GpioTermNone}},
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/* LAD2 */
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{GPIO_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* LAD3 */
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{GPIO_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* LFRAME# */
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{GPIO_LP_GPP_A5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* SERIRQ */
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{GPIO_LP_GPP_A6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* CLKRUN# */
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{GPIO_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* CLKOUT_LPC0 */
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{GPIO_LP_GPP_A9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* SUSWARN# tied to SUSACK# */
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{GPIO_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* SUS_STAT# TP27 */
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{GPIO_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* SUSACK# tied to SUSWARN# */
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{GPIO_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* SD_1P8_SEL */
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{GPIO_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* SD_PWR_EN# */
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{GPIO_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* TRACKPAD_INT_L */
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{GPIO_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
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GpioOutDefault, (GpioIntApic | GpioIntLevel), GpioResetDeep,
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GpioTermNone}},
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/* SRCCLKREQ1# / WLAN_PCIE_CLKREQ_L */
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{GPIO_LP_GPP_B6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
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GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
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/* SRCCLKREQ2# / KEPLER_PCIE_CLKREQ_L */
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{GPIO_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
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GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
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/* EXT_PWR_GATE# */
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{GPIO_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
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GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
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/* SLP_S0# */
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{GPIO_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
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GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* PLTRST# */
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{GPIO_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
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GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* WLAN_PCIE_WAKE_L */
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{GPIO_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
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GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}},
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/* SMBCLK (XDP) */
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{GPIO_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* SMBDATA (XDP) */
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{GPIO_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* EC_IN_RW */
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{GPIO_LP_GPP_C6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
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GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
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/* EN_PP3300_KEPLER */
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{GPIO_LP_GPP_C11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,
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GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},
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/* PCH_MEM_CONFIG[0] */
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{GPIO_LP_GPP_C12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* PCH_MEM_CONFIG[1] */
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{GPIO_LP_GPP_C13, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* PCH_MEM_CONFIG[2] */
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{GPIO_LP_GPP_C14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* PCH_MEM_CONFIG[3] */
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{GPIO_LP_GPP_C15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* I2C0_SDA */
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{GPIO_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* I2C0_SCL */
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{GPIO_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* I2C1 SDA */
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{GPIO_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* I2C1 SDA */
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{GPIO_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* UART2_RXD */
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{GPIO_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* UART2_TXD */
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{GPIO_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* EN_PP3300_DX_TOUCHSCREEN */
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{GPIO_LP_GPP_C22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,
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GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermWpd20K}},
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/* PCH_WP */
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{GPIO_LP_GPP_C23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
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GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermWpu20K}},
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/* EN_PP3300_DX_EMMC */
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{GPIO_LP_GPP_D5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,
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GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* EN_PP1800_DX_EMMC */
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{GPIO_LP_GPP_D6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,
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GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* USBA_1_ILIM_SEL_L */
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{GPIO_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,
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GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* USBA_2_ILIM_SEL_L */
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{GPIO_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,
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GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* EN_PP3300_DX_CAM */
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{GPIO_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,
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GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* DMIC_CLK1 */
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{GPIO_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* DMIC_DATA1 */
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{GPIO_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* DMIC_CLK0 */
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{GPIO_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* DMIC_DATA0 */
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{GPIO_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* I2S_MCLK */
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{GPIO_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* TPM_PIRQ_L */
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{GPIO_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
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GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}},
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/* TOUCHSCREEN_INT_L */
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{GPIO_LP_GPP_E7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
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GpioOutDefault, (GpioIntApic | GpioIntLevel), GpioResetDeep,
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GpioTermNone}},
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/* USB2_OC0# */
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{GPIO_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
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GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
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/* USB2_OC1# */
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{GPIO_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
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GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
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/* USB2_OC2# */
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{GPIO_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
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GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
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/* USB2_OC3# */
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{GPIO_LP_GPP_E12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
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GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
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/* DDPB_HPD0 */
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{GPIO_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
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GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
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/* DDPC_HPD1 */
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{GPIO_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
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GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
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/* EC_SMI_L */
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{GPIO_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
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GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}},
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/* EC_SCI_L */
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{GPIO_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
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GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}},
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/* EDP_HPD */
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{GPIO_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
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GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
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/*
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* The next 4 pads are for bit banging the amplifiers. They are connected
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* together with i2s0 signals. For default behavior of i2s make these
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* gpio inupts.
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*/
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/* I2S2_SCLK */
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{GPIO_LP_GPP_F0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* I2S2_SFRM */
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{GPIO_LP_GPP_F1, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* I2S2_TXD */
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{GPIO_LP_GPP_F2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* I2S2_RXD */
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{GPIO_LP_GPP_F3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* I2C4_SDA */
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{GPIO_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* I2C4_SCL */
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{GPIO_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* MIC_INT_L */
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{GPIO_LP_GPP_F10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv,
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GpioOutDefault, (GpioIntApic | GpioIntEdge), GpioResetDeep,
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GpioTermNone}},
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/* EMMC_CMD */
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{GPIO_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* EMMC_DATA0 */
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{GPIO_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* EMMC_DATA1 */
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{GPIO_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* EMMC_DATA2 */
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{GPIO_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* EMMC_DATA3 */
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{GPIO_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* EMMC_DATA4 */
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{GPIO_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* EMMC_DATA5 */
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{GPIO_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* EMMC_DATA6 */
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{GPIO_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* EMMC_DATA7 */
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{GPIO_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* EMMC_RCLK */
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{GPIO_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* EMMC_CLK */
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{GPIO_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* EMMC_CMD */
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{GPIO_LP_GPP_F23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
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GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
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/* SD_CMD */
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{GPIO_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
|
||||
/* SD_DATA0 */
|
||||
{GPIO_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
|
||||
/* SD_DATA1 */
|
||||
{GPIO_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
|
||||
/* SD_DATA2 */
|
||||
{GPIO_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
|
||||
/* SD_DATA3 */
|
||||
{GPIO_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
|
||||
/* SD_CD# */
|
||||
{GPIO_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
|
||||
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
|
||||
/* SD_CLK# */
|
||||
{GPIO_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
|
||||
GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}},
|
||||
/* SD_WP# */
|
||||
{GPIO_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
|
||||
GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}},
|
||||
/* ACPRESENT# */
|
||||
{GPIO_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
|
||||
GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
|
||||
/* EC_PCH_WAKE_L */
|
||||
{GPIO_LP_GPD2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
|
||||
GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}},
|
||||
/* PWRBTN# */
|
||||
{GPIO_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
|
||||
GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
|
||||
/* SLP_S3# */
|
||||
{GPIO_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
|
||||
GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},
|
||||
/* SLP_S4# */
|
||||
{GPIO_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
|
||||
GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},
|
||||
/* SUSCLK */
|
||||
{GPIO_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
|
||||
GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone}},
|
||||
/* SLP_S5# */
|
||||
{GPIO_LP_GPD10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
|
||||
GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone}},
|
||||
{END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone,
|
||||
GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},
|
||||
};
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user