intel/car/cache_as_ram_ht.inc: Prepare for dynamic CONFIG_RAMTOP
Change-Id: Idb0f621553e76e771a5d6f2d492675ccd989d947 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15228 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
committed by
Martin Roth
parent
07921540dd
commit
408d392823
@ -339,8 +339,12 @@ no_msr_11e:
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post_code(0x2f)
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/* Call romstage.c main function. */
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call main
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addl $4, %esp
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call romstage_main
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/* Save return value from romstage_main. It contains the stack to use
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* after cache-as-ram is torn down. It also contains the information
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* for setting up MTRRs. */
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movl %eax, %ebx
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post_code(0x30)
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@ -425,7 +429,8 @@ __main:
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post_code(POST_PREPARE_RAMSTAGE)
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cld /* Clear direction flag. */
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movl $CONFIG_RAMTOP, %esp
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/* Setup stack as indicated by return value from romstage_main(). */
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movl %ebx, %esp
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movl %esp, %ebp
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call copy_and_run
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@ -2,4 +2,5 @@ ramstage-y += model_106cx_init.c
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subdirs-y += ../../x86/name
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cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
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romstage-y += ../car/romstage.c
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cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin
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@ -15,3 +15,4 @@ subdirs-y += ../hyperthreading
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subdirs-y += ../speedstep
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cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
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romstage-y += ../car/romstage.c
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@ -10,3 +10,4 @@ subdirs-y += ../microcode
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subdirs-y += ../hyperthreading
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cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
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romstage-y += ../car/romstage.c
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