intel/car/cache_as_ram_ht.inc: Prepare for dynamic CONFIG_RAMTOP

Change-Id: Idb0f621553e76e771a5d6f2d492675ccd989d947
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15228
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki
2016-06-17 10:43:48 +03:00
committed by Martin Roth
parent 07921540dd
commit 408d392823
9 changed files with 21 additions and 13 deletions

View File

@ -339,8 +339,12 @@ no_msr_11e:
post_code(0x2f)
/* Call romstage.c main function. */
call main
addl $4, %esp
call romstage_main
/* Save return value from romstage_main. It contains the stack to use
* after cache-as-ram is torn down. It also contains the information
* for setting up MTRRs. */
movl %eax, %ebx
post_code(0x30)
@ -425,7 +429,8 @@ __main:
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */
movl $CONFIG_RAMTOP, %esp
/* Setup stack as indicated by return value from romstage_main(). */
movl %ebx, %esp
movl %esp, %ebp
call copy_and_run

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@ -2,4 +2,5 @@ ramstage-y += model_106cx_init.c
subdirs-y += ../../x86/name
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
romstage-y += ../car/romstage.c
cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin

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@ -15,3 +15,4 @@ subdirs-y += ../hyperthreading
subdirs-y += ../speedstep
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
romstage-y += ../car/romstage.c

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@ -10,3 +10,4 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
romstage-y += ../car/romstage.c