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soc/intel/cannonlake: Add support for D0 stepping

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D0 stepping with CPUID 0x60663 need to be added in coreboot.

TEST=Boot up with D0 stepping processor

Change-Id: I3b0f2616843367d2bfbee1b5bf75772b9e83e931
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Lijian Zhao 2017-12-01 12:53:43 -08:00 committed by Aaron Durbin
parent 5598db254f
commit 408d76f867
2 changed files with 2 additions and 0 deletions
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1
src/soc/intel/cannonlake/include/soc/cpu.h
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@ -25,6 +25,7 @@
#define CPUID_CANNONLAKE_A0 0x60660
#define CPUID_CANNONLAKE_B0 0x60661
#define CPUID_CANNONLAKE_C0 0x60662
#define CPUID_CANNONLAKE_D0 0x60663
/* Latency times in units of 1024ns. */
#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x4e

1
src/soc/intel/common/block/include/intelblocks/mp_init.h
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@ -31,6 +31,7 @@
#define CPUID_CANNONLAKE_A0 0x60660
#define CPUID_CANNONLAKE_B0 0x60661
#define CPUID_CANNONLAKE_C0 0x60662
#define CPUID_CANNONLAKE_D0 0x60663
#define CPUID_APOLLOLAKE_A0 0x506c8
#define CPUID_APOLLOLAKE_B0 0x506c9
#define CPUID_APOLLOLAKE_E0 0x506ca