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mb/google/guybrush: Reorganize bootblock_mainboard_early_init()

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This now skips all of the pieces done by PSP_verstage.

BUG=None
TEST=Boot Guybrush with & without PSP_verstage

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I5a6b8e2284e232c30c9f36ea7c6ab044e2644f7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Martin Roth
2021-08-31 17:56:38 -06:00
committed by Felix Held
parent 049e994fa8
commit 40d2c04937
1 changed files with 15 additions and 15 deletions
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20
src/mainboard/google/guybrush/bootblock.c
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@@ -31,7 +31,16 @@ void bootblock_mainboard_early_init(void)
size_t base_num_gpios, override_num_gpios; size_t base_num_gpios, override_num_gpios;
const struct soc_amd_gpio *base_gpios, *override_gpios; const struct soc_amd_gpio *base_gpios, *override_gpios;
if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { dword = pci_read_config32(SOC_LPC_DEV, 0x78);
dword &= 0xFFFFF9F3;
dword |= 0x200;
pci_write_config32(SOC_LPC_DEV, 0x78, dword);
pci_write_config32(SOC_LPC_DEV, 0x44, 0);
pci_write_config32(SOC_LPC_DEV, 0x48, 0);
if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK))
return;
base_gpios = variant_early_gpio_table(&base_num_gpios); base_gpios = variant_early_gpio_table(&base_num_gpios);
override_gpios = variant_early_override_gpio_table(&override_num_gpios); override_gpios = variant_early_override_gpio_table(&override_num_gpios);
@@ -42,17 +51,8 @@ void bootblock_mainboard_early_init(void)
* the Fibocom 350 PCIe init * the Fibocom 350 PCIe init
*/ */
stopwatch_init_usecs_expire(&pcie_init_timeout_sw, FC350_PCIE_INIT_DELAY_US); stopwatch_init_usecs_expire(&pcie_init_timeout_sw, FC350_PCIE_INIT_DELAY_US);
}
printk(BIOS_DEBUG, "Bootblock configure eSPI\n"); printk(BIOS_DEBUG, "Bootblock configure eSPI\n");
dword = pci_read_config32(SOC_LPC_DEV, 0x78);
dword &= 0xFFFFF9F3;
dword |= 0x200;
pci_write_config32(SOC_LPC_DEV, 0x78, dword);
pci_write_config32(SOC_LPC_DEV, 0x44, 0);
pci_write_config32(SOC_LPC_DEV, 0x48, 0);
dword = pm_read32(0x90); dword = pm_read32(0x90);
dword |= 1 << 16; dword |= 1 << 16;
pm_write32(0x90, dword); pm_write32(0x90, dword);