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mb/google/beltino: Factor out common MRC settings

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There's no need to redefine common settings.

Change-Id: I62f5014cf1fea093aee17023b48fd4d404279410
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
This commit is contained in:
Angel Pons
2020-07-03 18:34:22 +02:00
parent 3e72f87fe7
commit 411ae05f1d
1 changed files with 46 additions and 54 deletions
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56
src/mainboard/google/beltino/romstage.c
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@@ -44,34 +44,25 @@ void mainboard_config_rcba(void)
void mainboard_fill_pei_data(struct pei_data *pei_data) void mainboard_fill_pei_data(struct pei_data *pei_data)
{ {
struct pei_data mainboard_pei_data = { pei_data->system_type = 5; /* ULT */
.pei_version = PEI_VERSION, pei_data->spd_addresses[0] = 0xa0;
.mchbar = (uintptr_t)DEFAULT_MCHBAR, pei_data->spd_addresses[2] = 0xa4;
.dmibar = (uintptr_t)DEFAULT_DMIBAR, pei_data->ec_present = 0;
.epbar = DEFAULT_EPBAR, /*
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS, * 0 = leave channel enabled
.smbusbar = SMBUS_IO_BASE, * 1 = disable dimm 0 on channel
.hpet_address = HPET_ADDR, * 2 = disable dimm 1 on channel
.rcba = (uintptr_t)DEFAULT_RCBA, * 3 = disable dimm 0+1 on channel
.pmbase = DEFAULT_PMBASE, */
.gpiobase = DEFAULT_GPIOBASE, pei_data->dimm_channel0_disabled = 2;
.temp_mmio_base = 0xfed08000, pei_data->dimm_channel1_disabled = 2;
.system_type = 5, /* ULT */ /* Enable 2x refresh mode */
.tseg_size = CONFIG_SMM_TSEG_SIZE, pei_data->ddr_refresh_2x = 1;
.spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 }, pei_data->dq_pins_interleaved = 1;
.ec_present = 0, pei_data->max_ddr3_freq = 1600;
// 0 = leave channel enabled pei_data->usb_xhci_on_resume = 1;
// 1 = disable dimm 0 on channel
// 2 = disable dimm 1 on channel struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
// 3 = disable dimm 0+1 on channel
.dimm_channel0_disabled = 2,
.dimm_channel1_disabled = 2,
// Enable 2x refresh mode
.ddr_refresh_2x = 1,
.dq_pins_interleaved = 1,
.max_ddr3_freq = 1600,
.usb_xhci_on_resume = 1,
.usb2_ports = {
/* Length, Enable, OCn#, Location */ /* Length, Enable, OCn#, Location */
{ 0x0064, 1, 0, /* P0: VP8 */ { 0x0064, 1, 0, /* P0: VP8 */
USB_PORT_MINI_PCIE }, USB_PORT_MINI_PCIE },
@@ -89,15 +80,16 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
USB_PORT_INTERNAL }, USB_PORT_INTERNAL },
{ 0x0000, 0, 0, /* P7: N/C */ { 0x0000, 0, 0, /* P7: N/C */
USB_PORT_SKIP }, USB_PORT_SKIP },
}, };
.usb3_ports = {
struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = {
/* Enable, OCn# */ /* Enable, OCn# */
{ 1, 0 }, /* P1; CN22 */ { 1, 0 }, /* P1; CN22 */
{ 1, 1 }, /* P2; CN23 */ { 1, 1 }, /* P2; CN23 */
{ 1, 2 }, /* P3; CN25 */ { 1, 2 }, /* P3; CN25 */
{ 1, 2 }, /* P4; CN25 */ { 1, 2 }, /* P4; CN25 */
},
}; };
*pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */ memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports));
memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports));
} }