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vendorcode/intel/fsp2/glk: Add the FSP headers for version 2.2.3.1

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Add the headers for 2.2.3.1, which includes the following changes
over 2.2.0.0:
• [Implemented]GLK: XHCLKGTEN Register setting causes S0ix entry
failure in less than 5 cycles when a USB2 Ethernet Dongle is
connected. Refer GLK BIOS Spec Volume1 CDI# 571118 under chapter
7.20.6 for new Register settings.
• [Implemented] [GLK/GLK-R] DDR4 16Gb SDP Memory support for Gemini
Lake/Gemini Lake – R
• [Update] MRC new version update to 1.38.
• [Fixed][GLK-R][WLAN] Removed the DSW function - Wake on LAN from
S4 issue with latest Wifi driver.
[Update] MRC new version update to 1.39. Included fix for
MinRefRate2xEnable and support for Rowhammer mitigation.
• [Fixed] Disable Dynamic DiffAmp and set CTLE from 7 to 5. This
change specific to DDR4 memory configuration.
• GLK Klocwork Fix
• [Update] MRC new version update to 1.40.

Added in a separate directory as the default. The 2.2.0.0 headers
were left and will be used for Google boards, as some offsets have
moved.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I09498368b116c2add816eeada2fa4d0dba6e5765
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Sean Rhodes
2022-05-19 22:02:48 +01:00
committed by Felix Held
parent 234c42f7ed
commit 412222ae75
7 changed files with 2914 additions and 1 deletions
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3
src/soc/intel/apollolake/Kconfig
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@@ -209,7 +209,8 @@ config VERSTAGE_ADDR
The base address (in CAR) where verstage should be linked
config FSP_HEADER_PATH
default "src/vendorcode/intel/fsp/fsp2_0/glk" if SOC_INTEL_GEMINILAKE
default "src/vendorcode/intel/fsp/fsp2_0/glk/2.2.0.0" if VENDOR_GOOGLE && SOC_INTEL_GEMINILAKE
default "src/vendorcode/intel/fsp/fsp2_0/glk/2.2.3.1" if SOC_INTEL_GEMINILAKE
default "3rdparty/fsp/ApolloLakeFspBinPkg/Include/"
config FSP_FD_PATH