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soc/intel/cannonlake: Add support for setting FSP-S PcieRpHotPlug from devicetree

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Tested on system76 galp3-c

Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: I3aa8990a335e413628c016007ebabf7142aef80d
Reviewed-on: https://review.coreboot.org/c/31535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Jeremy Soller
2019-02-20 16:36:13 -07:00
committed by Patrick Georgi
parent eb503296fc
commit 4185de5ff7
2 changed files with 4 additions and 0 deletions
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src/soc/intel/cannonlake/chip.h
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@@ -162,6 +162,8 @@ struct soc_intel_cannonlake_config {
uint8_t PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS];
/* PCIe LTR(Latency Tolerance Reporting) mechanism */
uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
/* Enable/Disable HotPlug support for Root Port */
uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];
/* eMMC and SD */
uint8_t ScsEmmcHs400Enabled;