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src/soc/nvidia: Remove unnecessary space after casts

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Change-Id: I096e88158027ac22cf93a9450c869807dbc14670
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69810
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes Haouas
2022-11-18 15:09:28 +01:00
committed by Felix Held
parent 4d4193dcef
commit 41865cc5b4
5 changed files with 9 additions and 9 deletions
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4
src/soc/nvidia/tegra124/dp.c
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@@ -28,7 +28,7 @@ struct tegra_dc_dp_data dp_data;
static inline u32 tegra_dpaux_readl(struct tegra_dc_dp_data *dp, u32 reg) static inline u32 tegra_dpaux_readl(struct tegra_dc_dp_data *dp, u32 reg)
{ {
void *addr = dp->aux_base + (u32) (reg << 2); void *addr = dp->aux_base + (u32)(reg << 2);
u32 reg_val = READL(addr); u32 reg_val = READL(addr);
return reg_val; return reg_val;
} }
@@ -36,7 +36,7 @@ static inline u32 tegra_dpaux_readl(struct tegra_dc_dp_data *dp, u32 reg)
static inline void tegra_dpaux_writel(struct tegra_dc_dp_data *dp, static inline void tegra_dpaux_writel(struct tegra_dc_dp_data *dp,
u32 reg, u32 val) u32 reg, u32 val)
{ {
void *addr = dp->aux_base + (u32) (reg << 2); void *addr = dp->aux_base + (u32)(reg << 2);
WRITEL(val, addr); WRITEL(val, addr);
} }

4
src/soc/nvidia/tegra124/sor.c
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@@ -42,7 +42,7 @@
static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg) static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg)
{ {
void *addr = sor->base + (u32) (reg << 2); void *addr = sor->base + (u32)(reg << 2);
u32 reg_val = READL(addr); u32 reg_val = READL(addr);
return reg_val; return reg_val;
} }
@@ -50,7 +50,7 @@ static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg)
static inline void tegra_sor_writel(struct tegra_dc_sor_data *sor, static inline void tegra_sor_writel(struct tegra_dc_sor_data *sor,
u32 reg, u32 val) u32 reg, u32 val)
{ {
void *addr = sor->base + (u32) (reg << 2); void *addr = sor->base + (u32)(reg << 2);
WRITEL(val, addr); WRITEL(val, addr);
} }

4
src/soc/nvidia/tegra210/dp.c
View File

@@ -36,7 +36,7 @@ struct tegra_dc_dp_data dp_data;
static inline u32 tegra_dpaux_readl(struct tegra_dc_dp_data *dp, u32 reg) static inline u32 tegra_dpaux_readl(struct tegra_dc_dp_data *dp, u32 reg)
{ {
void *addr = dp->aux_base + (u32) (reg << 2); void *addr = dp->aux_base + (u32)(reg << 2);
u32 reg_val = READL(addr); u32 reg_val = READL(addr);
return reg_val; return reg_val;
} }
@@ -44,7 +44,7 @@ static inline u32 tegra_dpaux_readl(struct tegra_dc_dp_data *dp, u32 reg)
static inline void tegra_dpaux_writel(struct tegra_dc_dp_data *dp, static inline void tegra_dpaux_writel(struct tegra_dc_dp_data *dp,
u32 reg, u32 val) u32 reg, u32 val)
{ {
void *addr = dp->aux_base + (u32) (reg << 2); void *addr = dp->aux_base + (u32)(reg << 2);
WRITEL(val, addr); WRITEL(val, addr);
} }

4
src/soc/nvidia/tegra210/sor.c
View File

@@ -44,7 +44,7 @@
static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg) static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg)
{ {
void *addr = sor->base + (u32) (reg << 2); void *addr = sor->base + (u32)(reg << 2);
u32 reg_val = READL(addr); u32 reg_val = READL(addr);
return reg_val; return reg_val;
} }
@@ -52,7 +52,7 @@ static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg)
static inline void tegra_sor_writel(struct tegra_dc_sor_data *sor, static inline void tegra_sor_writel(struct tegra_dc_sor_data *sor,
u32 reg, u32 val) u32 reg, u32 val)
{ {
void *addr = sor->base + (u32) (reg << 2); void *addr = sor->base + (u32)(reg << 2);
WRITEL(val, addr); WRITEL(val, addr);
} }

2
src/soc/nvidia/tegra210/spi.c
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@@ -478,7 +478,7 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi,
dcache_clean_by_mva(spi->out_buf, bytes); dcache_clean_by_mva(spi->out_buf, bytes);
write32(&spi->dma_out->regs->apb_ptr, write32(&spi->dma_out->regs->apb_ptr,
(uintptr_t) & spi->regs->tx_fifo); (uintptr_t)&spi->regs->tx_fifo);
write32(&spi->dma_out->regs->ahb_ptr, (uintptr_t)spi->out_buf); write32(&spi->dma_out->regs->ahb_ptr, (uintptr_t)spi->out_buf);
setbits32(&spi->dma_out->regs->csr, APB_CSR_DIR); setbits32(&spi->dma_out->regs->csr, APB_CSR_DIR);
setup_dma_params(spi, spi->dma_out); setup_dma_params(spi, spi->dma_out);