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soc/intel/alderlake: Add support to update the FIVR configs

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This patch adds the supports to update the optimal FIVR
configurations for external voltage rails via devicetree.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Icf6c74bda5a167abf63938ebed6affc6b31c76f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55702
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
V Sowmya
2021-06-21 08:47:17 +05:30
committed by Patrick Georgi
parent 912a2353d2
commit 418d37e689
2 changed files with 89 additions and 0 deletions
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40
src/soc/intel/alderlake/fsp_params.c
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@@ -549,6 +549,45 @@ static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg,
printk(BIOS_INFO, "IRQ: Using dynamically assigned PCI IO-APIC IRQs\n");
}
static void fill_fsps_fivr_params(FSP_S_CONFIG *s_cfg,
const struct soc_intel_alderlake_config *config)
{
/* PCH FIVR settings override */
if (!config->ext_fivr_settings.configure_ext_fivr)
return;
s_cfg->PchFivrExtV1p05RailEnabledStates =
config->ext_fivr_settings.v1p05_enable_bitmap;
s_cfg->PchFivrExtV1p05RailSupportedVoltageStates =
config->ext_fivr_settings.v1p05_supported_voltage_bitmap;
s_cfg->PchFivrExtVnnRailEnabledStates =
config->ext_fivr_settings.vnn_enable_bitmap;
s_cfg->PchFivrExtVnnRailSupportedVoltageStates =
config->ext_fivr_settings.vnn_supported_voltage_bitmap;
s_cfg->PchFivrExtVnnRailSxEnabledStates =
config->ext_fivr_settings.vnn_enable_bitmap;
/* Convert the voltages to increments of 2.5mv */
s_cfg->PchFivrExtV1p05RailVoltage =
(config->ext_fivr_settings.v1p05_voltage_mv * 10) / 25;
s_cfg->PchFivrExtVnnRailVoltage =
(config->ext_fivr_settings.vnn_voltage_mv * 10) / 25;
s_cfg->PchFivrExtVnnRailSxVoltage =
(config->ext_fivr_settings.vnn_sx_voltage_mv * 10 / 25);
s_cfg->PchFivrExtV1p05RailIccMaximum =
config->ext_fivr_settings.v1p05_icc_max_ma;
s_cfg->PchFivrExtVnnRailIccMaximum =
config->ext_fivr_settings.vnn_icc_max_ma;
}
static void arch_silicon_init_params(FSPS_ARCH_UPD *s_arch_cfg)
{
/* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */
@@ -583,6 +622,7 @@ static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg,
fill_fsps_pcie_params,
fill_fsps_misc_power_params,
fill_fsps_irq_params,
fill_fsps_fivr_params,
};
for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++)