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mb/google/brya/var/felwinter: Update DPTF parameters for Felwinter

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Follow thermal team design to remove TSR3 sensor and update thermal
table for next build. The DPTF parameters were verified by thermal
team.

BUG=b:219690502
BRANCH=brya
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I0e34fabe546b6eabb3d3adad583668a15a1d908b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This commit is contained in:
John Su
2022-02-16 13:33:05 +08:00
committed by Felix Held
parent d91a6842bf
commit 41994fee94
1 changed files with 10 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

23
src/mainboard/google/brya/variants/felwinter/overridetree.cb
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@@ -78,28 +78,27 @@ chip soc/intel/alderlake
register "options.tsr[0].desc" = ""DRAM_SOC"" register "options.tsr[0].desc" = ""DRAM_SOC""
register "options.tsr[1].desc" = ""Ambient"" register "options.tsr[1].desc" = ""Ambient""
register "options.tsr[2].desc" = ""Charger"" register "options.tsr[2].desc" = ""Charger""
register "options.tsr[3].desc" = ""WWAN""
## Active Policy ## Active Policy
register "policies.active" = "{ register "policies.active" = "{
[0] = { [0] = {
.target = DPTF_CPU, .target = DPTF_CPU,
.thresholds = { .thresholds = {
TEMP_PCT(55, 65), TEMP_PCT(44, 76),
TEMP_PCT(52, 59), TEMP_PCT(40, 65),
TEMP_PCT(49, 50), TEMP_PCT(36, 53),
TEMP_PCT(46, 43), TEMP_PCT(32, 41),
TEMP_PCT(43, 37), TEMP_PCT(28, 29),
} }
}, },
[1] = { [1] = {
.target = DPTF_TEMP_SENSOR_1, .target = DPTF_TEMP_SENSOR_1,
.thresholds = { .thresholds = {
TEMP_PCT(55, 65), TEMP_PCT(44, 76),
TEMP_PCT(52, 59), TEMP_PCT(40, 65),
TEMP_PCT(49, 50), TEMP_PCT(36, 53),
TEMP_PCT(46, 43), TEMP_PCT(32, 41),
TEMP_PCT(43, 37), TEMP_PCT(28, 29),
} }
} }
}" }"
@@ -110,7 +109,6 @@ chip soc/intel/alderlake
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000), [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000),
[3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000),
[4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 75, 5000),
}" }"
## Critical Policy ## Critical Policy
@@ -119,7 +117,6 @@ chip soc/intel/alderlake
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN),
}" }"
register "controls.power_limits" = "{ register "controls.power_limits" = "{