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src: Move common IA-32 MSRs to <cpu/x86/msr.h>

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Use "cpu/x86/msr.h" for common IA-32 MSRs and correct IA-32 MSRs names.

Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28752
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS
2018-10-01 08:47:51 +02:00
committed by Martin Roth
parent 603963e1ba
commit 419bfbc1f1
56 changed files with 129 additions and 264 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
src/cpu/intel/common/common_init.c
View File

@@ -20,10 +20,6 @@
#include <cpu/x86/msr.h>
#include "common.h"
#define IA32_FEATURE_CONTROL 0x3a
#define CPUID_VMX (1 << 5)
#define CPUID_SMX (1 << 6)
void set_vmx(void)
{
struct cpuid_result regs;
@@ -105,7 +101,7 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version)
config->version = version;
msr.addrl = MSR_IA32_HWP_CAPABILITIES;
msr.addrl = IA32_HWP_CAPABILITIES;
/*
* Highest Performance:
@@ -141,7 +137,7 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version)
msr.bit_offset = 8;
config->regs[CPPC_GUARANTEED_PERF] = msr;
msr.addrl = MSR_IA32_HWP_REQUEST;
msr.addrl = IA32_HWP_REQUEST;
/*
* Desired Performance Register:
@@ -182,7 +178,7 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version)
*/
config->regs[CPPC_COUNTER_WRAP] = unsupported;
msr.addrl = MSR_IA32_MPERF;
msr.addrl = IA32_MPERF;
/*
* Reference Performance Counter Register:
@@ -192,7 +188,7 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version)
msr.bit_offset = 0;
config->regs[CPPC_REF_PERF_COUNTER] = msr;
msr.addrl = MSR_IA32_APERF;
msr.addrl = IA32_APERF;
/*
* Delivered Performance Counter Register:
@@ -200,7 +196,7 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version)
*/
config->regs[CPPC_DELIVERED_PERF_COUNTER] = msr;
msr.addrl = MSR_IA32_HWP_STATUS;
msr.addrl = IA32_HWP_STATUS;
/*
* Performance Limited Register:
@@ -210,7 +206,7 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version)
msr.bit_offset = 2;
config->regs[CPPC_PERF_LIMITED] = msr;
msr.addrl = MSR_IA32_PM_ENABLE;
msr.addrl = IA32_PM_ENABLE;
/*
* CPPC Enable Register:

13
src/cpu/intel/fsp_model_206ax/model_206ax.h
View File

@@ -20,25 +20,12 @@
/* SandyBridge/IvyBridge bus clock is fixed at 100MHz */
#define SANDYBRIDGE_BCLK 100
#define IA32_FEATURE_CONTROL 0x3a
#define CPUID_VMX (1 << 5)
#define CPUID_SMX (1 << 6)
#define MSR_FEATURE_CONFIG 0x13c
#define MSR_FLEX_RATIO 0x194
#define FLEX_RATIO_LOCK (1 << 20)
#define FLEX_RATIO_EN (1 << 16)
#define IA32_PLATFORM_DCA_CAP 0x1f8
#define IA32_MISC_ENABLE 0x1a0
#define MSR_TEMPERATURE_TARGET 0x1a2
#define IA32_PERF_CTL 0x199
#define IA32_THERM_INTERRUPT 0x19b
#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
#define ENERGY_POLICY_PERFORMANCE 0
#define ENERGY_POLICY_NORMAL 6
#define ENERGY_POLICY_POWERSAVE 15
#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
#define MSR_LT_LOCK_MEMORY 0x2e7
#define IA32_MC0_STATUS 0x401
#define MSR_PIC_MSG_CONTROL 0x2e
#define MSR_PLATFORM_INFO 0xce

13
src/cpu/intel/fsp_model_406dx/model_406dx.h
View File

@@ -21,25 +21,12 @@
/* Rangeley bus clock is fixed at 100MHz */
#define RANGELEY_BCLK 100
#define IA32_FEATURE_CONTROL 0x3a
#define CPUID_VMX (1 << 5)
#define CPUID_SMX (1 << 6)
#define MSR_FEATURE_CONFIG 0x13c
#define MSR_FLEX_RATIO 0x194
#define FLEX_RATIO_LOCK (1 << 20)
#define FLEX_RATIO_EN (1 << 16)
#define IA32_PLATFORM_DCA_CAP 0x1f8
#define IA32_MISC_ENABLE 0x1a0
#define MSR_TEMPERATURE_TARGET 0x1a2
#define IA32_PERF_CTL 0x199
#define IA32_THERM_INTERRUPT 0x19b
#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
#define ENERGY_POLICY_PERFORMANCE 0
#define ENERGY_POLICY_NORMAL 6
#define ENERGY_POLICY_POWERSAVE 15
#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
#define MSR_LT_LOCK_MEMORY 0x2e7
#define IA32_MC0_STATUS 0x401
#define MSR_NO_EVICT_MODE 0x2e0
#define MSR_PIC_MSG_CONTROL 0x2e

13
src/cpu/intel/haswell/haswell.h
View File

@@ -35,25 +35,12 @@
#define HASWELL_BCLK 100
#define CORE_THREAD_COUNT_MSR 0x35
#define IA32_FEATURE_CONTROL 0x3a
#define CPUID_VMX (1 << 5)
#define CPUID_SMX (1 << 6)
#define MSR_FEATURE_CONFIG 0x13c
#define MSR_FLEX_RATIO 0x194
#define FLEX_RATIO_LOCK (1 << 20)
#define FLEX_RATIO_EN (1 << 16)
#define IA32_PLATFORM_DCA_CAP 0x1f8
#define IA32_MISC_ENABLE 0x1a0
#define MSR_TEMPERATURE_TARGET 0x1a2
#define IA32_PERF_CTL 0x199
#define IA32_THERM_INTERRUPT 0x19b
#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
#define ENERGY_POLICY_PERFORMANCE 0
#define ENERGY_POLICY_NORMAL 6
#define ENERGY_POLICY_POWERSAVE 15
#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
#define MSR_LT_LOCK_MEMORY 0x2e7
#define IA32_MC0_STATUS 0x401
#define MSR_PIC_MSG_CONTROL 0x2e
#define MSR_PLATFORM_INFO 0xce

7
src/cpu/intel/haswell/haswell_init.c
View File

@@ -649,10 +649,10 @@ static void set_energy_perf_bias(u8 policy)
return;
/* Energy Policy is bits 3:0 */
msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);
msr = rdmsr(IA32_ENERGY_PERF_BIAS);
msr.lo &= ~0xf;
msr.lo |= policy & 0xf;
wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);
wrmsr(IA32_ENERGY_PERF_BIAS, msr);
printk(BIOS_DEBUG, "haswell: energy policy set to %u\n",
policy);
@@ -661,11 +661,10 @@ static void set_energy_perf_bias(u8 policy)
static void configure_mca(void)
{
msr_t msr;
const unsigned int mcg_cap_msr = 0x179;
int i;
int num_banks;
msr = rdmsr(mcg_cap_msr);
msr = rdmsr(IA32_MCG_CAP);
num_banks = msr.lo & 0xff;
msr.lo = msr.hi = 0;
/* TODO(adurbin): This should only be done on a cold boot. Also, some

6
src/cpu/intel/model_1067x/model_1067x_init.c
View File

@@ -190,7 +190,7 @@ static void configure_misc(const int eist, const int tm2, const int emttm)
const u32 sub_cstates = cpuid_edx(5);
msr = rdmsr(IA32_MISC_ENABLES);
msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 3); /* TM1 enable */
if (tm2)
msr.lo |= (1 << 13); /* TM2 enable */
@@ -220,11 +220,11 @@ static void configure_misc(const int eist, const int tm2, const int emttm)
if (rdmsr(MSR_FSB_CLOCK_VCC).hi & (1 << (63 - 32)))
msr.hi &= ~(1 << (38 - 32));
wrmsr(IA32_MISC_ENABLES, msr);
wrmsr(IA32_MISC_ENABLE, msr);
if (eist) {
msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */
wrmsr(IA32_MISC_ENABLES, msr);
wrmsr(IA32_MISC_ENABLE, msr);
}
}

1
src/cpu/intel/model_106cx/model_106cx_init.c
View File

@@ -56,7 +56,6 @@ static void configure_c_states(void)
wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr);
}
#define IA32_MISC_ENABLE 0x1a0
static void configure_misc(void)
{
msr_t msr;

13
src/cpu/intel/model_2065x/model_2065x.h
View File

@@ -20,26 +20,13 @@
/* Nehalem bus clock is fixed at 133MHz */
#define NEHALEM_BCLK 133
#define IA32_FEATURE_CONTROL 0x3a
#define CPUID_VMX (1 << 5)
#define CPUID_SMX (1 << 6)
#define MSR_FEATURE_CONFIG 0x13c
#define MSR_FLEX_RATIO 0x194
#define FLEX_RATIO_LOCK (1 << 20)
#define FLEX_RATIO_EN (1 << 16)
#define IA32_PLATFORM_DCA_CAP 0x1f8
#define IA32_MISC_ENABLE 0x1a0
#define MSR_TEMPERATURE_TARGET 0x1a2
#define IA32_FERR_CAPABILITY 0x1f1
#define FERR_ENABLE (1 << 0)
#define IA32_PERF_CTL 0x199
#define IA32_THERM_INTERRUPT 0x19b
#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
#define ENERGY_POLICY_PERFORMANCE 0
#define ENERGY_POLICY_NORMAL 6
#define ENERGY_POLICY_POWERSAVE 15
#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
#define IA32_MC0_STATUS 0x401
#define MSR_PIC_MSG_CONTROL 0x2e
#define MSR_PLATFORM_INFO 0xce

4
src/cpu/intel/model_2065x/model_2065x_init.c
View File

@@ -231,10 +231,10 @@ static void set_energy_perf_bias(u8 policy)
msr_t msr;
/* Energy Policy is bits 3:0 */
msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);
msr = rdmsr(IA32_ENERGY_PERF_BIAS);
msr.lo &= ~0xf;
msr.lo |= policy & 0xf;
wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);
wrmsr(IA32_ENERGY_PERF_BIAS, msr);
printk(BIOS_DEBUG, "model_x06ax: energy policy set to %u\n",
policy);

2
src/cpu/intel/model_206ax/common.c
View File

@@ -19,8 +19,6 @@
#include <cpu/x86/msr.h>
#include "model_206ax.h"
#define IA32_PLATFORM_ID 0x17
int get_platform_id(void)
{
msr_t msr;

15
src/cpu/intel/model_206ax/model_206ax.h
View File

@@ -20,27 +20,12 @@
/* SandyBridge/IvyBridge bus clock is fixed at 100MHz */
#define SANDYBRIDGE_BCLK 100
#define IA32_FEATURE_CONTROL 0x3a
#define CPUID_VMX (1 << 5)
#define CPUID_SMX (1 << 6)
#define MSR_FEATURE_CONFIG 0x13c
#define MSR_FLEX_RATIO 0x194
#define FLEX_RATIO_LOCK (1 << 20)
#define FLEX_RATIO_EN (1 << 16)
#define IA32_PLATFORM_DCA_CAP 0x1f8
#define IA32_MISC_ENABLE 0x1a0
#define MSR_TEMPERATURE_TARGET 0x1a2
#define IA32_PERF_CTL 0x199
#define IA32_THERM_INTERRUPT 0x19b
#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
#define ENERGY_POLICY_PERFORMANCE 0
#define ENERGY_POLICY_NORMAL 6
#define ENERGY_POLICY_POWERSAVE 15
#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
#define MSR_LT_LOCK_MEMORY 0x2e7
#define IA32_MC0_STATUS 0x401
#define IA32_MCG_CAP 0x179
#define MSR_PIC_MSG_CONTROL 0x2e
#define MSR_PLATFORM_INFO 0xce
#define PLATFORM_INFO_SET_TDP (1 << 29)

4
src/cpu/intel/model_206ax/model_206ax_init.c
View File

@@ -401,10 +401,10 @@ static void set_energy_perf_bias(u8 policy)
msr_t msr;
/* Energy Policy is bits 3:0 */
msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);
msr = rdmsr(IA32_ENERGY_PERF_BIAS);
msr.lo &= ~0xf;
msr.lo |= policy & 0xf;
wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);
wrmsr(IA32_ENERGY_PERF_BIAS, msr);
printk(BIOS_DEBUG, "model_x06ax: energy policy set to %u\n",
policy);

1
src/cpu/intel/model_6ex/model_6ex_init.c
View File

@@ -58,7 +58,6 @@ static void configure_c_states(void)
wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr);
}
#define IA32_MISC_ENABLE 0x1a0
static void configure_misc(void)
{
msr_t msr;

1
src/cpu/intel/model_6fx/model_6fx_init.c
View File

@@ -59,7 +59,6 @@ static void configure_c_states(void)
wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr);
}
#define IA32_MISC_ENABLE 0x1a0
#define IA32_PECI_CTL 0x5a0
static void configure_misc(void)

4
src/cpu/intel/smm/gen1/smmrelocate.c
View File

@@ -36,10 +36,6 @@
#define G_SMRAME (1 << 3)
#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
#define IA32_FEATURE_CONTROL 0x3a
#define FEATURE_CONTROL_LOCK_BIT (1 << 0)
#define SMRR_ENABLE (1 << 3)
struct ied_header {
char signature[10];
u32 size;

2
src/cpu/intel/speedstep/speedstep.c
View File

@@ -72,7 +72,7 @@ static void speedstep_get_limits(sst_params_t *const params)
msr = rdmsr(MSR_FSB_CLOCK_VCC);
if ((msr.hi & (1 << (63 - 32))) &&
/* supported and */
!(rdmsr(IA32_MISC_ENABLES).hi & (1 << (38 - 32)))) {
!(rdmsr(IA32_MISC_ENABLE).hi & (1 << (38 - 32)))) {
/* not disabled */
params->turbo = SPEEDSTEP_STATE_FROM_MSR(msr.hi, state_mask);
params->turbo.is_turbo = 1;

10
src/cpu/intel/turbo/turbo.c
View File

@@ -68,7 +68,7 @@ int get_turbo_state(void)
cpuid_regs = cpuid(CPUID_LEAF_PM);
turbo_cap = !!(cpuid_regs.eax & PM_CAP_TURBO_MODE);
msr = rdmsr(MSR_IA32_MISC_ENABLES);
msr = rdmsr(IA32_MISC_ENABLE);
turbo_en = !(msr.hi & H_MISC_DISABLE_TURBO);
if (!turbo_cap && turbo_en) {
@@ -97,9 +97,9 @@ void enable_turbo(void)
/* Only possible if turbo is available but hidden */
if (get_turbo_state() == TURBO_DISABLED) {
/* Clear Turbo Disable bit in Misc Enables */
msr = rdmsr(MSR_IA32_MISC_ENABLES);
msr = rdmsr(IA32_MISC_ENABLE);
msr.hi &= ~H_MISC_DISABLE_TURBO;
wrmsr(MSR_IA32_MISC_ENABLES, msr);
wrmsr(IA32_MISC_ENABLE, msr);
/* Update cached turbo state */
set_global_turbo_state(TURBO_ENABLED);
@@ -115,9 +115,9 @@ void disable_turbo(void)
msr_t msr;
/* Set Turbo Disable bit in Misc Enables */
msr = rdmsr(MSR_IA32_MISC_ENABLES);
msr = rdmsr(IA32_MISC_ENABLE);
msr.hi |= H_MISC_DISABLE_TURBO;
wrmsr(MSR_IA32_MISC_ENABLES, msr);
wrmsr(IA32_MISC_ENABLE, msr);
/* Update cached turbo state */
set_global_turbo_state(TURBO_UNAVAILABLE);

25
src/cpu/via/nano/nano_init.c
View File

@@ -28,9 +28,6 @@
#define MODEL_NANO_3000_B0 0x8
#define MODEL_NANO_3000_B2 0xa
#define MSR_IA32_PERF_STATUS 0x00000198
#define MSR_IA32_PERF_CTL 0x00000199
#define MSR_IA32_MISC_ENABLE 0x000001a0
#define NANO_MYSTERIOUS_MSR 0x120e
static void nano_finish_fid_vid_transition(void)
@@ -41,7 +38,7 @@ static void nano_finish_fid_vid_transition(void)
int cnt = 0;
do {
udelay(16);
msr = rdmsr(MSR_IA32_PERF_STATUS);
msr = rdmsr(IA32_PERF_STATUS);
cnt++;
if (cnt > 128) {
printk(BIOS_WARNING,
@@ -61,7 +58,7 @@ static void nano_set_max_fid_vid(void)
{
msr_t msr;
/* Get voltage and frequency info */
msr = rdmsr(MSR_IA32_PERF_STATUS);
msr = rdmsr(IA32_PERF_STATUS);
u8 min_fid = (msr.hi >> 24);
u8 max_fid = (msr.hi >> 8) & 0xff;
u8 min_vid = (msr.hi >> 16) & 0xff;
@@ -78,7 +75,7 @@ static void nano_set_max_fid_vid(void)
/* Set highest frequency and VID */
msr.lo = msr.hi;
msr.hi = 0;
wrmsr(MSR_IA32_PERF_CTL, msr);
wrmsr(IA32_PERF_CTL, msr);
/* Wait for the transition to complete, otherwise, the CPU
* might reset itself repeatedly */
nano_finish_fid_vid_transition();
@@ -96,9 +93,9 @@ static void nano_power(void)
{
msr_t msr;
/* Enable Powersaver */
msr = rdmsr(MSR_IA32_MISC_ENABLE);
msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 16);
wrmsr(MSR_IA32_MISC_ENABLE, msr);
wrmsr(IA32_MISC_ENABLE, msr);
/* Enable 6 bit or 7-bit VRM support
* This MSR is not documented by VIA docs, other than setting these
@@ -116,24 +113,24 @@ static void nano_power(void)
nano_set_max_fid_vid();
/* Enable TM3 */
msr = rdmsr(MSR_IA32_MISC_ENABLE);
msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= ( (1 << 3) | (1 << 13) );
wrmsr(MSR_IA32_MISC_ENABLE, msr);
wrmsr(IA32_MISC_ENABLE, msr);
u8 stepping = ( cpuid_eax(0x1) ) &0xf;
if (stepping >= MODEL_NANO_3000_B0) {
/* Hello Nano 3000. The Terminator needs a CPU upgrade */
/* Enable C1e, C2e, C3e, and C4e states */
msr = rdmsr(MSR_IA32_MISC_ENABLE);
msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= ( (1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */
msr.hi |= (1 << 0); /* C4e */
wrmsr(MSR_IA32_MISC_ENABLE, msr);
wrmsr(IA32_MISC_ENABLE, msr);
}
/* Lock on Powersaver */
msr = rdmsr(MSR_IA32_MISC_ENABLE);
msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 20);
wrmsr(MSR_IA32_MISC_ENABLE, msr);
wrmsr(IA32_MISC_ENABLE, msr);
}
static void nano_init(struct device *dev)

2
src/cpu/via/nano/update_ucode.c
View File

@@ -32,7 +32,7 @@ static ucode_update_status nano_apply_ucode(const nano_ucode_header *ucode)
* not the header. The header is just there to help us. */
msr.lo = (unsigned int)(&(ucode->ucode_start));
msr.hi = 0;
wrmsr(MSR_IA32_BIOS_UPDT_TRIG, msr);
wrmsr(IA32_BIOS_UPDT_TRIG, msr);
/* Let's see if we updated successfully */
msr = rdmsr(MSR_UCODE_UPDATE_STATUS);

2
src/cpu/via/nano/update_ucode.h
View File

@@ -18,8 +18,6 @@
#include <cpu/cpu.h>
#define MSR_IA32_BIOS_UPDT_TRIG 0x00000079
#define MSR_IA32_BIOS_SIGN_ID 0x0000008b
#define MSR_UCODE_UPDATE_STATUS 0x00001205
#define NANO_UCODE_SIGNATURE 0x53415252

2
src/cpu/x86/pae/pgtbl.c
View File

@@ -183,7 +183,7 @@ void paging_set_pat(uint64_t pat)
msr_t msr;
msr.lo = pat;
msr.hi = pat >> 32;
wrmsr(MSR_IA32_PAT, msr);
wrmsr(IA32_PAT, msr);
}
/* PAT encoding used in util/x86/x86_page_tables.go. It matches the linux

6
src/cpu/x86/sipi_vector.S
View File

@@ -16,6 +16,7 @@
#include <cpu/x86/cr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/x86/msr.h>
/* The SIPI vector is responsible for initializing the APs in the system. It
* loads microcode, sets up MSRs, and enables caching before calling into
@@ -25,9 +26,6 @@
#define CODE_SEG 0x10
#define DATA_SEG 0x18
#define IA32_UPDT_TRIG 0x79
#define IA32_BIOS_SIGN_ID 0x8b
.section ".module_parameters", "aw", @progbits
ap_start_params:
gdtaddr:
@@ -145,7 +143,7 @@ lock_microcode:
load_microcode:
/* Load new microcode. */
mov $IA32_UPDT_TRIG, %ecx
mov $IA32_BIOS_UPDT_TRIG, %ecx
xor %edx, %edx
mov %edi, %eax
/* The microcode pointer is passed in pointing to the header. Adjust