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src: Move common IA-32 MSRs to <cpu/x86/msr.h>

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Use "cpu/x86/msr.h" for common IA-32 MSRs and correct IA-32 MSRs names.

Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28752
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS
2018-10-01 08:47:51 +02:00
committed by Martin Roth
parent 603963e1ba
commit 419bfbc1f1
56 changed files with 129 additions and 264 deletions
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16
src/cpu/intel/common/common_init.c
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@@ -20,10 +20,6 @@
#include <cpu/x86/msr.h>
#include "common.h"
#define IA32_FEATURE_CONTROL 0x3a
#define CPUID_VMX (1 << 5)
#define CPUID_SMX (1 << 6)
void set_vmx(void)
{
struct cpuid_result regs;
@@ -105,7 +101,7 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version)
config->version = version;
msr.addrl = MSR_IA32_HWP_CAPABILITIES;
msr.addrl = IA32_HWP_CAPABILITIES;
/*
* Highest Performance:
@@ -141,7 +137,7 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version)
msr.bit_offset = 8;
config->regs[CPPC_GUARANTEED_PERF] = msr;
msr.addrl = MSR_IA32_HWP_REQUEST;
msr.addrl = IA32_HWP_REQUEST;
/*
* Desired Performance Register:
@@ -182,7 +178,7 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version)
*/
config->regs[CPPC_COUNTER_WRAP] = unsupported;
msr.addrl = MSR_IA32_MPERF;
msr.addrl = IA32_MPERF;
/*
* Reference Performance Counter Register:
@@ -192,7 +188,7 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version)
msr.bit_offset = 0;
config->regs[CPPC_REF_PERF_COUNTER] = msr;
msr.addrl = MSR_IA32_APERF;
msr.addrl = IA32_APERF;
/*
* Delivered Performance Counter Register:
@@ -200,7 +196,7 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version)
*/
config->regs[CPPC_DELIVERED_PERF_COUNTER] = msr;
msr.addrl = MSR_IA32_HWP_STATUS;
msr.addrl = IA32_HWP_STATUS;
/*
* Performance Limited Register:
@@ -210,7 +206,7 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version)
msr.bit_offset = 2;
config->regs[CPPC_PERF_LIMITED] = msr;
msr.addrl = MSR_IA32_PM_ENABLE;
msr.addrl = IA32_PM_ENABLE;
/*
* CPPC Enable Register: