src: Move common IA-32 MSRs to <cpu/x86/msr.h>
Use "cpu/x86/msr.h" for common IA-32 MSRs and correct IA-32 MSRs names. Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28752 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Martin Roth
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@@ -19,8 +19,6 @@
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#include <cpu/x86/msr.h>
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#include "model_206ax.h"
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#define IA32_PLATFORM_ID 0x17
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int get_platform_id(void)
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{
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msr_t msr;
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@@ -20,27 +20,12 @@
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/* SandyBridge/IvyBridge bus clock is fixed at 100MHz */
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#define SANDYBRIDGE_BCLK 100
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#define IA32_FEATURE_CONTROL 0x3a
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#define CPUID_VMX (1 << 5)
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#define CPUID_SMX (1 << 6)
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#define MSR_FEATURE_CONFIG 0x13c
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#define MSR_FLEX_RATIO 0x194
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#define FLEX_RATIO_LOCK (1 << 20)
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#define FLEX_RATIO_EN (1 << 16)
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#define IA32_PLATFORM_DCA_CAP 0x1f8
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#define IA32_MISC_ENABLE 0x1a0
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#define MSR_TEMPERATURE_TARGET 0x1a2
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#define IA32_PERF_CTL 0x199
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#define IA32_THERM_INTERRUPT 0x19b
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#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
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#define ENERGY_POLICY_PERFORMANCE 0
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#define ENERGY_POLICY_NORMAL 6
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#define ENERGY_POLICY_POWERSAVE 15
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#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
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#define MSR_LT_LOCK_MEMORY 0x2e7
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#define IA32_MC0_STATUS 0x401
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#define IA32_MCG_CAP 0x179
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#define MSR_PIC_MSG_CONTROL 0x2e
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#define MSR_PLATFORM_INFO 0xce
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#define PLATFORM_INFO_SET_TDP (1 << 29)
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@@ -401,10 +401,10 @@ static void set_energy_perf_bias(u8 policy)
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msr_t msr;
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/* Energy Policy is bits 3:0 */
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msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);
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msr = rdmsr(IA32_ENERGY_PERF_BIAS);
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msr.lo &= ~0xf;
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msr.lo |= policy & 0xf;
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wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);
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wrmsr(IA32_ENERGY_PERF_BIAS, msr);
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printk(BIOS_DEBUG, "model_x06ax: energy policy set to %u\n",
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policy);
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