soc/intel/apollolake: add option for SLP_S3_L assertion width

In order to provide time for the S0 rails to discharge one needs
to be able to set the SLP_S3_L assertion width. The hardware default
is 60 microcseconds which is not slow enough on most boards. Therefore
provide a devicetree option for the mainboard to set accordingly
for its needs. An unset value in devicetree results in a conservative
2 second SLP_S3_L duration.

BUG=chrome-os-partner:56581

Change-Id: I6c6df2f7a181746708ab7897249ae82109c55f50
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16326
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>

src/soc/intel/apollolake/chip.h

@@ -106,6 +106,9 @@ struct soc_intel_apollolake_config {
 
 	/* Enable DPTF support */
 	int dptf_enable;
+
+	/* SLP S3 minimum assertion width. */
+	int slp_s3_assertion_width_usecs;
 };
 
 #endif	/* _SOC_APOLLOLAKE_CHIP_H_ */