diff --git a/src/mainboard/amd/bilby/dsdt.asl b/src/mainboard/amd/bilby/dsdt.asl
index dd42608162..57ee5d63a9 100644
--- a/src/mainboard/amd/bilby/dsdt.asl
+++ b/src/mainboard/amd/bilby/dsdt.asl
@@ -14,25 +14,7 @@ DefinitionBlock (
 	)
 {	/* Start of ASL file */
 	#include <acpi/dsdt_top.asl>
-	#include <globalnvs.asl>
 
-	/* Power state notification to ALIB */
-	#include <pnot.asl>
-
-	/* Contains the supported sleep states for this chipset */
-	#include <soc/amd/common/acpi/sleepstates.asl>
-
-	/* Contains _SWS methods */
-	#include <soc/amd/common/acpi/acpi_wake_source.asl>
-
-	/* System Bus */
-	Scope(\_SB) { /* Start \_SB scope */
-		/* global utility methods expected within the \_SB scope */
-		#include <arch/x86/acpi/globutil.asl>
-
-		/* Describe the SOC */
-		#include <soc.asl>
-
-	} /* End \_SB scope */
+	#include <soc.asl>
 }
 /* End of ASL file */
diff --git a/src/mainboard/amd/mandolin/dsdt.asl b/src/mainboard/amd/mandolin/dsdt.asl
index dd42608162..57ee5d63a9 100644
--- a/src/mainboard/amd/mandolin/dsdt.asl
+++ b/src/mainboard/amd/mandolin/dsdt.asl
@@ -14,25 +14,7 @@ DefinitionBlock (
 	)
 {	/* Start of ASL file */
 	#include <acpi/dsdt_top.asl>
-	#include <globalnvs.asl>
 
-	/* Power state notification to ALIB */
-	#include <pnot.asl>
-
-	/* Contains the supported sleep states for this chipset */
-	#include <soc/amd/common/acpi/sleepstates.asl>
-
-	/* Contains _SWS methods */
-	#include <soc/amd/common/acpi/acpi_wake_source.asl>
-
-	/* System Bus */
-	Scope(\_SB) { /* Start \_SB scope */
-		/* global utility methods expected within the \_SB scope */
-		#include <arch/x86/acpi/globutil.asl>
-
-		/* Describe the SOC */
-		#include <soc.asl>
-
-	} /* End \_SB scope */
+	#include <soc.asl>
 }
 /* End of ASL file */
diff --git a/src/mainboard/google/zork/dsdt.asl b/src/mainboard/google/zork/dsdt.asl
index dc4322daee..4cb85069b7 100644
--- a/src/mainboard/google/zork/dsdt.asl
+++ b/src/mainboard/google/zork/dsdt.asl
@@ -18,26 +18,7 @@ DefinitionBlock (
 
 	Name(LIDS, 0)
 
-	#include <globalnvs.asl>
-
-	/* Power state notification to ALIB */
-	#include <pnot.asl>
-
-	/* Contains the supported sleep states for this chipset */
-	#include <soc/amd/common/acpi/sleepstates.asl>
-
-	/* Contains _SWS methods */
-	#include <soc/amd/common/acpi/acpi_wake_source.asl>
-
-	/* System Bus */
-	Scope(\_SB) { /* Start \_SB scope */
-		/* global utility methods expected within the \_SB scope */
-		#include <arch/x86/acpi/globutil.asl>
-
-		/* Describe the SOC */
-		#include <soc.asl>
-
-	} /* End \_SB scope */
+	#include <soc.asl>
 
 	/* Thermal handler */
 	#include <variant/acpi/thermal.asl>
diff --git a/src/soc/amd/picasso/acpi/soc.asl b/src/soc/amd/picasso/acpi/soc.asl
index a958570905..7c13f0863e 100644
--- a/src/soc/amd/picasso/acpi/soc.asl
+++ b/src/soc/amd/picasso/acpi/soc.asl
@@ -1,30 +1,47 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <soc/amd/common/acpi/pci_root.asl>
+#include "globalnvs.asl"
 
-ROOT_BRIDGE(PCI0)
+/* Power state notification to ALIB */
+#include "pnot.asl"
 
-Scope(PCI0) {
-	/* Describe the AMD Northbridge */
-	#include "northbridge.asl"
+/* Contains the supported sleep states for this chipset */
+#include <soc/amd/common/acpi/sleepstates.asl>
 
-	/* Describe the AMD Fusion Controller Hub */
-	#include <soc/amd/common/acpi/lpc.asl>
-	#include <soc/amd/common/acpi/platform.asl>
-}
+/* Contains _SWS methods */
+#include <soc/amd/common/acpi/acpi_wake_source.asl>
 
-/* PCI IRQ mapping for the Southbridge */
-#include "pci_int_defs.asl"
+/* System Bus */
+Scope(\_SB) { /* Start \_SB scope */
+	/* global utility methods expected within the \_SB scope */
+	#include <arch/x86/acpi/globutil.asl>
 
-/* Describe PCI INT[A-H] for the Southbridge */
-#include <soc/amd/common/acpi/pci_int.asl>
+	ROOT_BRIDGE(PCI0)
 
-/* Describe the MMIO devices in the FCH */
-#include "mmio.asl"
+	Scope(PCI0) {
+		/* Describe the AMD Northbridge */
+		#include "northbridge.asl"
 
-/* Add GPIO library */
-#include <soc/amd/common/acpi/gpio_bank_lib.asl>
+		/* Describe the AMD Fusion Controller Hub */
+		#include <soc/amd/common/acpi/lpc.asl>
+		#include <soc/amd/common/acpi/platform.asl>
+	}
 
-#if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)
-#include <soc/amd/common/acpi/dptc.asl>
-#endif
+	/* PCI IRQ mapping for the Southbridge */
+	#include "pci_int_defs.asl"
+
+	/* Describe PCI INT[A-H] for the Southbridge */
+	#include <soc/amd/common/acpi/pci_int.asl>
+
+	/* Describe the MMIO devices in the FCH */
+	#include "mmio.asl"
+
+	/* Add GPIO library */
+	#include <soc/amd/common/acpi/gpio_bank_lib.asl>
+
+	#if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)
+	#include <soc/amd/common/acpi/dptc.asl>
+	#endif
+
+} /* End \_SB scope */