From 41b92819f33e249fb7148b9f634b2efb7be8d9fc Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Wed, 22 Feb 2023 12:40:46 -0700 Subject: [PATCH] gaze18 and oryp11: Fix CPU root port definitions Change-Id: I1d1834786b08f2b8ba00642477dd26d9d1201e0f --- src/mainboard/system76/rpl/variants/gaze18/overridetree.cb | 6 +++--- src/mainboard/system76/rpl/variants/oryp11/overridetree.cb | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/system76/rpl/variants/gaze18/overridetree.cb b/src/mainboard/system76/rpl/variants/gaze18/overridetree.cb index 3e21e2ee89..241428dcc0 100644 --- a/src/mainboard/system76/rpl/variants/gaze18/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/gaze18/overridetree.cb @@ -20,15 +20,15 @@ chip soc/intel/alderlake device ref pcie5_0 on # CPU PCIe RP#2 x8, Clock 3 (GPU) - register "pch_pcie_rp[CPU_RP(2)]" = "{ + register "cpu_pcie_rp[CPU_RP(2)]" = "{ .clk_src = 3, .clk_req = 3, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end device ref pcie4_0 on - # PCIE PEG0 x4, Clock 0 (SSD0) - register "pch_pcie_rp[CPU_RP(1)]" = "{ + # CPU RP#1 x4, Clock 0 (SSD0) + register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_src = 0, .clk_req = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, diff --git a/src/mainboard/system76/rpl/variants/oryp11/overridetree.cb b/src/mainboard/system76/rpl/variants/oryp11/overridetree.cb index 102ddf7f88..6be05386fb 100644 --- a/src/mainboard/system76/rpl/variants/oryp11/overridetree.cb +++ b/src/mainboard/system76/rpl/variants/oryp11/overridetree.cb @@ -20,7 +20,7 @@ chip soc/intel/alderlake device ref pcie5_0 on # CPU PCIe RP#2 x8, Clock 3 (GPU) - register "pch_pcie_rp[CPU_RP(2)]" = "{ + register "cpu_pcie_rp[CPU_RP(2)]" = "{ .clk_src = 3, .clk_req = 3, .flags = PCIE_RP_LTR | PCIE_RP_AER, @@ -28,7 +28,7 @@ chip soc/intel/alderlake end device ref pcie4_0 on # CPU RP#1 x4, Clock 0 (SSD2) - register "pch_pcie_rp[CPU_RP(1)]" = "{ + register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_src = 0, .clk_req = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, @@ -36,7 +36,7 @@ chip soc/intel/alderlake end device ref pcie4_1 on # PCIE RP#3 x4, Clock 4 (SSD1) - register "pch_pcie_rp[CPU_RP(3)]" = "{ + register "cpu_pcie_rp[CPU_RP(3)]" = "{ .clk_src = 4, .clk_req = 4, .flags = PCIE_RP_LTR | PCIE_RP_AER,