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soc/amd/stoneyridge: Remove dev_find_slot where possible

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The procedure dev_find_slot has 3 main uses. To find configuration
(devicetree), to verify if a particular device is enabled at build \
time, and to get the address for PCI access while in bootblock/romstage.
The third use can be hidden by using macros defined in pci_devs.h,
making it very clear what PCI device is being accessed. replace the
temporary pointers to device used with PCI access with SOC_XXX_DEV where
XXX is the device being accessed, and remove the setting of the temporary
pointers.

BUG=b:117917136
TEST=Build grunt.

Change-Id: Ic38ea04bfcc1ccaa12937b19e9442a26d869ef11
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Richard Spiegel
2018-10-22 13:57:18 -07:00
committed by Martin Roth
parent 58bf3e7632
commit 41baf0c3ff
4 changed files with 24 additions and 30 deletions
Download Patch File Download Diff File Expand all files Collapse all files

25
src/soc/amd/stoneyridge/northbridge.c
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@@ -48,27 +48,25 @@ static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg,
u32 io_min, u32 io_max)
{
u32 tempreg;
struct device *addr_map = dev_find_slot(0, ADDR_DEVFN);
/* io range allocation. Limit */
tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4)
| ((io_max & 0xf0) << (12 - 4));
pci_write_config32(addr_map, reg + 4, tempreg);
pci_write_config32(SOC_ADDR_DEV, reg + 4, tempreg);
tempreg = 3 | ((io_min & 0xf0) << (12 - 4)); /* base: ISA and VGA ? */
pci_write_config32(addr_map, reg, tempreg);
pci_write_config32(SOC_ADDR_DEV, reg, tempreg);
}
static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index,
u32 mmio_min, u32 mmio_max)
{
u32 tempreg;
struct device *addr_map = dev_find_slot(0, ADDR_DEVFN);
/* io range allocation. Limit */
tempreg = (nodeid & 0xf) | (linkn << 4) | (mmio_max & 0xffffff00);
pci_write_config32(addr_map, reg + 4, tempreg);
pci_write_config32(SOC_ADDR_DEV, reg + 4, tempreg);
tempreg = 3 | (nodeid & 0x30) | (mmio_min & 0xffffff00);
pci_write_config32(addr_map, reg, tempreg);
pci_write_config32(SOC_ADDR_DEV, reg, tempreg);
}
static void read_resources(struct device *dev)
@@ -154,7 +152,7 @@ static void create_vga_resource(struct device *dev)
printk(BIOS_DEBUG, "VGA: %s has VGA device\n", dev_path(dev));
/* Route A0000-BFFFF, IO 3B0-3BB 3C0-3DF */
pci_write_config32(dev_find_slot(0, ADDR_DEVFN), 0xf4, 1);
pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE);
}
static void set_resources(struct device *dev)
@@ -379,17 +377,16 @@ void amd_initcpuio(void)
void fam15_finalize(void *chip_info)
{
struct device *dev;
u32 value;
dev = dev_find_slot(0, GNB_DEVFN); /* clear IoapicSbFeatureEn */
pci_write_config32(dev, 0xf8, 0);
pci_write_config32(dev, 0xfc, 5); /* TODO: move it to dsdt.asl */
/* TODO: move IOAPIC code to dsdt.asl */
pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, 0);
pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, 5);
/* disable No Snoop */
dev = dev_find_slot(0, HDA0_DEVFN);
value = pci_read_config32(dev, HDA_DEV_CTRL_STATUS);
value = pci_read_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS);
value &= ~HDA_NO_SNOOP_EN;
pci_write_config32(dev, HDA_DEV_CTRL_STATUS, value);
pci_write_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS, value);
}
void domain_read_resources(struct device *dev)