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soc/intel: Fix SMRAM base MSR

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Previous setting was correct but assumed SMI handler is
always located at the beginning of TSEG. Break the assumption.

Change-Id: I5da1a36fc95f76fa3225498bbac41b2dd4d1dfec
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34730
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2019-08-05 22:00:08 +03:00
parent d157b3e1e0
commit 41d9b65149
3 changed files with 6 additions and 9 deletions
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5
src/soc/intel/cannonlake/smmrelocate.c
View File

@@ -192,10 +192,9 @@ static void fill_in_relocation_params(struct smm_relocation_params *params)
smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size); smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);
/* SMRR has 32-bits of valid address aligned to 4KiB. */ /* SMRR has 32-bits of valid address aligned to 4KiB. */
params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK; params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK;
params->smrr_base.hi = 0; params->smrr_base.hi = 0;
params->smrr_mask.lo = (~(tseg_size - 1) & rmask) params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID;
| MTRR_PHYS_MASK_VALID;
params->smrr_mask.hi = 0; params->smrr_mask.hi = 0;
/* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */ /* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */

5
src/soc/intel/icelake/smmrelocate.c
View File

@@ -191,10 +191,9 @@ static void fill_in_relocation_params(struct smm_relocation_params *params)
smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size); smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);
/* SMRR has 32-bits of valid address aligned to 4KiB. */ /* SMRR has 32-bits of valid address aligned to 4KiB. */
params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK; params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK;
params->smrr_base.hi = 0; params->smrr_base.hi = 0;
params->smrr_mask.lo = (~(tseg_size - 1) & rmask) params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID;
| MTRR_PHYS_MASK_VALID;
params->smrr_mask.hi = 0; params->smrr_mask.hi = 0;
/* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */ /* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */

5
src/soc/intel/skylake/smmrelocate.c
View File

@@ -201,10 +201,9 @@ static void fill_in_relocation_params(struct smm_relocation_params *params)
smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size); smm_subregion(SMM_SUBREGION_CHIPSET, &params->ied_base, &params->ied_size);
/* SMRR has 32-bits of valid address aligned to 4KiB. */ /* SMRR has 32-bits of valid address aligned to 4KiB. */
params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK; params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK;
params->smrr_base.hi = 0; params->smrr_base.hi = 0;
params->smrr_mask.lo = (~(tseg_size - 1) & rmask) params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID;
| MTRR_PHYS_MASK_VALID;
params->smrr_mask.hi = 0; params->smrr_mask.hi = 0;
/* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */ /* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */