libpayload: add UDC driver for Designware controller
Found in rockchips rk3288 as used in google/veyron. BUG=None TEST=None BRANCH=None Change-Id: I2f2c36c5bea3986a8a37f84c75608b838a8782ae Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 59a0bcd97e8d0f5ce5ac1301910e11b01e2d24b1 Original-Change-Id: Ic89ed54c48d6f9ce125a93caf96471abc6e8cd9d Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/272108 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Lin Huang <hl@rock-chips.com> Original-Tested-by: Lin Huang <hl@rock-chips.com> Reviewed-on: http://review.coreboot.org/10689 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
huang lin
committed by
Patrick Georgi
Patrick Georgi
parent
066cc85e22
commit
41e2499734
@@ -19,621 +19,7 @@
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#ifndef __DWC2_REGS_H__
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#define __DWC2_REGS_H__
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#define MAX_EPS_CHANNELS 16
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typedef struct core_reg {
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uint32_t gotgctl;
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uint32_t gotgint;
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uint32_t gahbcfg;
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uint32_t gusbcfg;
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uint32_t grstctl;
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uint32_t gintsts;
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uint32_t gintmsk;
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uint32_t grxstsr;
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uint32_t grxstsp;
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uint32_t grxfsiz;
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uint32_t gnptxfsiz;
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uint32_t gnptxsts;
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uint32_t gi2cctl;
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uint32_t gpvndctl;
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uint32_t ggpio;
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uint32_t guid;
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uint32_t gsnpsid;
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uint32_t ghwcfg1;
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uint32_t ghwcfg2;
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uint32_t ghwcfg3;
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uint32_t ghwcfg4;
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uint32_t reserved1[(0x100 - 0x54) / 4];
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uint32_t hptxfsiz;
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uint32_t dptxfsiz_dieptxf[15];
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uint32_t reserved2[(0x400 - 0x140) / 4];
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} core_reg_t;
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typedef struct hc_reg {
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uint32_t hccharn;
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uint32_t hcspltn;
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uint32_t hcintn;
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uint32_t hcintmaskn;
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uint32_t hctsizn;
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uint32_t hcdman;
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uint32_t reserved[2];
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} hc_reg_t;
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/* Host Mode Register Structures */
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typedef struct host_reg {
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uint32_t hcfg;
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uint32_t hfir;
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uint32_t hfnum;
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uint32_t reserved0;
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uint32_t hptxsts;
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uint32_t haint;
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uint32_t haintmsk;
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uint32_t reserved1[(0x440 - 0x41c) / 4];
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uint32_t hprt;
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uint32_t reserved2[(0x500 - 0x444) / 4];
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hc_reg_t hchn[MAX_EPS_CHANNELS];
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uint32_t reserved3[(0x800 - 0x700) / 4];
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} host_reg_t;
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/* Device IN ep reg */
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typedef struct in_ep_reg {
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uint32_t diepctl;
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uint32_t reserved04;
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uint32_t diepint;
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uint32_t reserved0c;
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uint32_t dieptsiz;
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uint32_t diepdma;
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uint32_t dtxfsts;
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uint32_t diepdmab;
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} in_ep_reg_t;
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typedef struct out_ep_reg {
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uint32_t doepctl;
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uint32_t reserved04;
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uint32_t doepint;
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uint32_t reserved0c;
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uint32_t doeptsiz;
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uint32_t doepdma;
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uint32_t reserved18;
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uint32_t doepdmab;
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} out_ep_reg_t;
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/* Device Mode Registers Structures */
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typedef struct device_reg {
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uint32_t dcfg;
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uint32_t dctl;
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uint32_t dsts;
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uint32_t unused;
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uint32_t diepmsk;
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uint32_t doepmsk;
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uint32_t daint;
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uint32_t daintmsk;
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uint32_t dtknqr1;
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uint32_t dtknqr2;
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uint32_t dvbusdis;
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uint32_t dvbuspulse;
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uint32_t dtknqr3_dthrctl;
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uint32_t dtknqr4_fifoemptymsk;
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uint32_t reserved1[(0x900 - 0x838) / 4];
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in_ep_reg_t inep[MAX_EPS_CHANNELS];
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out_ep_reg_t outep[MAX_EPS_CHANNELS];
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uint32_t reserved8[(0xe00 - 0xd00) / 4];
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} device_reg_t;
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typedef struct pwr_clk_ctrl_reg {
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uint32_t pcgcctl;
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uint32_t reserved[(0x1000 - 0xe04) / 4];
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} pwr_clk_ctrl_reg_t;
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typedef struct data_fifo {
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uint32_t dataport;
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uint32_t reserved[(0x1000 - 0x004) / 4];
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} data_fifo_t;
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typedef struct dwc2_otg_reg {
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core_reg_t core;
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host_reg_t host;
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device_reg_t device;
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pwr_clk_ctrl_reg_t pcgr;
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data_fifo_t dfifo[MAX_EPS_CHANNELS];
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uint32_t reserved[(0x40000 - 0x11000) / 4];
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} dwc2_reg_t;
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/**
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* This union represents the bit fields of the Core AHB Configuration
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* Register (GAHBCFG).
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*/
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typedef union {
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/* raw register data */
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uint32_t d32;
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/* register bits */
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struct {
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unsigned glblintrmsk:1;
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#define GLBINT_ENABLE 1
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unsigned hbstlen:4;
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#define DMA_BURST_SINGLE 0
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#define DMA_BURST_INCR 1
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#define DMA_BURST_INCR4 3
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#define DMA_BURST_INCR8 5
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#define DMA_BURST_INCR16 7
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unsigned dmaen:1;
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unsigned reserved:1;
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unsigned nptxfemplvl:1;
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unsigned ptxfemplvl:1;
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unsigned reserved9_31:23;
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};
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} gahbcfg_t;
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/**
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* This union represents the bit fields of the Core USB Configuration
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* Register (GUSBCFG).
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*/
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typedef union {
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/* raw register data */
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uint32_t d32;
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/* register bits */
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struct {
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unsigned toutcal:3;
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unsigned phyif:1;
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unsigned ulpiutmisel:1;
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unsigned fsintf:1;
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unsigned physel:1;
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unsigned ddrsel:1;
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unsigned srpcap:1;
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unsigned hnpcap:1;
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unsigned usbtrdtim:4;
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unsigned reserved14:1;
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unsigned phylpwrclksel:1;
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unsigned otgi2csel:1;
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unsigned ulpifsls:1;
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unsigned ulpiautores:1;
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unsigned ulpiclksusm:1;
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unsigned ulpiextvbusdrv:1;
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unsigned ulpiextvbusindicator:1;
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unsigned termseldlpulse:1;
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unsigned reserved23_28:6;
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unsigned forcehstmode:1;
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unsigned forcedevmode:1;
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unsigned cortxpkt:1;
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};
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} gusbcfg_t;
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/**
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* This union represents the bit fields of the Core Reset Register
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* (GRSTCTL).
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*/
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typedef union {
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/* raw register data */
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uint32_t d32;
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/* register bits */
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struct {
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/** Core Soft Reset (CSftRst) (Device and Host)
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*
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* The application can flush the control logic in the
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* entire core using this bit. This bit resets the
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* pipelines in the AHB Clock domain as well as the
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* PHY Clock domain.
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*
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* The state machines are reset to an IDLE state, the
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* control bits in the CSRs are cleared, all the
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* transmit FIFOs and the receive FIFO are flushed.
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*
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* The status mask bits that control the generation of
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* the interrupt, are cleared, to clear the
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* interrupt. The interrupt status bits are not
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* cleared, so the application can get the status of
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* any events that occurred in the core after it has
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* set this bit.
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*
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* Any transactions on the AHB are terminated as soon
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* as possible following the protocol. Any
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* transactions on the USB are terminated immediately.
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*
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* The configuration settings in the CSRs are
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* unchanged, so the software doesn't have to
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* reprogram these registers (Device
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* Configuration/Host Configuration/Core System
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* Configuration/Core PHY Configuration).
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*
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* The application can write to this bit, any time it
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* wants to reset the core. This is a self clearing
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* bit and the core clears this bit after all the
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* necessary logic is reset in the core, which may
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* take several clocks, depending on the current state
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* of the core.
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*/
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unsigned csftrst:1;
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/** Hclk Soft Reset
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*
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* The application uses this bit to reset the control logic in
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* the AHB clock domain. Only AHB clock domain pipelines are
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* reset.
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*/
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unsigned hsftrst:1;
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/** Host Frame Counter Reset (Host Only)<br>
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*
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* The application can reset the (micro)frame number
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* counter inside the core, using this bit. When the
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* (micro)frame counter is reset, the subsequent SOF
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* sent out by the core, will have a (micro)frame
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* number of 0.
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*/
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unsigned frmcntrrst:1;
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/** In Token Sequence Learning Queue Flush
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* (INTknQFlsh) (Device Only)
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*/
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unsigned intknqflsh:1;
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/** RxFIFO Flush (RxFFlsh) (Device and Host)
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*
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* The application can flush the entire Receive FIFO
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* using this bit. <p>The application must first
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* ensure that the core is not in the middle of a
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* transaction. <p>The application should write into
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* this bit, only after making sure that neither the
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* DMA engine is reading from the RxFIFO nor the MAC
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* is writing the data in to the FIFO. <p>The
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* application should wait until the bit is cleared
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* before performing any other operations. This bit
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* will takes 8 clocks (slowest of PHY or AHB clock)
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* to clear.
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*/
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unsigned rxfflsh:1;
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/** TxFIFO Flush (TxFFlsh) (Device and Host).
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*
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* This bit is used to selectively flush a single or
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* all transmit FIFOs. The application must first
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* ensure that the core is not in the middle of a
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* transaction. <p>The application should write into
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* this bit, only after making sure that neither the
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* DMA engine is writing into the TxFIFO nor the MAC
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* is reading the data out of the FIFO. <p>The
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* application should wait until the core clears this
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* bit, before performing any operations. This bit
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* will takes 8 clocks (slowest of PHY or AHB clock)
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* to clear.
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*/
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unsigned txfflsh:1;
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/** TxFIFO Number (TxFNum) (Device and Host).
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*
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* This is the FIFO number which needs to be flushed,
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* using the TxFIFO Flush bit. This field should not
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* be changed until the TxFIFO Flush bit is cleared by
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* the core.
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* - 0x0 : Non Periodic TxFIFO Flush
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* - 0x1 : Periodic TxFIFO #1 Flush in device mode
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* or Periodic TxFIFO in host mode
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* - 0x2 : Periodic TxFIFO #2 Flush in device mode.
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* - ...
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* - 0xF : Periodic TxFIFO #15 Flush in device mode
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* - 0x10: Flush all the Transmit NonPeriodic and
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* Transmit Periodic FIFOs in the core
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*/
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unsigned txfnum:5;
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/** Reserved */
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unsigned reserved11_29:19;
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/** DMA Request Signal. Indicated DMA request is in
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* probress. Used for debug purpose. */
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unsigned dmareq:1;
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/** AHB Master Idle. Indicates the AHB Master State
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* Machine is in IDLE condition. */
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unsigned ahbidle:1;
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} ;
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} grstctl_t;
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/**
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* This union represents the bit fields of the Core Interrupt Mask
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* Register (GINTMSK).
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*/
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typedef union {
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/* raw register data */
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uint32_t d32;
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/* register bits */
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struct {
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unsigned curmod:1;
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unsigned modemis:1;
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unsigned otgint:1;
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unsigned sof:1;
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unsigned rxflvl:1;
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unsigned nptxfemp:1;
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unsigned ginnakeff:1;
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unsigned goutnakeff:1;
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unsigned reserved8:1;
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unsigned i2cint:1;
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unsigned erlysusp:1;
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unsigned usbsusp:1;
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unsigned usbrst:1;
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unsigned enumdone:1;
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unsigned isooutdrop:1;
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unsigned eopf:1;
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unsigned reserved16_20:5;
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unsigned incompip:1;
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unsigned reserved22_23:2;
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unsigned prtint:1;
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unsigned hchint:1;
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unsigned ptxfemp:1;
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unsigned reserved27:1;
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unsigned conidstschng:1;
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unsigned disconnint:1;
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unsigned sessreqint:1;
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unsigned wkupint:1;
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} ;
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} gintmsk_t;
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/**
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* This union represents the bit fields of the Core Non-Periodic
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* Transmit FIFO Size Register(GNPTXFSIZ).
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*/
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typedef union {
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/* raw register data */
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uint32_t d32;
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/* register bits */
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struct {
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unsigned nptxfstaddr:16;
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unsigned nptxfdep:16;
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};
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} gnptxfsiz_t;
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/**
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* This union represents the bit fields of the Core Receive FIFO Size
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* Register(GRXFSIZ).
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*/
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typedef union {
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/* raw register data */
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uint32_t d32;
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/* register bits */
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/*The value in this fieles is in terms of 32-bit words size.
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*/
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struct {
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unsigned rxfdep:16;
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unsigned reserved:16;
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};
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} grxfsiz_t;
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/**
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* This union represents the bit fields of the Core Interrupt Register
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* (GINTSTS).
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*/
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typedef union {
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/* raw register data */
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uint32_t d32;
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#define SOF_INTR_MASK 0x0008
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/* register bits */
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struct {
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unsigned curmod:1;
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#define HOST_MODE 1
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#define DEVICE_MODE 0
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unsigned modemis:1;
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unsigned otgint:1;
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unsigned sof:1;
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unsigned rxflvl:1;
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unsigned nptxfemp:1;
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unsigned ginnakeff:1;
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unsigned goutnakeff:1;
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unsigned reserved8:1;
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unsigned i2cint:1;
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unsigned erlysusp:1;
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unsigned usbsusp:1;
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unsigned usbrst:1;
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unsigned enumdone:1;
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unsigned isooutdrop:1;
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unsigned eopf:1;
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unsigned reserved16_20:5;
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unsigned incompip:1;
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unsigned reserved22_23:2;
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unsigned prtint:1;
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unsigned hchint:1;
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unsigned ptxfemp:1;
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unsigned reserved27:1;
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unsigned conidstschng:1;
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unsigned disconnint:1;
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unsigned sessreqint:1;
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unsigned wkupint:1;
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};
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} gintsts_t;
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/**
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* This union represents the bit fields of the User HW Config3 Register
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* (GHWCFG3).
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*/
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typedef union {
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/* raw register data */
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uint32_t d32;
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/* register bits */
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struct {
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unsigned reserved:16;
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unsigned dfifodepth:16;
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};
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} ghwcfg3_t;
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/**
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* This union represents the bit fields in the Host Configuration Register.
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*/
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typedef union {
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/* raw register data */
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uint32_t d32;
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/* register bits */
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struct {
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/** FS/LS Phy Clock Select */
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unsigned fslspclksel:2;
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#define PHYCLK_30_60_MHZ 0
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#define PHYCLK_48_MHZ 1
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#define PHYCLK_6_MHZ 2
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/** FS/LS Only Support */
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unsigned fslssupp:1;
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};
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} hcfg_t;
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/**
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* This union represents the bit fields in the Host Port Control and status
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* Register.
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*/
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typedef union {
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/* raw register data */
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uint32_t d32;
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/* register bits */
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struct {
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unsigned prtconnsts:1;
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unsigned prtconndet:1;
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unsigned prtena:1;
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unsigned prtenchng:1;
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unsigned prtovrcurract:1;
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unsigned prtovrcurrchng:1;
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unsigned prtres:1;
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unsigned prtsusp:1;
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unsigned prtrst:1;
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unsigned reserved9:1;
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unsigned prtlnsts:2;
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unsigned prtpwr:1;
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unsigned prttstctl:4;
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unsigned prtspd:2;
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#define PRTSPD_HIGH 0
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#define PRTSPD_FULL 1
|
||||
#define PRTSPD_LOW 2
|
||||
unsigned reserved19_31:13;
|
||||
};
|
||||
} hprt_t;
|
||||
/* Mask W1C bits */
|
||||
#define HPRT_W1C_MASK (~((1 << 1) | (1 << 2) | (1 << 3) | (1 << 5)))
|
||||
|
||||
/**
|
||||
* This union represents the bit fields in the Host Channel Characteristics
|
||||
* Register.
|
||||
*/
|
||||
typedef union {
|
||||
/* raw register data */
|
||||
uint32_t d32;
|
||||
|
||||
/* register bits */
|
||||
struct {
|
||||
/** Maximum packet size in bytes */
|
||||
unsigned mps:11;
|
||||
/** Endpoint number */
|
||||
unsigned epnum:4;
|
||||
/** 0: OUT, 1: IN */
|
||||
unsigned epdir:1;
|
||||
unsigned reserved:1;
|
||||
/** 0: Full/high speed device, 1: Low speed device */
|
||||
unsigned lspddev:1;
|
||||
/** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */
|
||||
unsigned eptype:2;
|
||||
/** Packets per frame for periodic transfers. 0 is reserved. */
|
||||
unsigned multicnt:2;
|
||||
/** Device address */
|
||||
unsigned devaddr:7;
|
||||
/**
|
||||
* Frame to transmit periodic transaction.
|
||||
* 0: even, 1: odd
|
||||
*/
|
||||
unsigned oddfrm:1;
|
||||
/** Channel disable */
|
||||
unsigned chdis:1;
|
||||
/** Channel enable */
|
||||
unsigned chen:1;
|
||||
};
|
||||
} hcchar_t;
|
||||
|
||||
typedef enum {
|
||||
EPDIR_OUT = 0,
|
||||
EPDIR_IN,
|
||||
} ep_dir_t;
|
||||
|
||||
/**
|
||||
* This union represents the bit fields in the Host All Interrupt
|
||||
* Register.
|
||||
*/
|
||||
typedef union {
|
||||
/* raw register data */
|
||||
uint32_t d32;
|
||||
/* register bits */
|
||||
struct {
|
||||
/** Transfer Complete */
|
||||
unsigned xfercomp:1;
|
||||
/** Channel Halted */
|
||||
unsigned chhltd:1;
|
||||
/** AHB Error */
|
||||
unsigned ahberr:1;
|
||||
/** STALL Response Received */
|
||||
unsigned stall:1;
|
||||
/** NAK Response Received */
|
||||
unsigned nak:1;
|
||||
/** ACK Response Received */
|
||||
unsigned ack:1;
|
||||
/** NYET Response Received */
|
||||
unsigned nyet:1;
|
||||
/** Transaction Err */
|
||||
unsigned xacterr:1;
|
||||
/** Babble Error */
|
||||
unsigned bblerr:1;
|
||||
/** Frame Overrun */
|
||||
unsigned frmovrun:1;
|
||||
/** Data Toggle Error */
|
||||
unsigned datatglerr:1;
|
||||
/** Reserved */
|
||||
unsigned reserved:21;
|
||||
};
|
||||
} hcint_t;
|
||||
|
||||
/**
|
||||
* This union represents the bit fields in the Host Channel Transfer Size
|
||||
* Register.
|
||||
*/
|
||||
typedef union {
|
||||
/* raw register data */
|
||||
uint32_t d32;
|
||||
|
||||
/* register bits */
|
||||
struct {
|
||||
/* Total transfer size in bytes */
|
||||
unsigned xfersize:19;
|
||||
/** Data packets to transfer */
|
||||
unsigned pktcnt:10;
|
||||
/**
|
||||
* Packet ID for next data packet
|
||||
* 0: DATA0
|
||||
* 1: DATA2
|
||||
* 2: DATA1
|
||||
* 3: MDATA (non-Control), SETUP (Control)
|
||||
*/
|
||||
unsigned pid:2;
|
||||
#define PID_DATA0 0
|
||||
#define PID_DATA1 2
|
||||
#define PID_DATA2 1
|
||||
#define PID_MDATA 3
|
||||
#define PID_SETUP 3
|
||||
/* Do PING protocol when 1 */
|
||||
unsigned dopng:1;
|
||||
};
|
||||
} hctsiz_t;
|
||||
|
||||
/**
|
||||
* This union represents the bit fields in the Host Channel Interrupt Mask
|
||||
* Register.
|
||||
*/
|
||||
typedef union {
|
||||
/* raw register data */
|
||||
uint32_t d32;
|
||||
/* register bits */
|
||||
struct {
|
||||
unsigned xfercomp:1;
|
||||
unsigned chhltd:1;
|
||||
unsigned ahberr:1;
|
||||
unsigned stall:1;
|
||||
unsigned nak:1;
|
||||
unsigned ack:1;
|
||||
unsigned nyet:1;
|
||||
unsigned xacterr:1;
|
||||
unsigned bblerr:1;
|
||||
unsigned frmovrun:1;
|
||||
unsigned datatglerr:1;
|
||||
unsigned reserved:21;
|
||||
};
|
||||
} hcintmsk_t;
|
||||
#include <usb/dwc2_registers.h>
|
||||
|
||||
typedef struct dwc_ctrl {
|
||||
#define DMA_SIZE (64 * 1024)
|
||||
|
||||
Reference in New Issue
Block a user