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mb/system76/tgl-u: Disable SATA DevSlp

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After changing EC detection of S0ix from CPU_C10_GATE# to SLP_S0#,
DevSlp blocks suspend entry. Disable it for now.

Change-Id: I3ac796f1fcdd201bcfc0bff4f02dca379b5b8234
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
2022-11-14 11:38:40 -07:00
committed by Tim Crawford
parent 10bd2a294f
commit 421b2ecbb0
2 changed files with 4 additions and 2 deletions
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3
src/mainboard/system76/tgl-u/variants/darp7/overridetree.cb
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@@ -124,7 +124,8 @@ chip soc/intel/tigerlake
device ref sata on device ref sata on
# SATA1 (SSD0) # SATA1 (SSD0)
register "SataPortsEnable[1]" = "1" register "SataPortsEnable[1]" = "1"
register "SataPortsDevSlp[1]" = "1" # FIXME: DevSlp breaks S0ix
#register "SataPortsDevSlp[1]" = "1"
register "SataPortsEnableDitoConfig[1]" = "1" register "SataPortsEnableDitoConfig[1]" = "1"
register "SataSalpSupport" = "1" register "SataSalpSupport" = "1"
end end

3
src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb
View File

@@ -104,7 +104,8 @@ chip soc/intel/tigerlake
device ref sata on device ref sata on
# SATA1 (SSD2) # SATA1 (SSD2)
register "SataPortsEnable[1]" = "1" register "SataPortsEnable[1]" = "1"
register "SataPortsDevSlp[1]" = "1" # FIXME: DevSlp breaks S0ix
#register "SataPortsDevSlp[1]" = "1"
register "SataPortsEnableDitoConfig[1]" = "1" register "SataPortsEnableDitoConfig[1]" = "1"
register "SataSalpSupport" = "1" register "SataSalpSupport" = "1"
end end