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sc7180: clock: Remove unwanted QUPv3 Frequency

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As the UART clock frequency is no longer required by the UART
driver, remove the unwated frequency.

Tested: Compile and boot up testing.

Change-Id: I137682b3ca45481ad34ac8ddb5cd308444f752a7
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Taniya Das
2020-09-03 23:08:31 +05:30
committed by Julius Werner
parent dcf80ab025
commit 4236187dea
2 changed files with 0 additions and 9 deletions
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8
src/soc/qualcomm/sc7180/clock.c
View File

@@ -11,14 +11,6 @@
#define DIV(div) (2 * div - 1) #define DIV(div) (2 * div - 1)
struct clock_config qup_cfg[] = { struct clock_config qup_cfg[] = {
{
.hz = QUPV3_UART_SRC_HZ,
.src = SRC_GPLL0_EVEN_300MHZ,
.div = DIV(1),
.m = 384,
.n = 15625,
.d_2 = 15625,
},
{ {
.hz = SRC_XO_HZ, /* 19.2KHz */ .hz = SRC_XO_HZ, /* 19.2KHz */
.src = SRC_XO_19_2MHZ, .src = SRC_XO_19_2MHZ,

1
src/soc/qualcomm/sc7180/include/soc/clock.h
View File

@@ -20,7 +20,6 @@
#define SRC_XO_HZ (19200 * KHz) #define SRC_XO_HZ (19200 * KHz)
#define GPLL0_EVEN_HZ (300 * MHz) #define GPLL0_EVEN_HZ (300 * MHz)
#define GPLL0_MAIN_HZ (600 * MHz) #define GPLL0_MAIN_HZ (600 * MHz)
#define QUPV3_UART_SRC_HZ 7372800
#define SRC_XO_19_2MHZ 0 #define SRC_XO_19_2MHZ 0
#define SRC_GPLL0_MAIN_600MHZ 1 #define SRC_GPLL0_MAIN_600MHZ 1