sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/system76/whl-u/dt: Make use of chipset devicetree

Browse Source 
Make use of the alias names defined in the chipset devicetree and remove
devices which are equal to the ones from the chipset devicetree.

Change-Id: Iebe5f8729d463767f5a1b52c375d11bb9d413144
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Felix Singer
2023-11-01 01:55:41 +01:00
parent f67238ef76
commit 4250266bb7
3 changed files with 20 additions and 57 deletions
Download Patch File Download Diff File Expand all files Collapse all files

69
src/mainboard/system76/whl-u/devicetree.cb
View File

@@ -59,18 +59,14 @@ chip soc/intel/cannonlake
device cpu_cluster 0 on end
device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on # Integrated Graphics Device
device ref igpu on
register "gfx" = "GMA_STATIC_DISPLAYS(0)"
end
device pci 04.0 on # SA Thermal device
device ref dptf on
register "Device4Enable" = "1"
end
device pci 12.0 on end # Thermal Subsystem
device pci 12.5 off end # UFS SCS
device pci 12.6 off end # GSPI #2
device pci 13.0 off end # Integrated Sensor Hub
device pci 14.0 on # USB xHCI
device ref thermal on end
device ref xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC_SKIP), /* USB-A */
[1] = USB2_PORT_MID(OC_SKIP), /* 3G / LTE */
@@ -88,39 +84,22 @@ chip soc/intel/cannonlake
[5] = USB3_PORT_EMPTY, /* Used by TBT */
}"
end
device pci 14.1 off end # USB xDCI (OTG)
device pci 14.3 on # CNVi wifi
device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "PME_B0_EN_BIT"
device generic 0 on end
end
end
device pci 14.5 off end # SDCard
device pci 15.0 on end # I2C #0
device pci 15.1 off end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection
device pci 16.4 off end # Management Engine Interface 3
device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 on # SATA
device ref i2c0 on end
device ref sata on
register "SataPortsEnable" = "{
[0] = 1,
[2] = 1,
}"
end
device pci 19.0 off end # I2C #4
device pci 19.1 off end # I2C #5
device pci 19.2 on end # UART #2
device pci 1a.0 off end # eMMC
device pci 1c.0 on end # PCI Express Port 1
device pci 1c.1 off end # PCI Express Port 2
device pci 1c.2 off end # PCI Express Port 3
device pci 1c.3 off end # PCI Express Port 4
device pci 1c.4 on # PCI Express Port 5
device ref uart2 on end
device ref pcie_rp1 on end
device ref pcie_rp5 on
# PCI Express Root port #5 x4, Clock 4 (TBT)
register "PcieRpEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "1"
@@ -128,40 +107,28 @@ chip soc/intel/cannonlake
register "PcieClkSrcUsage[4]" = "4"
register "PcieClkSrcClkReq[4]" = "4"
end
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 on # PCI Express Port 9
device ref pcie_rp9 on
# PCI Express Root port #9 x1, Clock 3 (LAN)
register "PcieRpEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[3]" = "8"
register "PcieClkSrcClkReq[3]" = "3"
end
device pci 1d.1 on # PCI Express Port 10
device ref pcie_rp10 on
# PCI Express Root port #10 x1, Clock 2 (WLAN)
register "PcieRpEnable[9]" = "1"
register "PcieRpLtrEnable[9]" = "0"
register "PcieClkSrcUsage[2]" = "9"
register "PcieClkSrcClkReq[2]" = "2"
end
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
device pci 1d.4 on # PCI Express Port 13
device ref pcie_rp13 on
# PCI Express Root port #13 x4, Clock 5 (NVMe)
register "PcieRpEnable[12]" = "1"
register "PcieRpLtrEnable[12]" = "1"
register "PcieClkSrcUsage[5]" = "12"
register "PcieClkSrcClkReq[5]" = "5"
end
device pci 1d.5 off end # PCI Express Port 14
device pci 1d.6 off end # PCI Express Port 15
device pci 1d.7 off end # PCI Express Port 16
device pci 1e.0 off end # UART #0
device pci 1e.1 off end # UART #1
device pci 1e.2 off end # GSPI #0
device pci 1e.3 off end # GSPI #1
device pci 1f.0 on # LPC Interface
device ref lpc_espi on
register "gen1_dec" = "0x000c0081"
register "gen2_dec" = "0x00040069"
register "gen3_dec" = "0x00fc0e01"
@@ -170,15 +137,11 @@ chip soc/intel/cannonlake
device pnp 0c31.0 on end
end
end
device pci 1f.1 off end # P2SB
device pci 1f.2 hidden end # Power Management Controller
device pci 1f.3 on # Intel HDA
device ref hda on
register "PchHdaAudioLinkHda" = "1"
register "PchHdaAudioLinkDmic0" = "1"
register "PchHdaAudioLinkDmic1" = "1"
end
device pci 1f.4 on end # SMBus
device pci 1f.5 on end # PCH SPI
device pci 1f.6 off end # GbE
device ref smbus on end
end
end

4
src/mainboard/system76/whl-u/variants/darp5/overridetree.cb
View File

@@ -3,7 +3,7 @@
chip soc/intel/cannonlake
device domain 0 on
subsystemid 0x1558 0x1325 inherit
device pci 15.0 on
device ref i2c0 on
chip drivers/i2c/hid
register "generic.hid" = ""SYNA1202""
register "generic.desc" = ""Synaptics Touchpad""
@@ -12,6 +12,6 @@ chip soc/intel/cannonlake
register "hid_desc_reg_offset" = "0x20"
device i2c 2c on end
end
end # I2C #0
end
end
end

4
src/mainboard/system76/whl-u/variants/galp3-c/overridetree.cb
View File

@@ -3,8 +3,8 @@
chip soc/intel/cannonlake
device domain 0 on
subsystemid 0x1558 0x1323 inherit
device pci 15.0 on
device ref i2c0 on
# I2C HID not supported on galp3-c
end # I2C #0
end
end
end