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mb/*/*/devicetree.cb: Normalize disabled PIRQ values

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If bit 7 of a PIRQ route is set, it is disabled. Modern OSes don't use
PIRQ routing, so we might as well zero the other bits for consistency.

Tested on Asrock B85M Pro4 with SeaBIOS 1.13.0, still boots.

Change-Id: I78980b9ea5e878a6200df0f6c18c5e7d06a7950a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43861
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
2020-07-25 13:44:34 +02:00
parent 7417bb0e5a
commit 4276050d13
12 changed files with 57 additions and 57 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/mainboard/intel/baskingridge/devicetree.cb
View File

@@ -32,10 +32,10 @@ chip northbridge/intel/haswell
device pci 02.0 on end # vga controller
chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH
register "pirqa_routing" = "0x8b"
register "pirqb_routing" = "0x8a"
register "pirqc_routing" = "0x8b"
register "pirqd_routing" = "0x8b"
register "pirqa_routing" = "0x80"
register "pirqb_routing" = "0x80"
register "pirqc_routing" = "0x80"
register "pirqd_routing" = "0x80"
register "pirqe_routing" = "0x80"
register "pirqf_routing" = "0x80"
register "pirqg_routing" = "0x80"

8
src/mainboard/intel/wtm2/devicetree.cb
View File

@@ -9,10 +9,10 @@ chip soc/intel/broadwell
# Enable DVI Hotplug with 6ms pulse
register "gpu_dp_b_hotplug" = "0x06"
register "pirqa_routing" = "0x8b"
register "pirqb_routing" = "0x8a"
register "pirqc_routing" = "0x8b"
register "pirqd_routing" = "0x8b"
register "pirqa_routing" = "0x80"
register "pirqb_routing" = "0x80"
register "pirqc_routing" = "0x80"
register "pirqd_routing" = "0x80"
register "pirqe_routing" = "0x80"
register "pirqf_routing" = "0x80"
register "pirqg_routing" = "0x80"