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sb/intel/bd82x6x: Drop P_LVLx support in FADT

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IO MWAIT redirection is not enabled, and C-states are reported using the
_CST ACPI object, which overrides the P_LVLx values.

Change-Id: I737bd58bcda3e7c5f6591e4c2309530ff035e2c8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Angel Pons
2021-06-04 13:00:36 +02:00
committed by Patrick Georgi
parent 685dc56b9f
commit 427e435b9b
9 changed files with 3 additions and 24 deletions
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1
src/southbridge/intel/bd82x6x/chip.h
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@@ -63,7 +63,6 @@ struct southbridge_intel_bd82x6x_config {
/* Override PCIe ASPM */
uint8_t pcie_aspm[8];
int c2_latency;
int docking_supported;
uint8_t pcie_hotplug_map[8];

13
src/southbridge/intel/bd82x6x/fadt.c
View File

@@ -11,7 +11,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
struct device *dev = pcidev_on_root(0x1f, 0);
struct southbridge_intel_bd82x6x_config *chip = dev->chip_info;
u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
int c2_latency;
fadt->sci_int = 0x9;
@@ -32,12 +31,9 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->pm2_cnt_len = 1;
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 16;
c2_latency = chip->c2_latency;
if (!c2_latency) {
c2_latency = 101; /* c2 unsupported */
}
fadt->p_lvl2_lat = c2_latency;
fadt->p_lvl3_lat = 87;
/* P_LVLx not used */
fadt->p_lvl2_lat = 101;
fadt->p_lvl3_lat = 1001;
/* P_CNT not supported */
fadt->duty_offset = 0;
fadt->duty_width = 0;
@@ -55,9 +51,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
if (chip->docking_supported) {
fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
}
if (c2_latency < 100) {
fadt->flags |= ACPI_FADT_C2_MP_SUPPORTED;
}
fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
fadt->x_pm1a_evt_blk.bit_width = 32;