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soc/intel/apollolake: Set PL2 in RAPL register

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This patch sets the package power limit (PL2) value
in RAPL register.

BUG=chrome-os-partner:60535
TEST=Built, booted on reef and verified PL2 value.

Change-Id: I83fe854cf3e9fc92ab87f84b86e64ebb6085065f
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/17699
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Sumeet Pawnikar
2016-12-02 18:14:19 +05:30
committed by Aaron Durbin
parent 256db40b14
commit 428f90afe7
2 changed files with 18 additions and 7 deletions
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2
src/soc/intel/apollolake/chip.h
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@@ -100,6 +100,8 @@ struct soc_intel_apollolake_config {
/* PL1 override value in mW for APL */
uint16_t tdp_pl1_override_mw;
/* PL2 override value in mW for APL */
uint16_t tdp_pl2_override_mw;
/* Configure Audio clk gate and power gate
* IOSF-SB port ID 92 offset 0x530 [5] and [3]